xref: /openbmc/linux/arch/arm64/boot/dts/ti/k3-am642-evm.dts (revision 0afadba435892c8d330e3238b9cc7f9ee8b20e90)
11e6550d3SDave Gerlach// SPDX-License-Identifier: GPL-2.0
21e6550d3SDave Gerlach/*
31e6550d3SDave Gerlach * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
41e6550d3SDave Gerlach */
51e6550d3SDave Gerlach
61e6550d3SDave Gerlach/dts-v1/;
71e6550d3SDave Gerlach
8354065beSKishon Vijay Abraham I#include <dt-bindings/phy/phy.h>
9354065beSKishon Vijay Abraham I#include <dt-bindings/mux/ti-serdes.h>
101e6550d3SDave Gerlach#include <dt-bindings/leds/common.h>
11985204ecSVignesh Raghavendra#include <dt-bindings/gpio/gpio.h>
12985204ecSVignesh Raghavendra#include <dt-bindings/net/ti-dp83867.h>
131e6550d3SDave Gerlach#include "k3-am642.dtsi"
141e6550d3SDave Gerlach
151e6550d3SDave Gerlach/ {
161e6550d3SDave Gerlach	compatible =  "ti,am642-evm", "ti,am642";
171e6550d3SDave Gerlach	model = "Texas Instruments AM642 EVM";
181e6550d3SDave Gerlach
191e6550d3SDave Gerlach	chosen {
201e6550d3SDave Gerlach		stdout-path = "serial2:115200n8";
211e6550d3SDave Gerlach		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
221e6550d3SDave Gerlach	};
231e6550d3SDave Gerlach
241e6550d3SDave Gerlach	memory@80000000 {
251e6550d3SDave Gerlach		device_type = "memory";
261e6550d3SDave Gerlach		/* 2G RAM */
271e6550d3SDave Gerlach		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
281e6550d3SDave Gerlach
291e6550d3SDave Gerlach	};
301e6550d3SDave Gerlach
311e6550d3SDave Gerlach	reserved-memory {
321e6550d3SDave Gerlach		#address-cells = <2>;
331e6550d3SDave Gerlach		#size-cells = <2>;
341e6550d3SDave Gerlach		ranges;
351e6550d3SDave Gerlach
361e6550d3SDave Gerlach		secure_ddr: optee@9e800000 {
371e6550d3SDave Gerlach			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
381e6550d3SDave Gerlach			alignment = <0x1000>;
391e6550d3SDave Gerlach			no-map;
401e6550d3SDave Gerlach		};
411e6550d3SDave Gerlach	};
421e6550d3SDave Gerlach
431e6550d3SDave Gerlach	evm_12v0: fixedregulator-evm12v0 {
441e6550d3SDave Gerlach		/* main DC jack */
451e6550d3SDave Gerlach		compatible = "regulator-fixed";
461e6550d3SDave Gerlach		regulator-name = "evm_12v0";
471e6550d3SDave Gerlach		regulator-min-microvolt = <12000000>;
481e6550d3SDave Gerlach		regulator-max-microvolt = <12000000>;
491e6550d3SDave Gerlach		regulator-always-on;
501e6550d3SDave Gerlach		regulator-boot-on;
511e6550d3SDave Gerlach	};
521e6550d3SDave Gerlach
531e6550d3SDave Gerlach	vsys_5v0: fixedregulator-vsys5v0 {
541e6550d3SDave Gerlach		/* output of LM5140 */
551e6550d3SDave Gerlach		compatible = "regulator-fixed";
561e6550d3SDave Gerlach		regulator-name = "vsys_5v0";
571e6550d3SDave Gerlach		regulator-min-microvolt = <5000000>;
581e6550d3SDave Gerlach		regulator-max-microvolt = <5000000>;
591e6550d3SDave Gerlach		vin-supply = <&evm_12v0>;
601e6550d3SDave Gerlach		regulator-always-on;
611e6550d3SDave Gerlach		regulator-boot-on;
621e6550d3SDave Gerlach	};
631e6550d3SDave Gerlach
641e6550d3SDave Gerlach	vsys_3v3: fixedregulator-vsys3v3 {
651e6550d3SDave Gerlach		/* output of LM5140 */
661e6550d3SDave Gerlach		compatible = "regulator-fixed";
671e6550d3SDave Gerlach		regulator-name = "vsys_3v3";
681e6550d3SDave Gerlach		regulator-min-microvolt = <3300000>;
691e6550d3SDave Gerlach		regulator-max-microvolt = <3300000>;
701e6550d3SDave Gerlach		vin-supply = <&evm_12v0>;
711e6550d3SDave Gerlach		regulator-always-on;
721e6550d3SDave Gerlach		regulator-boot-on;
731e6550d3SDave Gerlach	};
741e6550d3SDave Gerlach
751e6550d3SDave Gerlach	vdd_mmc1: fixed-regulator-sd {
761e6550d3SDave Gerlach		/* TPS2051BD */
771e6550d3SDave Gerlach		compatible = "regulator-fixed";
781e6550d3SDave Gerlach		regulator-name = "vdd_mmc1";
791e6550d3SDave Gerlach		regulator-min-microvolt = <3300000>;
801e6550d3SDave Gerlach		regulator-max-microvolt = <3300000>;
811e6550d3SDave Gerlach		regulator-boot-on;
821e6550d3SDave Gerlach		enable-active-high;
831e6550d3SDave Gerlach		vin-supply = <&vsys_3v3>;
841e6550d3SDave Gerlach		gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
851e6550d3SDave Gerlach	};
861e6550d3SDave Gerlach
871e6550d3SDave Gerlach	vddb: fixedregulator-vddb {
881e6550d3SDave Gerlach		compatible = "regulator-fixed";
891e6550d3SDave Gerlach		regulator-name = "vddb_3v3_display";
901e6550d3SDave Gerlach		regulator-min-microvolt = <3300000>;
911e6550d3SDave Gerlach		regulator-max-microvolt = <3300000>;
921e6550d3SDave Gerlach		vin-supply = <&vsys_3v3>;
931e6550d3SDave Gerlach		regulator-always-on;
941e6550d3SDave Gerlach		regulator-boot-on;
951e6550d3SDave Gerlach	};
961e6550d3SDave Gerlach
971e6550d3SDave Gerlach	leds {
981e6550d3SDave Gerlach		compatible = "gpio-leds";
991e6550d3SDave Gerlach
1001e6550d3SDave Gerlach		led-0 {
1011e6550d3SDave Gerlach			label = "am64-evm:red:heartbeat";
1021e6550d3SDave Gerlach			gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
1031e6550d3SDave Gerlach			linux,default-trigger = "heartbeat";
1041e6550d3SDave Gerlach			function = LED_FUNCTION_HEARTBEAT;
1051e6550d3SDave Gerlach			default-state = "off";
1061e6550d3SDave Gerlach		};
1071e6550d3SDave Gerlach	};
108985204ecSVignesh Raghavendra
109985204ecSVignesh Raghavendra	mdio_mux: mux-controller {
110985204ecSVignesh Raghavendra		compatible = "gpio-mux";
111985204ecSVignesh Raghavendra		#mux-control-cells = <0>;
112985204ecSVignesh Raghavendra
113985204ecSVignesh Raghavendra		mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
114985204ecSVignesh Raghavendra	};
115985204ecSVignesh Raghavendra
116985204ecSVignesh Raghavendra	mdio-mux-1 {
117985204ecSVignesh Raghavendra		compatible = "mdio-mux-multiplexer";
118985204ecSVignesh Raghavendra		mux-controls = <&mdio_mux>;
119985204ecSVignesh Raghavendra		mdio-parent-bus = <&cpsw3g_mdio>;
120985204ecSVignesh Raghavendra		#address-cells = <1>;
121985204ecSVignesh Raghavendra		#size-cells = <0>;
122985204ecSVignesh Raghavendra
123985204ecSVignesh Raghavendra		mdio@1 {
124985204ecSVignesh Raghavendra			reg = <0x1>;
125985204ecSVignesh Raghavendra			#address-cells = <1>;
126985204ecSVignesh Raghavendra			#size-cells = <0>;
127985204ecSVignesh Raghavendra
128985204ecSVignesh Raghavendra			cpsw3g_phy3: ethernet-phy@3 {
129985204ecSVignesh Raghavendra				reg = <3>;
130985204ecSVignesh Raghavendra			};
131985204ecSVignesh Raghavendra		};
132985204ecSVignesh Raghavendra	};
1331e6550d3SDave Gerlach};
1341e6550d3SDave Gerlach
1351e6550d3SDave Gerlach&main_pmx0 {
1361e6550d3SDave Gerlach	main_mmc1_pins_default: main-mmc1-pins-default {
1371e6550d3SDave Gerlach		pinctrl-single,pins = <
1381e6550d3SDave Gerlach			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
1391e6550d3SDave Gerlach			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
1401e6550d3SDave Gerlach			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
1411e6550d3SDave Gerlach			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
1421e6550d3SDave Gerlach			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
1431e6550d3SDave Gerlach			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
1441e6550d3SDave Gerlach			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
1451e6550d3SDave Gerlach			AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
1461e6550d3SDave Gerlach			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
1471e6550d3SDave Gerlach		>;
1481e6550d3SDave Gerlach	};
1491e6550d3SDave Gerlach
1501e6550d3SDave Gerlach	main_uart0_pins_default: main-uart0-pins-default {
1511e6550d3SDave Gerlach		pinctrl-single,pins = <
1521e6550d3SDave Gerlach			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
1531e6550d3SDave Gerlach			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
1541e6550d3SDave Gerlach			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
1551e6550d3SDave Gerlach			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
1561e6550d3SDave Gerlach		>;
1571e6550d3SDave Gerlach	};
1581e6550d3SDave Gerlach
1594fb6c046SAswath Govindraju	main_spi0_pins_default: main-spi0-pins-default {
1604fb6c046SAswath Govindraju		pinctrl-single,pins = <
1614fb6c046SAswath Govindraju			AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
1624fb6c046SAswath Govindraju			AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
1634fb6c046SAswath Govindraju			AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
1644fb6c046SAswath Govindraju			AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
1654fb6c046SAswath Govindraju		>;
1664fb6c046SAswath Govindraju	};
1674fb6c046SAswath Govindraju
1681e6550d3SDave Gerlach	main_i2c1_pins_default: main-i2c1-pins-default {
1691e6550d3SDave Gerlach		pinctrl-single,pins = <
1701e6550d3SDave Gerlach			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
1711e6550d3SDave Gerlach			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
1721e6550d3SDave Gerlach		>;
1731e6550d3SDave Gerlach	};
174985204ecSVignesh Raghavendra
175985204ecSVignesh Raghavendra	mdio1_pins_default: mdio1-pins-default {
176985204ecSVignesh Raghavendra		pinctrl-single,pins = <
177985204ecSVignesh Raghavendra			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
178985204ecSVignesh Raghavendra			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
179985204ecSVignesh Raghavendra		>;
180985204ecSVignesh Raghavendra	};
181985204ecSVignesh Raghavendra
182985204ecSVignesh Raghavendra	rgmii1_pins_default: rgmii1-pins-default {
183985204ecSVignesh Raghavendra		pinctrl-single,pins = <
184985204ecSVignesh Raghavendra			AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
185985204ecSVignesh Raghavendra			AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
186985204ecSVignesh Raghavendra			AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
187985204ecSVignesh Raghavendra			AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
188985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
189985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
190985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
191985204ecSVignesh Raghavendra			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
192985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
193985204ecSVignesh Raghavendra			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
194985204ecSVignesh Raghavendra			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
195985204ecSVignesh Raghavendra			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
196985204ecSVignesh Raghavendra		>;
197985204ecSVignesh Raghavendra	};
198985204ecSVignesh Raghavendra
199985204ecSVignesh Raghavendra       rgmii2_pins_default: rgmii2-pins-default {
200985204ecSVignesh Raghavendra		pinctrl-single,pins = <
201985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
202985204ecSVignesh Raghavendra			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
203985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
204985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
205985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
206985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
207985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
208985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
209985204ecSVignesh Raghavendra			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
210985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
211985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
212985204ecSVignesh Raghavendra			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
213985204ecSVignesh Raghavendra		>;
214985204ecSVignesh Raghavendra	};
21504a80a75SAswath Govindraju
21604a80a75SAswath Govindraju	main_usb0_pins_default: main-usb0-pins-default {
21704a80a75SAswath Govindraju		pinctrl-single,pins = <
21804a80a75SAswath Govindraju			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
21904a80a75SAswath Govindraju		>;
22004a80a75SAswath Govindraju	};
221e4e4e894SVignesh Raghavendra
222e4e4e894SVignesh Raghavendra	ospi0_pins_default: ospi0-pins-default {
223e4e4e894SVignesh Raghavendra		pinctrl-single,pins = <
224e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
225e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
226e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
227e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
228e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
229e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
230e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
231e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
232e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
233e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
234e4e4e894SVignesh Raghavendra			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
235e4e4e894SVignesh Raghavendra		>;
236e4e4e894SVignesh Raghavendra	};
2371e6550d3SDave Gerlach};
2381e6550d3SDave Gerlach
2391e6550d3SDave Gerlach&main_uart0 {
2401e6550d3SDave Gerlach	pinctrl-names = "default";
2411e6550d3SDave Gerlach	pinctrl-0 = <&main_uart0_pins_default>;
2421e6550d3SDave Gerlach};
2431e6550d3SDave Gerlach
2441e6550d3SDave Gerlach/* main_uart1 is reserved for firmware usage */
2451e6550d3SDave Gerlach&main_uart1 {
2461e6550d3SDave Gerlach	status = "reserved";
2471e6550d3SDave Gerlach};
2481e6550d3SDave Gerlach
2491e6550d3SDave Gerlach&main_uart2 {
2501e6550d3SDave Gerlach	status = "disabled";
2511e6550d3SDave Gerlach};
2521e6550d3SDave Gerlach
2531e6550d3SDave Gerlach&main_uart3 {
2541e6550d3SDave Gerlach	status = "disabled";
2551e6550d3SDave Gerlach};
2561e6550d3SDave Gerlach
2571e6550d3SDave Gerlach&main_uart4 {
2581e6550d3SDave Gerlach	status = "disabled";
2591e6550d3SDave Gerlach};
2601e6550d3SDave Gerlach
2611e6550d3SDave Gerlach&main_uart5 {
2621e6550d3SDave Gerlach	status = "disabled";
2631e6550d3SDave Gerlach};
2641e6550d3SDave Gerlach
2651e6550d3SDave Gerlach&main_uart6 {
2661e6550d3SDave Gerlach	status = "disabled";
2671e6550d3SDave Gerlach};
2681e6550d3SDave Gerlach
2691e6550d3SDave Gerlach&mcu_uart0 {
2701e6550d3SDave Gerlach	status = "disabled";
2711e6550d3SDave Gerlach};
2721e6550d3SDave Gerlach
2731e6550d3SDave Gerlach&mcu_uart1 {
2741e6550d3SDave Gerlach	status = "disabled";
2751e6550d3SDave Gerlach};
2761e6550d3SDave Gerlach
2771e6550d3SDave Gerlach&main_i2c1 {
2781e6550d3SDave Gerlach	pinctrl-names = "default";
2791e6550d3SDave Gerlach	pinctrl-0 = <&main_i2c1_pins_default>;
2801e6550d3SDave Gerlach	clock-frequency = <400000>;
2811e6550d3SDave Gerlach
2821e6550d3SDave Gerlach	exp1: gpio@22 {
2831e6550d3SDave Gerlach		compatible = "ti,tca6424";
2841e6550d3SDave Gerlach		reg = <0x22>;
2851e6550d3SDave Gerlach		gpio-controller;
2861e6550d3SDave Gerlach		#gpio-cells = <2>;
2871e6550d3SDave Gerlach		gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
2881e6550d3SDave Gerlach				  "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
2891e6550d3SDave Gerlach				  "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
2901e6550d3SDave Gerlach				  "MMC1_SD_EN", "FSI_FET_SEL",
2911e6550d3SDave Gerlach				  "MCAN0_STB_3V3", "MCAN1_STB_3V3",
2921e6550d3SDave Gerlach				  "CPSW_FET_SEL", "CPSW_FET2_SEL",
2931e6550d3SDave Gerlach				  "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
2941e6550d3SDave Gerlach				  "GPIO_OLED_RESETn", "VPP_LDO_EN",
2951e6550d3SDave Gerlach				  "TEST_LED1", "TP92", "TP90", "TP88",
2961e6550d3SDave Gerlach				  "TP87", "TP86", "TP89", "TP91";
2971e6550d3SDave Gerlach	};
2981e6550d3SDave Gerlach
2991e6550d3SDave Gerlach	/* osd9616p0899-10 */
3001e6550d3SDave Gerlach	display@3c {
3011e6550d3SDave Gerlach		compatible = "solomon,ssd1306fb-i2c";
3021e6550d3SDave Gerlach		reg = <0x3c>;
3031e6550d3SDave Gerlach		reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
3041e6550d3SDave Gerlach		vbat-supply = <&vddb>;
3051e6550d3SDave Gerlach		solomon,height = <16>;
3061e6550d3SDave Gerlach		solomon,width = <96>;
3071e6550d3SDave Gerlach		solomon,com-seq;
3081e6550d3SDave Gerlach		solomon,com-invdir;
3091e6550d3SDave Gerlach		solomon,page-offset = <0>;
3101e6550d3SDave Gerlach		solomon,prechargep1 = <2>;
3111e6550d3SDave Gerlach		solomon,prechargep2 = <13>;
3121e6550d3SDave Gerlach	};
3131e6550d3SDave Gerlach};
3141e6550d3SDave Gerlach
315d5a4d541SAswath Govindraju/* mcu_gpio0 is reserved for mcu firmware usage */
316d5a4d541SAswath Govindraju&mcu_gpio0 {
317d5a4d541SAswath Govindraju	status = "reserved";
318d5a4d541SAswath Govindraju};
319d5a4d541SAswath Govindraju
3201e6550d3SDave Gerlach&mcu_i2c0 {
3211e6550d3SDave Gerlach	status = "disabled";
3221e6550d3SDave Gerlach};
3231e6550d3SDave Gerlach
3241e6550d3SDave Gerlach&mcu_i2c1 {
3251e6550d3SDave Gerlach	status = "disabled";
3261e6550d3SDave Gerlach};
3271e6550d3SDave Gerlach
3281e6550d3SDave Gerlach&mcu_spi0 {
3291e6550d3SDave Gerlach	status = "disabled";
3301e6550d3SDave Gerlach};
3311e6550d3SDave Gerlach
3321e6550d3SDave Gerlach&mcu_spi1 {
3331e6550d3SDave Gerlach	status = "disabled";
3341e6550d3SDave Gerlach};
3351e6550d3SDave Gerlach
3364fb6c046SAswath Govindraju&main_spi0 {
3374fb6c046SAswath Govindraju	pinctrl-names = "default";
3384fb6c046SAswath Govindraju	pinctrl-0 = <&main_spi0_pins_default>;
339d3f1b155SAswath Govindraju	ti,pindir-d0-out-d1-in;
3404fb6c046SAswath Govindraju	eeprom@0 {
3414fb6c046SAswath Govindraju		compatible = "microchip,93lc46b";
3424fb6c046SAswath Govindraju		reg = <0>;
3434fb6c046SAswath Govindraju		spi-max-frequency = <1000000>;
3444fb6c046SAswath Govindraju		spi-cs-high;
3454fb6c046SAswath Govindraju		data-size = <16>;
3464fb6c046SAswath Govindraju	};
3474fb6c046SAswath Govindraju};
3484fb6c046SAswath Govindraju
3491e6550d3SDave Gerlach&sdhci0 {
3501e6550d3SDave Gerlach	/* emmc */
3511e6550d3SDave Gerlach	bus-width = <8>;
3521e6550d3SDave Gerlach	non-removable;
3531e6550d3SDave Gerlach	ti,driver-strength-ohm = <50>;
3541e6550d3SDave Gerlach	disable-wp;
3551e6550d3SDave Gerlach};
3561e6550d3SDave Gerlach
3571e6550d3SDave Gerlach&sdhci1 {
3581e6550d3SDave Gerlach	/* SD/MMC */
3591e6550d3SDave Gerlach	vmmc-supply = <&vdd_mmc1>;
3601e6550d3SDave Gerlach	pinctrl-names = "default";
3611e6550d3SDave Gerlach	bus-width = <4>;
3621e6550d3SDave Gerlach	pinctrl-0 = <&main_mmc1_pins_default>;
3631e6550d3SDave Gerlach	ti,driver-strength-ohm = <50>;
3641e6550d3SDave Gerlach	disable-wp;
3651e6550d3SDave Gerlach};
366985204ecSVignesh Raghavendra
36704a80a75SAswath Govindraju&usbss0 {
36804a80a75SAswath Govindraju	ti,vbus-divider;
36904a80a75SAswath Govindraju	ti,usb2-only;
37004a80a75SAswath Govindraju};
37104a80a75SAswath Govindraju
37204a80a75SAswath Govindraju&usb0 {
37304a80a75SAswath Govindraju	dr_mode = "otg";
37404a80a75SAswath Govindraju	maximum-speed = "high-speed";
37504a80a75SAswath Govindraju	pinctrl-names = "default";
37604a80a75SAswath Govindraju	pinctrl-0 = <&main_usb0_pins_default>;
37704a80a75SAswath Govindraju};
37804a80a75SAswath Govindraju
379985204ecSVignesh Raghavendra&cpsw3g {
380985204ecSVignesh Raghavendra	pinctrl-names = "default";
381985204ecSVignesh Raghavendra	pinctrl-0 = <&mdio1_pins_default
382985204ecSVignesh Raghavendra		     &rgmii1_pins_default
383985204ecSVignesh Raghavendra		     &rgmii2_pins_default>;
384985204ecSVignesh Raghavendra};
385985204ecSVignesh Raghavendra
386985204ecSVignesh Raghavendra&cpsw_port1 {
387985204ecSVignesh Raghavendra	phy-mode = "rgmii-rxid";
388985204ecSVignesh Raghavendra	phy-handle = <&cpsw3g_phy0>;
389985204ecSVignesh Raghavendra};
390985204ecSVignesh Raghavendra
391985204ecSVignesh Raghavendra&cpsw_port2 {
392985204ecSVignesh Raghavendra	phy-mode = "rgmii-rxid";
393985204ecSVignesh Raghavendra	phy-handle = <&cpsw3g_phy3>;
394985204ecSVignesh Raghavendra};
395985204ecSVignesh Raghavendra
396985204ecSVignesh Raghavendra&cpsw3g_mdio {
397985204ecSVignesh Raghavendra	cpsw3g_phy0: ethernet-phy@0 {
398985204ecSVignesh Raghavendra		reg = <0>;
399985204ecSVignesh Raghavendra		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
400985204ecSVignesh Raghavendra		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
401985204ecSVignesh Raghavendra	};
402985204ecSVignesh Raghavendra};
403fad4e18fSVignesh Raghavendra
404fad4e18fSVignesh Raghavendra&tscadc0 {
405fad4e18fSVignesh Raghavendra	/* ADC is reserved for R5 usage */
406fad4e18fSVignesh Raghavendra	status = "reserved";
407fad4e18fSVignesh Raghavendra};
408e4e4e894SVignesh Raghavendra
409e4e4e894SVignesh Raghavendra&ospi0 {
410e4e4e894SVignesh Raghavendra	pinctrl-names = "default";
411e4e4e894SVignesh Raghavendra	pinctrl-0 = <&ospi0_pins_default>;
412e4e4e894SVignesh Raghavendra
413e4e4e894SVignesh Raghavendra	flash@0{
414e4e4e894SVignesh Raghavendra		compatible = "jedec,spi-nor";
415e4e4e894SVignesh Raghavendra		reg = <0x0>;
416e4e4e894SVignesh Raghavendra		spi-tx-bus-width = <8>;
417e4e4e894SVignesh Raghavendra		spi-rx-bus-width = <8>;
418e4e4e894SVignesh Raghavendra		spi-max-frequency = <25000000>;
419e4e4e894SVignesh Raghavendra		cdns,tshsl-ns = <60>;
420e4e4e894SVignesh Raghavendra		cdns,tsd2d-ns = <60>;
421e4e4e894SVignesh Raghavendra		cdns,tchsh-ns = <60>;
422e4e4e894SVignesh Raghavendra		cdns,tslch-ns = <60>;
423e4e4e894SVignesh Raghavendra		cdns,read-delay = <4>;
424e4e4e894SVignesh Raghavendra		#address-cells = <1>;
425e4e4e894SVignesh Raghavendra		#size-cells = <1>;
426e4e4e894SVignesh Raghavendra	};
427e4e4e894SVignesh Raghavendra};
4287dd84752SSuman Anna
4297dd84752SSuman Anna&mailbox0_cluster2 {
4307dd84752SSuman Anna	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
4317dd84752SSuman Anna		ti,mbox-rx = <0 0 2>;
4327dd84752SSuman Anna		ti,mbox-tx = <1 0 2>;
4337dd84752SSuman Anna	};
4347dd84752SSuman Anna
4357dd84752SSuman Anna	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
4367dd84752SSuman Anna		ti,mbox-rx = <2 0 2>;
4377dd84752SSuman Anna		ti,mbox-tx = <3 0 2>;
4387dd84752SSuman Anna	};
4397dd84752SSuman Anna};
4407dd84752SSuman Anna
4417dd84752SSuman Anna&mailbox0_cluster3 {
4427dd84752SSuman Anna	status = "disabled";
4437dd84752SSuman Anna};
4447dd84752SSuman Anna
4457dd84752SSuman Anna&mailbox0_cluster4 {
4467dd84752SSuman Anna	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
4477dd84752SSuman Anna		ti,mbox-rx = <0 0 2>;
4487dd84752SSuman Anna		ti,mbox-tx = <1 0 2>;
4497dd84752SSuman Anna	};
4507dd84752SSuman Anna
4517dd84752SSuman Anna	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
4527dd84752SSuman Anna		ti,mbox-rx = <2 0 2>;
4537dd84752SSuman Anna		ti,mbox-tx = <3 0 2>;
4547dd84752SSuman Anna	};
4557dd84752SSuman Anna};
4567dd84752SSuman Anna
4577dd84752SSuman Anna&mailbox0_cluster5 {
4587dd84752SSuman Anna	status = "disabled";
4597dd84752SSuman Anna};
4607dd84752SSuman Anna
4617dd84752SSuman Anna&mailbox0_cluster6 {
4627dd84752SSuman Anna	mbox_m4_0: mbox-m4-0 {
4637dd84752SSuman Anna		ti,mbox-rx = <0 0 2>;
4647dd84752SSuman Anna		ti,mbox-tx = <1 0 2>;
4657dd84752SSuman Anna	};
4667dd84752SSuman Anna};
4677dd84752SSuman Anna
4687dd84752SSuman Anna&mailbox0_cluster7 {
4697dd84752SSuman Anna	status = "disabled";
4707dd84752SSuman Anna};
471354065beSKishon Vijay Abraham I
472*0afadba4SSuman Anna&main_r5fss0_core0 {
473*0afadba4SSuman Anna	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
474*0afadba4SSuman Anna};
475*0afadba4SSuman Anna
476*0afadba4SSuman Anna&main_r5fss0_core1 {
477*0afadba4SSuman Anna	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
478*0afadba4SSuman Anna};
479*0afadba4SSuman Anna
480*0afadba4SSuman Anna&main_r5fss1_core0 {
481*0afadba4SSuman Anna	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
482*0afadba4SSuman Anna};
483*0afadba4SSuman Anna
484*0afadba4SSuman Anna&main_r5fss1_core1 {
485*0afadba4SSuman Anna	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
486*0afadba4SSuman Anna};
487*0afadba4SSuman Anna
488354065beSKishon Vijay Abraham I&serdes_ln_ctrl {
489354065beSKishon Vijay Abraham I	idle-states = <AM64_SERDES0_LANE0_PCIE0>;
490354065beSKishon Vijay Abraham I};
491354065beSKishon Vijay Abraham I
492354065beSKishon Vijay Abraham I&serdes0 {
493354065beSKishon Vijay Abraham I	serdes0_pcie_link: phy@0 {
494354065beSKishon Vijay Abraham I		reg = <0>;
495354065beSKishon Vijay Abraham I		cdns,num-lanes = <1>;
496354065beSKishon Vijay Abraham I		#phy-cells = <0>;
497354065beSKishon Vijay Abraham I		cdns,phy-type = <PHY_TYPE_PCIE>;
498354065beSKishon Vijay Abraham I		resets = <&serdes_wiz0 1>;
499354065beSKishon Vijay Abraham I	};
500354065beSKishon Vijay Abraham I};
501354065beSKishon Vijay Abraham I
502354065beSKishon Vijay Abraham I&pcie0_rc {
503354065beSKishon Vijay Abraham I	reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
504354065beSKishon Vijay Abraham I	phys = <&serdes0_pcie_link>;
505354065beSKishon Vijay Abraham I	phy-names = "pcie-phy";
506354065beSKishon Vijay Abraham I	num-lanes = <1>;
507354065beSKishon Vijay Abraham I};
508354065beSKishon Vijay Abraham I
509354065beSKishon Vijay Abraham I&pcie0_ep {
510354065beSKishon Vijay Abraham I	phys = <&serdes0_pcie_link>;
511354065beSKishon Vijay Abraham I	phy-names = "pcie-phy";
512354065beSKishon Vijay Abraham I	num-lanes = <1>;
513354065beSKishon Vijay Abraham I	status = "disabled";
514354065beSKishon Vijay Abraham I};
515