1*c46388a5SZhizhou Zhang/* 2*c46388a5SZhizhou Zhang * Spreadtrum Sharkl64 platform DTS file 3*c46388a5SZhizhou Zhang * 4*c46388a5SZhizhou Zhang * Copyright (C) 2014, Spreadtrum Communications Inc. 5*c46388a5SZhizhou Zhang * 6*c46388a5SZhizhou Zhang * This file is licensed under a dual GPLv2 or X11 license. 7*c46388a5SZhizhou Zhang */ 8*c46388a5SZhizhou Zhang 9*c46388a5SZhizhou Zhang/ { 10*c46388a5SZhizhou Zhang interrupt-parent = <&gic>; 11*c46388a5SZhizhou Zhang #address-cells = <2>; 12*c46388a5SZhizhou Zhang #size-cells = <2>; 13*c46388a5SZhizhou Zhang 14*c46388a5SZhizhou Zhang soc { 15*c46388a5SZhizhou Zhang compatible = "simple-bus"; 16*c46388a5SZhizhou Zhang #address-cells = <2>; 17*c46388a5SZhizhou Zhang #size-cells = <2>; 18*c46388a5SZhizhou Zhang ranges; 19*c46388a5SZhizhou Zhang 20*c46388a5SZhizhou Zhang ap-apb { 21*c46388a5SZhizhou Zhang compatible = "simple-bus"; 22*c46388a5SZhizhou Zhang #address-cells = <2>; 23*c46388a5SZhizhou Zhang #size-cells = <2>; 24*c46388a5SZhizhou Zhang ranges; 25*c46388a5SZhizhou Zhang 26*c46388a5SZhizhou Zhang uart0: serial@70000000 { 27*c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 28*c46388a5SZhizhou Zhang reg = <0 0x70000000 0 0x100>; 29*c46388a5SZhizhou Zhang interrupts = <0 2 0xf04>; 30*c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 31*c46388a5SZhizhou Zhang status = "disabled"; 32*c46388a5SZhizhou Zhang }; 33*c46388a5SZhizhou Zhang 34*c46388a5SZhizhou Zhang uart1: serial@70100000 { 35*c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 36*c46388a5SZhizhou Zhang reg = <0 0x70100000 0 0x100>; 37*c46388a5SZhizhou Zhang interrupts = <0 3 0xf04>; 38*c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 39*c46388a5SZhizhou Zhang status = "disabled"; 40*c46388a5SZhizhou Zhang }; 41*c46388a5SZhizhou Zhang 42*c46388a5SZhizhou Zhang uart2: serial@70200000 { 43*c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 44*c46388a5SZhizhou Zhang reg = <0 0x70200000 0 0x100>; 45*c46388a5SZhizhou Zhang interrupts = <0 4 0xf04>; 46*c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 47*c46388a5SZhizhou Zhang status = "disabled"; 48*c46388a5SZhizhou Zhang }; 49*c46388a5SZhizhou Zhang 50*c46388a5SZhizhou Zhang uart3: serial@70300000 { 51*c46388a5SZhizhou Zhang compatible = "sprd,sc9836-uart"; 52*c46388a5SZhizhou Zhang reg = <0 0x70300000 0 0x100>; 53*c46388a5SZhizhou Zhang interrupts = <0 5 0xf04>; 54*c46388a5SZhizhou Zhang clocks = <&clk26mhz>; 55*c46388a5SZhizhou Zhang status = "disabled"; 56*c46388a5SZhizhou Zhang }; 57*c46388a5SZhizhou Zhang }; 58*c46388a5SZhizhou Zhang }; 59*c46388a5SZhizhou Zhang 60*c46388a5SZhizhou Zhang clk26mhz: clk26mhz { 61*c46388a5SZhizhou Zhang compatible = "fixed-clock"; 62*c46388a5SZhizhou Zhang #clock-cells = <0>; 63*c46388a5SZhizhou Zhang clock-frequency = <26000000>; 64*c46388a5SZhizhou Zhang }; 65*c46388a5SZhizhou Zhang}; 66