1*587b4ee2SJianqun Xu// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*587b4ee2SJianqun Xu// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 3*587b4ee2SJianqun Xu 4*587b4ee2SJianqun Xu#include "rk3399.dtsi" 5*587b4ee2SJianqun Xu 6*587b4ee2SJianqun Xu/ { 7*587b4ee2SJianqun Xu compatible = "rockchip,rk3399pro"; 8*587b4ee2SJianqun Xu}; 9*587b4ee2SJianqun Xu 10*587b4ee2SJianqun Xu/* Default to enabled since AP talk to NPU part over pcie */ 11*587b4ee2SJianqun Xu&pcie_phy { 12*587b4ee2SJianqun Xu status = "okay"; 13*587b4ee2SJianqun Xu}; 14*587b4ee2SJianqun Xu 15*587b4ee2SJianqun Xu/* Default to enabled since AP talk to NPU part over pcie */ 16*587b4ee2SJianqun Xu&pcie0 { 17*587b4ee2SJianqun Xu ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; 18*587b4ee2SJianqun Xu num-lanes = <4>; 19*587b4ee2SJianqun Xu pinctrl-names = "default"; 20*587b4ee2SJianqun Xu pinctrl-0 = <&pcie_clkreqn_cpm>; 21*587b4ee2SJianqun Xu status = "okay"; 22*587b4ee2SJianqun Xu}; 23