1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 4 */ 5 6#include <dt-bindings/clock/rk3368-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3368"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet0 = &gmac; 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 i2c4 = &i2c4; 27 i2c5 = &i2c5; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 spi0 = &spi0; 34 spi1 = &spi1; 35 spi2 = &spi2; 36 }; 37 38 cpus { 39 #address-cells = <0x2>; 40 #size-cells = <0x0>; 41 42 cpu-map { 43 cluster0 { 44 core0 { 45 cpu = <&cpu_b0>; 46 }; 47 core1 { 48 cpu = <&cpu_b1>; 49 }; 50 core2 { 51 cpu = <&cpu_b2>; 52 }; 53 core3 { 54 cpu = <&cpu_b3>; 55 }; 56 }; 57 58 cluster1 { 59 core0 { 60 cpu = <&cpu_l0>; 61 }; 62 core1 { 63 cpu = <&cpu_l1>; 64 }; 65 core2 { 66 cpu = <&cpu_l2>; 67 }; 68 core3 { 69 cpu = <&cpu_l3>; 70 }; 71 }; 72 }; 73 74 cpu_l0: cpu@0 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x0>; 78 enable-method = "psci"; 79 #cooling-cells = <2>; /* min followed by max */ 80 }; 81 82 cpu_l1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x1>; 86 enable-method = "psci"; 87 #cooling-cells = <2>; /* min followed by max */ 88 }; 89 90 cpu_l2: cpu@2 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a53"; 93 reg = <0x0 0x2>; 94 enable-method = "psci"; 95 #cooling-cells = <2>; /* min followed by max */ 96 }; 97 98 cpu_l3: cpu@3 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x0 0x3>; 102 enable-method = "psci"; 103 #cooling-cells = <2>; /* min followed by max */ 104 }; 105 106 cpu_b0: cpu@100 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x0 0x100>; 110 enable-method = "psci"; 111 #cooling-cells = <2>; /* min followed by max */ 112 }; 113 114 cpu_b1: cpu@101 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x0 0x101>; 118 enable-method = "psci"; 119 #cooling-cells = <2>; /* min followed by max */ 120 }; 121 122 cpu_b2: cpu@102 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x0 0x102>; 126 enable-method = "psci"; 127 #cooling-cells = <2>; /* min followed by max */ 128 }; 129 130 cpu_b3: cpu@103 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a53"; 133 reg = <0x0 0x103>; 134 enable-method = "psci"; 135 #cooling-cells = <2>; /* min followed by max */ 136 }; 137 }; 138 139 arm-pmu { 140 compatible = "arm,armv8-pmuv3"; 141 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 150 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 151 <&cpu_b2>, <&cpu_b3>; 152 }; 153 154 psci { 155 compatible = "arm,psci-0.2"; 156 method = "smc"; 157 }; 158 159 timer { 160 compatible = "arm,armv8-timer"; 161 interrupts = <GIC_PPI 13 162 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 163 <GIC_PPI 14 164 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 165 <GIC_PPI 11 166 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 167 <GIC_PPI 10 168 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 169 }; 170 171 xin24m: oscillator { 172 compatible = "fixed-clock"; 173 clock-frequency = <24000000>; 174 clock-output-names = "xin24m"; 175 #clock-cells = <0>; 176 }; 177 178 sdmmc: mmc@ff0c0000 { 179 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 180 reg = <0x0 0xff0c0000 0x0 0x4000>; 181 max-frequency = <150000000>; 182 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 183 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 184 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 185 fifo-depth = <0x100>; 186 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 187 resets = <&cru SRST_MMC0>; 188 reset-names = "reset"; 189 status = "disabled"; 190 }; 191 192 sdio0: mmc@ff0d0000 { 193 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 194 reg = <0x0 0xff0d0000 0x0 0x4000>; 195 max-frequency = <150000000>; 196 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 197 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 198 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 199 fifo-depth = <0x100>; 200 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 201 resets = <&cru SRST_SDIO0>; 202 reset-names = "reset"; 203 status = "disabled"; 204 }; 205 206 emmc: mmc@ff0f0000 { 207 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 208 reg = <0x0 0xff0f0000 0x0 0x4000>; 209 max-frequency = <150000000>; 210 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 211 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 212 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 213 fifo-depth = <0x100>; 214 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 215 resets = <&cru SRST_EMMC>; 216 reset-names = "reset"; 217 status = "disabled"; 218 }; 219 220 saradc: saradc@ff100000 { 221 compatible = "rockchip,saradc"; 222 reg = <0x0 0xff100000 0x0 0x100>; 223 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 224 #io-channel-cells = <1>; 225 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 226 clock-names = "saradc", "apb_pclk"; 227 resets = <&cru SRST_SARADC>; 228 reset-names = "saradc-apb"; 229 status = "disabled"; 230 }; 231 232 spi0: spi@ff110000 { 233 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 234 reg = <0x0 0xff110000 0x0 0x1000>; 235 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 236 clock-names = "spiclk", "apb_pclk"; 237 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 status = "disabled"; 243 }; 244 245 spi1: spi@ff120000 { 246 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 247 reg = <0x0 0xff120000 0x0 0x1000>; 248 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 249 clock-names = "spiclk", "apb_pclk"; 250 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 spi2: spi@ff130000 { 259 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 260 reg = <0x0 0xff130000 0x0 0x1000>; 261 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 262 clock-names = "spiclk", "apb_pclk"; 263 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 271 i2c2: i2c@ff140000 { 272 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 273 reg = <0x0 0xff140000 0x0 0x1000>; 274 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 clock-names = "i2c"; 278 clocks = <&cru PCLK_I2C2>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&i2c2_xfer>; 281 status = "disabled"; 282 }; 283 284 i2c3: i2c@ff150000 { 285 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 286 reg = <0x0 0xff150000 0x0 0x1000>; 287 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 clock-names = "i2c"; 291 clocks = <&cru PCLK_I2C3>; 292 pinctrl-names = "default"; 293 pinctrl-0 = <&i2c3_xfer>; 294 status = "disabled"; 295 }; 296 297 i2c4: i2c@ff160000 { 298 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 299 reg = <0x0 0xff160000 0x0 0x1000>; 300 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 clock-names = "i2c"; 304 clocks = <&cru PCLK_I2C4>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&i2c4_xfer>; 307 status = "disabled"; 308 }; 309 310 i2c5: i2c@ff170000 { 311 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 312 reg = <0x0 0xff170000 0x0 0x1000>; 313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clock-names = "i2c"; 317 clocks = <&cru PCLK_I2C5>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&i2c5_xfer>; 320 status = "disabled"; 321 }; 322 323 uart0: serial@ff180000 { 324 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 325 reg = <0x0 0xff180000 0x0 0x100>; 326 clock-frequency = <24000000>; 327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 328 clock-names = "baudclk", "apb_pclk"; 329 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 330 reg-shift = <2>; 331 reg-io-width = <4>; 332 status = "disabled"; 333 }; 334 335 uart1: serial@ff190000 { 336 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 337 reg = <0x0 0xff190000 0x0 0x100>; 338 clock-frequency = <24000000>; 339 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 340 clock-names = "baudclk", "apb_pclk"; 341 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 342 reg-shift = <2>; 343 reg-io-width = <4>; 344 status = "disabled"; 345 }; 346 347 uart3: serial@ff1b0000 { 348 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 349 reg = <0x0 0xff1b0000 0x0 0x100>; 350 clock-frequency = <24000000>; 351 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 352 clock-names = "baudclk", "apb_pclk"; 353 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 status = "disabled"; 357 }; 358 359 uart4: serial@ff1c0000 { 360 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 361 reg = <0x0 0xff1c0000 0x0 0x100>; 362 clock-frequency = <24000000>; 363 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 364 clock-names = "baudclk", "apb_pclk"; 365 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 366 reg-shift = <2>; 367 reg-io-width = <4>; 368 status = "disabled"; 369 }; 370 371 dmac_peri: dma-controller@ff250000 { 372 compatible = "arm,pl330", "arm,primecell"; 373 reg = <0x0 0xff250000 0x0 0x4000>; 374 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 376 #dma-cells = <1>; 377 arm,pl330-broken-no-flushp; 378 arm,pl330-periph-burst; 379 clocks = <&cru ACLK_DMAC_PERI>; 380 clock-names = "apb_pclk"; 381 }; 382 383 thermal-zones { 384 cpu_thermal: cpu-thermal { 385 polling-delay-passive = <100>; /* milliseconds */ 386 polling-delay = <5000>; /* milliseconds */ 387 388 thermal-sensors = <&tsadc 0>; 389 390 trips { 391 cpu_alert0: cpu_alert0 { 392 temperature = <75000>; /* millicelsius */ 393 hysteresis = <2000>; /* millicelsius */ 394 type = "passive"; 395 }; 396 cpu_alert1: cpu_alert1 { 397 temperature = <80000>; /* millicelsius */ 398 hysteresis = <2000>; /* millicelsius */ 399 type = "passive"; 400 }; 401 cpu_crit: cpu_crit { 402 temperature = <95000>; /* millicelsius */ 403 hysteresis = <2000>; /* millicelsius */ 404 type = "critical"; 405 }; 406 }; 407 408 cooling-maps { 409 map0 { 410 trip = <&cpu_alert0>; 411 cooling-device = 412 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 413 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 414 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 415 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 416 }; 417 map1 { 418 trip = <&cpu_alert1>; 419 cooling-device = 420 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 421 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 422 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 423 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 424 }; 425 }; 426 }; 427 428 gpu_thermal: gpu-thermal { 429 polling-delay-passive = <100>; /* milliseconds */ 430 polling-delay = <5000>; /* milliseconds */ 431 432 thermal-sensors = <&tsadc 1>; 433 434 trips { 435 gpu_alert0: gpu_alert0 { 436 temperature = <80000>; /* millicelsius */ 437 hysteresis = <2000>; /* millicelsius */ 438 type = "passive"; 439 }; 440 gpu_crit: gpu_crit { 441 temperature = <115000>; /* millicelsius */ 442 hysteresis = <2000>; /* millicelsius */ 443 type = "critical"; 444 }; 445 }; 446 447 cooling-maps { 448 map0 { 449 trip = <&gpu_alert0>; 450 cooling-device = 451 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 452 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 453 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 454 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 455 }; 456 }; 457 }; 458 }; 459 460 tsadc: tsadc@ff280000 { 461 compatible = "rockchip,rk3368-tsadc"; 462 reg = <0x0 0xff280000 0x0 0x100>; 463 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 465 clock-names = "tsadc", "apb_pclk"; 466 resets = <&cru SRST_TSADC>; 467 reset-names = "tsadc-apb"; 468 pinctrl-names = "init", "default", "sleep"; 469 pinctrl-0 = <&otp_pin>; 470 pinctrl-1 = <&otp_out>; 471 pinctrl-2 = <&otp_pin>; 472 #thermal-sensor-cells = <1>; 473 rockchip,hw-tshut-temp = <95000>; 474 status = "disabled"; 475 }; 476 477 gmac: ethernet@ff290000 { 478 compatible = "rockchip,rk3368-gmac"; 479 reg = <0x0 0xff290000 0x0 0x10000>; 480 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 481 interrupt-names = "macirq"; 482 rockchip,grf = <&grf>; 483 clocks = <&cru SCLK_MAC>, 484 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 485 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 486 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 487 clock-names = "stmmaceth", 488 "mac_clk_rx", "mac_clk_tx", 489 "clk_mac_ref", "clk_mac_refout", 490 "aclk_mac", "pclk_mac"; 491 status = "disabled"; 492 }; 493 494 usb_host0_ehci: usb@ff500000 { 495 compatible = "generic-ehci"; 496 reg = <0x0 0xff500000 0x0 0x100>; 497 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&cru HCLK_HOST0>; 499 status = "disabled"; 500 }; 501 502 usb_otg: usb@ff580000 { 503 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 504 "snps,dwc2"; 505 reg = <0x0 0xff580000 0x0 0x40000>; 506 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cru HCLK_OTG0>; 508 clock-names = "otg"; 509 dr_mode = "otg"; 510 g-np-tx-fifo-size = <16>; 511 g-rx-fifo-size = <275>; 512 g-tx-fifo-size = <256 128 128 64 64 32>; 513 status = "disabled"; 514 }; 515 516 dmac_bus: dma-controller@ff600000 { 517 compatible = "arm,pl330", "arm,primecell"; 518 reg = <0x0 0xff600000 0x0 0x4000>; 519 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 521 #dma-cells = <1>; 522 arm,pl330-broken-no-flushp; 523 arm,pl330-periph-burst; 524 clocks = <&cru ACLK_DMAC_BUS>; 525 clock-names = "apb_pclk"; 526 }; 527 528 i2c0: i2c@ff650000 { 529 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 530 reg = <0x0 0xff650000 0x0 0x1000>; 531 clocks = <&cru PCLK_I2C0>; 532 clock-names = "i2c"; 533 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c0_xfer>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c1: i2c@ff660000 { 542 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 543 reg = <0x0 0xff660000 0x0 0x1000>; 544 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clock-names = "i2c"; 548 clocks = <&cru PCLK_I2C1>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&i2c1_xfer>; 551 status = "disabled"; 552 }; 553 554 pwm0: pwm@ff680000 { 555 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 556 reg = <0x0 0xff680000 0x0 0x10>; 557 #pwm-cells = <3>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&pwm0_pin>; 560 clocks = <&cru PCLK_PWM1>; 561 clock-names = "pwm"; 562 status = "disabled"; 563 }; 564 565 pwm1: pwm@ff680010 { 566 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 567 reg = <0x0 0xff680010 0x0 0x10>; 568 #pwm-cells = <3>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pwm1_pin>; 571 clocks = <&cru PCLK_PWM1>; 572 clock-names = "pwm"; 573 status = "disabled"; 574 }; 575 576 pwm2: pwm@ff680020 { 577 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 578 reg = <0x0 0xff680020 0x0 0x10>; 579 #pwm-cells = <3>; 580 clocks = <&cru PCLK_PWM1>; 581 clock-names = "pwm"; 582 status = "disabled"; 583 }; 584 585 pwm3: pwm@ff680030 { 586 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 587 reg = <0x0 0xff680030 0x0 0x10>; 588 #pwm-cells = <3>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pwm3_pin>; 591 clocks = <&cru PCLK_PWM1>; 592 clock-names = "pwm"; 593 status = "disabled"; 594 }; 595 596 uart2: serial@ff690000 { 597 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 598 reg = <0x0 0xff690000 0x0 0x100>; 599 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 600 clock-names = "baudclk", "apb_pclk"; 601 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&uart2_xfer>; 604 reg-shift = <2>; 605 reg-io-width = <4>; 606 status = "disabled"; 607 }; 608 609 mbox: mbox@ff6b0000 { 610 compatible = "rockchip,rk3368-mailbox"; 611 reg = <0x0 0xff6b0000 0x0 0x1000>; 612 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&cru PCLK_MAILBOX>; 617 clock-names = "pclk_mailbox"; 618 #mbox-cells = <1>; 619 status = "disabled"; 620 }; 621 622 pmugrf: syscon@ff738000 { 623 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; 624 reg = <0x0 0xff738000 0x0 0x1000>; 625 626 pmu_io_domains: io-domains { 627 compatible = "rockchip,rk3368-pmu-io-voltage-domain"; 628 status = "disabled"; 629 }; 630 631 reboot-mode { 632 compatible = "syscon-reboot-mode"; 633 offset = <0x200>; 634 mode-normal = <BOOT_NORMAL>; 635 mode-recovery = <BOOT_RECOVERY>; 636 mode-bootloader = <BOOT_FASTBOOT>; 637 mode-loader = <BOOT_BL_DOWNLOAD>; 638 }; 639 }; 640 641 cru: clock-controller@ff760000 { 642 compatible = "rockchip,rk3368-cru"; 643 reg = <0x0 0xff760000 0x0 0x1000>; 644 rockchip,grf = <&grf>; 645 #clock-cells = <1>; 646 #reset-cells = <1>; 647 }; 648 649 grf: syscon@ff770000 { 650 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; 651 reg = <0x0 0xff770000 0x0 0x1000>; 652 653 io_domains: io-domains { 654 compatible = "rockchip,rk3368-io-voltage-domain"; 655 status = "disabled"; 656 }; 657 }; 658 659 wdt: watchdog@ff800000 { 660 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 661 reg = <0x0 0xff800000 0x0 0x100>; 662 clocks = <&cru PCLK_WDT>; 663 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 664 status = "disabled"; 665 }; 666 667 timer0: timer@ff810000 { 668 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 669 reg = <0x0 0xff810000 0x0 0x20>; 670 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 671 }; 672 673 spdif: spdif@ff880000 { 674 compatible = "rockchip,rk3368-spdif"; 675 reg = <0x0 0xff880000 0x0 0x1000>; 676 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 678 clock-names = "mclk", "hclk"; 679 dmas = <&dmac_bus 3>; 680 dma-names = "tx"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&spdif_tx>; 683 status = "disabled"; 684 }; 685 686 i2s_2ch: i2s-2ch@ff890000 { 687 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 688 reg = <0x0 0xff890000 0x0 0x1000>; 689 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 690 clock-names = "i2s_clk", "i2s_hclk"; 691 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; 692 dmas = <&dmac_bus 6>, <&dmac_bus 7>; 693 dma-names = "tx", "rx"; 694 status = "disabled"; 695 }; 696 697 i2s_8ch: i2s-8ch@ff898000 { 698 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 699 reg = <0x0 0xff898000 0x0 0x1000>; 700 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 701 clock-names = "i2s_clk", "i2s_hclk"; 702 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; 703 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 704 dma-names = "tx", "rx"; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&i2s_8ch_bus>; 707 status = "disabled"; 708 }; 709 710 iep_mmu: iommu@ff900800 { 711 compatible = "rockchip,iommu"; 712 reg = <0x0 0xff900800 0x0 0x100>; 713 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 714 interrupt-names = "iep_mmu"; 715 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 716 clock-names = "aclk", "iface"; 717 #iommu-cells = <0>; 718 status = "disabled"; 719 }; 720 721 isp_mmu: iommu@ff914000 { 722 compatible = "rockchip,iommu"; 723 reg = <0x0 0xff914000 0x0 0x100>, 724 <0x0 0xff915000 0x0 0x100>; 725 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 726 interrupt-names = "isp_mmu"; 727 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 728 clock-names = "aclk", "iface"; 729 #iommu-cells = <0>; 730 rockchip,disable-mmu-reset; 731 status = "disabled"; 732 }; 733 734 vop_mmu: iommu@ff930300 { 735 compatible = "rockchip,iommu"; 736 reg = <0x0 0xff930300 0x0 0x100>; 737 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "vop_mmu"; 739 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 740 clock-names = "aclk", "iface"; 741 #iommu-cells = <0>; 742 status = "disabled"; 743 }; 744 745 hevc_mmu: iommu@ff9a0440 { 746 compatible = "rockchip,iommu"; 747 reg = <0x0 0xff9a0440 0x0 0x40>, 748 <0x0 0xff9a0480 0x0 0x40>; 749 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 750 interrupt-names = "hevc_mmu"; 751 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 752 clock-names = "aclk", "iface"; 753 #iommu-cells = <0>; 754 status = "disabled"; 755 }; 756 757 vpu_mmu: iommu@ff9a0800 { 758 compatible = "rockchip,iommu"; 759 reg = <0x0 0xff9a0800 0x0 0x100>; 760 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "vepu_mmu", "vdpu_mmu"; 763 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 764 clock-names = "aclk", "iface"; 765 #iommu-cells = <0>; 766 status = "disabled"; 767 }; 768 769 efuse256: efuse@ffb00000 { 770 compatible = "rockchip,rk3368-efuse"; 771 reg = <0x0 0xffb00000 0x0 0x20>; 772 #address-cells = <1>; 773 #size-cells = <1>; 774 clocks = <&cru PCLK_EFUSE256>; 775 clock-names = "pclk_efuse"; 776 777 cpu_leakage: cpu-leakage@17 { 778 reg = <0x17 0x1>; 779 }; 780 temp_adjust: temp-adjust@1f { 781 reg = <0x1f 0x1>; 782 }; 783 }; 784 785 gic: interrupt-controller@ffb71000 { 786 compatible = "arm,gic-400"; 787 interrupt-controller; 788 #interrupt-cells = <3>; 789 #address-cells = <0>; 790 791 reg = <0x0 0xffb71000 0x0 0x1000>, 792 <0x0 0xffb72000 0x0 0x2000>, 793 <0x0 0xffb74000 0x0 0x2000>, 794 <0x0 0xffb76000 0x0 0x2000>; 795 interrupts = <GIC_PPI 9 796 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 797 }; 798 799 pinctrl: pinctrl { 800 compatible = "rockchip,rk3368-pinctrl"; 801 rockchip,grf = <&grf>; 802 rockchip,pmu = <&pmugrf>; 803 #address-cells = <0x2>; 804 #size-cells = <0x2>; 805 ranges; 806 807 gpio0: gpio0@ff750000 { 808 compatible = "rockchip,gpio-bank"; 809 reg = <0x0 0xff750000 0x0 0x100>; 810 clocks = <&cru PCLK_GPIO0>; 811 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 812 813 gpio-controller; 814 #gpio-cells = <0x2>; 815 816 interrupt-controller; 817 #interrupt-cells = <0x2>; 818 }; 819 820 gpio1: gpio1@ff780000 { 821 compatible = "rockchip,gpio-bank"; 822 reg = <0x0 0xff780000 0x0 0x100>; 823 clocks = <&cru PCLK_GPIO1>; 824 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 825 826 gpio-controller; 827 #gpio-cells = <0x2>; 828 829 interrupt-controller; 830 #interrupt-cells = <0x2>; 831 }; 832 833 gpio2: gpio2@ff790000 { 834 compatible = "rockchip,gpio-bank"; 835 reg = <0x0 0xff790000 0x0 0x100>; 836 clocks = <&cru PCLK_GPIO2>; 837 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 838 839 gpio-controller; 840 #gpio-cells = <0x2>; 841 842 interrupt-controller; 843 #interrupt-cells = <0x2>; 844 }; 845 846 gpio3: gpio3@ff7a0000 { 847 compatible = "rockchip,gpio-bank"; 848 reg = <0x0 0xff7a0000 0x0 0x100>; 849 clocks = <&cru PCLK_GPIO3>; 850 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 851 852 gpio-controller; 853 #gpio-cells = <0x2>; 854 855 interrupt-controller; 856 #interrupt-cells = <0x2>; 857 }; 858 859 pcfg_pull_up: pcfg-pull-up { 860 bias-pull-up; 861 }; 862 863 pcfg_pull_down: pcfg-pull-down { 864 bias-pull-down; 865 }; 866 867 pcfg_pull_none: pcfg-pull-none { 868 bias-disable; 869 }; 870 871 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 872 bias-disable; 873 drive-strength = <12>; 874 }; 875 876 emmc { 877 emmc_clk: emmc-clk { 878 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 879 }; 880 881 emmc_cmd: emmc-cmd { 882 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; 883 }; 884 885 emmc_pwr: emmc-pwr { 886 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; 887 }; 888 889 emmc_bus1: emmc-bus1 { 890 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; 891 }; 892 893 emmc_bus4: emmc-bus4 { 894 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 895 <1 RK_PC3 2 &pcfg_pull_up>, 896 <1 RK_PC4 2 &pcfg_pull_up>, 897 <1 RK_PC5 2 &pcfg_pull_up>; 898 }; 899 900 emmc_bus8: emmc-bus8 { 901 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 902 <1 RK_PC3 2 &pcfg_pull_up>, 903 <1 RK_PC4 2 &pcfg_pull_up>, 904 <1 RK_PC5 2 &pcfg_pull_up>, 905 <1 RK_PC6 2 &pcfg_pull_up>, 906 <1 RK_PC7 2 &pcfg_pull_up>, 907 <1 RK_PD0 2 &pcfg_pull_up>, 908 <1 RK_PD1 2 &pcfg_pull_up>; 909 }; 910 }; 911 912 gmac { 913 rgmii_pins: rgmii-pins { 914 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 915 <3 RK_PD0 1 &pcfg_pull_none>, 916 <3 RK_PC3 1 &pcfg_pull_none>, 917 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 918 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 919 <3 RK_PB2 1 &pcfg_pull_none_12ma>, 920 <3 RK_PB6 1 &pcfg_pull_none_12ma>, 921 <3 RK_PD4 1 &pcfg_pull_none_12ma>, 922 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 923 <3 RK_PB7 1 &pcfg_pull_none>, 924 <3 RK_PC0 1 &pcfg_pull_none>, 925 <3 RK_PC1 1 &pcfg_pull_none>, 926 <3 RK_PC2 1 &pcfg_pull_none>, 927 <3 RK_PD1 1 &pcfg_pull_none>, 928 <3 RK_PC4 1 &pcfg_pull_none>; 929 }; 930 931 rmii_pins: rmii-pins { 932 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 933 <3 RK_PD0 1 &pcfg_pull_none>, 934 <3 RK_PC3 1 &pcfg_pull_none>, 935 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 936 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 937 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 938 <3 RK_PB7 1 &pcfg_pull_none>, 939 <3 RK_PC0 1 &pcfg_pull_none>, 940 <3 RK_PC4 1 &pcfg_pull_none>, 941 <3 RK_PC5 1 &pcfg_pull_none>; 942 }; 943 }; 944 945 i2c0 { 946 i2c0_xfer: i2c0-xfer { 947 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 948 <0 RK_PA7 1 &pcfg_pull_none>; 949 }; 950 }; 951 952 i2c1 { 953 i2c1_xfer: i2c1-xfer { 954 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, 955 <2 RK_PC6 1 &pcfg_pull_none>; 956 }; 957 }; 958 959 i2c2 { 960 i2c2_xfer: i2c2-xfer { 961 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, 962 <3 RK_PD7 2 &pcfg_pull_none>; 963 }; 964 }; 965 966 i2c3 { 967 i2c3_xfer: i2c3-xfer { 968 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 969 <1 RK_PC1 1 &pcfg_pull_none>; 970 }; 971 }; 972 973 i2c4 { 974 i2c4_xfer: i2c4-xfer { 975 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 976 <3 RK_PD1 2 &pcfg_pull_none>; 977 }; 978 }; 979 980 i2c5 { 981 i2c5_xfer: i2c5-xfer { 982 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, 983 <3 RK_PD3 2 &pcfg_pull_none>; 984 }; 985 }; 986 987 i2s { 988 i2s_8ch_bus: i2s-8ch-bus { 989 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 990 <2 RK_PB5 1 &pcfg_pull_none>, 991 <2 RK_PB6 1 &pcfg_pull_none>, 992 <2 RK_PB7 1 &pcfg_pull_none>, 993 <2 RK_PC0 1 &pcfg_pull_none>, 994 <2 RK_PC1 1 &pcfg_pull_none>, 995 <2 RK_PC2 1 &pcfg_pull_none>, 996 <2 RK_PC3 1 &pcfg_pull_none>, 997 <2 RK_PC4 1 &pcfg_pull_none>; 998 }; 999 }; 1000 1001 pwm0 { 1002 pwm0_pin: pwm0-pin { 1003 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; 1004 }; 1005 }; 1006 1007 pwm1 { 1008 pwm1_pin: pwm1-pin { 1009 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; 1010 }; 1011 }; 1012 1013 pwm3 { 1014 pwm3_pin: pwm3-pin { 1015 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>; 1016 }; 1017 }; 1018 1019 sdio0 { 1020 sdio0_bus1: sdio0-bus1 { 1021 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; 1022 }; 1023 1024 sdio0_bus4: sdio0-bus4 { 1025 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, 1026 <2 RK_PD5 1 &pcfg_pull_up>, 1027 <2 RK_PD6 1 &pcfg_pull_up>, 1028 <2 RK_PD7 1 &pcfg_pull_up>; 1029 }; 1030 1031 sdio0_cmd: sdio0-cmd { 1032 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; 1033 }; 1034 1035 sdio0_clk: sdio0-clk { 1036 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 1037 }; 1038 1039 sdio0_cd: sdio0-cd { 1040 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; 1041 }; 1042 1043 sdio0_wp: sdio0-wp { 1044 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; 1045 }; 1046 1047 sdio0_pwr: sdio0-pwr { 1048 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; 1049 }; 1050 1051 sdio0_bkpwr: sdio0-bkpwr { 1052 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; 1053 }; 1054 1055 sdio0_int: sdio0-int { 1056 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; 1057 }; 1058 }; 1059 1060 sdmmc { 1061 sdmmc_clk: sdmmc-clk { 1062 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1063 }; 1064 1065 sdmmc_cmd: sdmmc-cmd { 1066 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1067 }; 1068 1069 sdmmc_cd: sdmmc-cd { 1070 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1071 }; 1072 1073 sdmmc_bus1: sdmmc-bus1 { 1074 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; 1075 }; 1076 1077 sdmmc_bus4: sdmmc-bus4 { 1078 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, 1079 <2 RK_PA6 1 &pcfg_pull_up>, 1080 <2 RK_PA7 1 &pcfg_pull_up>, 1081 <2 RK_PB0 1 &pcfg_pull_up>; 1082 }; 1083 }; 1084 1085 spdif { 1086 spdif_tx: spdif-tx { 1087 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1088 }; 1089 }; 1090 1091 spi0 { 1092 spi0_clk: spi0-clk { 1093 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; 1094 }; 1095 spi0_cs0: spi0-cs0 { 1096 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; 1097 }; 1098 spi0_cs1: spi0-cs1 { 1099 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; 1100 }; 1101 spi0_tx: spi0-tx { 1102 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; 1103 }; 1104 spi0_rx: spi0-rx { 1105 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; 1106 }; 1107 }; 1108 1109 spi1 { 1110 spi1_clk: spi1-clk { 1111 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 1112 }; 1113 spi1_cs0: spi1-cs0 { 1114 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; 1115 }; 1116 spi1_cs1: spi1-cs1 { 1117 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; 1118 }; 1119 spi1_rx: spi1-rx { 1120 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; 1121 }; 1122 spi1_tx: spi1-tx { 1123 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; 1124 }; 1125 }; 1126 1127 spi2 { 1128 spi2_clk: spi2-clk { 1129 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; 1130 }; 1131 spi2_cs0: spi2-cs0 { 1132 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1133 }; 1134 spi2_rx: spi2-rx { 1135 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; 1136 }; 1137 spi2_tx: spi2-tx { 1138 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1139 }; 1140 }; 1141 1142 tsadc { 1143 otp_pin: otp-pin { 1144 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 1145 }; 1146 1147 otp_out: otp-out { 1148 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1149 }; 1150 }; 1151 1152 uart0 { 1153 uart0_xfer: uart0-xfer { 1154 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, 1155 <2 RK_PD1 1 &pcfg_pull_none>; 1156 }; 1157 1158 uart0_cts: uart0-cts { 1159 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 1160 }; 1161 1162 uart0_rts: uart0-rts { 1163 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 1164 }; 1165 }; 1166 1167 uart1 { 1168 uart1_xfer: uart1-xfer { 1169 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, 1170 <0 RK_PC5 3 &pcfg_pull_none>; 1171 }; 1172 1173 uart1_cts: uart1-cts { 1174 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; 1175 }; 1176 1177 uart1_rts: uart1-rts { 1178 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; 1179 }; 1180 }; 1181 1182 uart2 { 1183 uart2_xfer: uart2-xfer { 1184 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, 1185 <2 RK_PA5 2 &pcfg_pull_none>; 1186 }; 1187 /* no rts / cts for uart2 */ 1188 }; 1189 1190 uart3 { 1191 uart3_xfer: uart3-xfer { 1192 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, 1193 <3 RK_PD6 3 &pcfg_pull_none>; 1194 }; 1195 1196 uart3_cts: uart3-cts { 1197 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; 1198 }; 1199 1200 uart3_rts: uart3-rts { 1201 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; 1202 }; 1203 }; 1204 1205 uart4 { 1206 uart4_xfer: uart4-xfer { 1207 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, 1208 <0 RK_PD2 3 &pcfg_pull_none>; 1209 }; 1210 1211 uart4_cts: uart4-cts { 1212 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; 1213 }; 1214 1215 uart4_rts: uart4-rts { 1216 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; 1217 }; 1218 }; 1219 }; 1220}; 1221