1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2/* 3 * Realtek RTD1293/RTD1295/RTD1296 SoC 4 * 5 * Copyright (c) 2016-2019 Andreas Färber 6 */ 7 8/memreserve/ 0x0000000000000000 0x0000000000030000; 9/memreserve/ 0x0000000000030000 0x00000000000d0000; 10/memreserve/ 0x0000000001b00000 0x00000000004be000; 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/realtek,rtd1295.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 reserved-memory { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 rpc_comm: rpc@1f000 { 26 reg = <0x1f000 0x1000>; 27 }; 28 29 rpc_ringbuf: rpc@1ffe000 { 30 reg = <0x1ffe000 0x4000>; 31 }; 32 33 tee: tee@10100000 { 34 reg = <0x10100000 0xf00000>; 35 no-map; 36 }; 37 }; 38 39 arm_pmu: arm-pmu { 40 compatible = "arm,cortex-a53-pmu"; 41 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 42 }; 43 44 osc27M: osc { 45 compatible = "fixed-clock"; 46 clock-frequency = <27000000>; 47 #clock-cells = <0>; 48 clock-output-names = "osc27M"; 49 }; 50 51 soc { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 /* Exclude up to 2 GiB of RAM */ 56 ranges = <0x80000000 0x80000000 0x80000000>; 57 58 rbus: bus@98000000 { 59 compatible = "simple-bus"; 60 reg = <0x98000000 0x200000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 ranges = <0x0 0x98000000 0x200000>; 64 65 reset1: reset-controller@0 { 66 compatible = "snps,dw-low-reset"; 67 reg = <0x0 0x4>; 68 #reset-cells = <1>; 69 }; 70 71 reset2: reset-controller@4 { 72 compatible = "snps,dw-low-reset"; 73 reg = <0x4 0x4>; 74 #reset-cells = <1>; 75 }; 76 77 reset3: reset-controller@8 { 78 compatible = "snps,dw-low-reset"; 79 reg = <0x8 0x4>; 80 #reset-cells = <1>; 81 }; 82 83 reset4: reset-controller@50 { 84 compatible = "snps,dw-low-reset"; 85 reg = <0x50 0x4>; 86 #reset-cells = <1>; 87 }; 88 89 iso_reset: reset-controller@7088 { 90 compatible = "snps,dw-low-reset"; 91 reg = <0x7088 0x4>; 92 #reset-cells = <1>; 93 }; 94 95 wdt: watchdog@7680 { 96 compatible = "realtek,rtd1295-watchdog"; 97 reg = <0x7680 0x100>; 98 clocks = <&osc27M>; 99 }; 100 101 uart0: serial@7800 { 102 compatible = "snps,dw-apb-uart"; 103 reg = <0x7800 0x400>; 104 reg-shift = <2>; 105 reg-io-width = <4>; 106 clock-frequency = <27000000>; 107 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; 108 status = "disabled"; 109 }; 110 111 uart1: serial@1b200 { 112 compatible = "snps,dw-apb-uart"; 113 reg = <0x1b200 0x100>; 114 reg-shift = <2>; 115 reg-io-width = <4>; 116 clock-frequency = <432000000>; 117 resets = <&reset2 RTD1295_RSTN_UR1>; 118 status = "disabled"; 119 }; 120 121 uart2: serial@1b400 { 122 compatible = "snps,dw-apb-uart"; 123 reg = <0x1b400 0x100>; 124 reg-shift = <2>; 125 reg-io-width = <4>; 126 clock-frequency = <432000000>; 127 resets = <&reset2 RTD1295_RSTN_UR2>; 128 status = "disabled"; 129 }; 130 }; 131 132 gic: interrupt-controller@ff011000 { 133 compatible = "arm,gic-400"; 134 reg = <0xff011000 0x1000>, 135 <0xff012000 0x2000>, 136 <0xff014000 0x2000>, 137 <0xff016000 0x2000>; 138 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 139 interrupt-controller; 140 #interrupt-cells = <3>; 141 }; 142 }; 143}; 144