1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2/* 3 * Realtek RTD1293/RTD1295/RTD1296 SoC 4 * 5 * Copyright (c) 2016-2019 Andreas Färber 6 */ 7 8/memreserve/ 0x0000000000000000 0x0000000000030000; 9/memreserve/ 0x0000000000030000 0x00000000000d0000; 10/memreserve/ 0x0000000001b00000 0x00000000004be000; 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/realtek,rtd1295.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 reserved-memory { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 rpc_comm: rpc@1f000 { 26 reg = <0x1f000 0x1000>; 27 }; 28 29 rpc_ringbuf: rpc@1ffe000 { 30 reg = <0x1ffe000 0x4000>; 31 }; 32 33 tee: tee@10100000 { 34 reg = <0x10100000 0xf00000>; 35 no-map; 36 }; 37 }; 38 39 arm_pmu: arm-pmu { 40 compatible = "arm,cortex-a53-pmu"; 41 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 42 }; 43 44 osc27M: osc { 45 compatible = "fixed-clock"; 46 clock-frequency = <27000000>; 47 #clock-cells = <0>; 48 clock-output-names = "osc27M"; 49 }; 50 51 soc { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 /* Exclude up to 2 GiB of RAM */ 56 ranges = <0x80000000 0x80000000 0x80000000>; 57 58 reset1: reset-controller@98000000 { 59 compatible = "snps,dw-low-reset"; 60 reg = <0x98000000 0x4>; 61 #reset-cells = <1>; 62 }; 63 64 reset2: reset-controller@98000004 { 65 compatible = "snps,dw-low-reset"; 66 reg = <0x98000004 0x4>; 67 #reset-cells = <1>; 68 }; 69 70 reset3: reset-controller@98000008 { 71 compatible = "snps,dw-low-reset"; 72 reg = <0x98000008 0x4>; 73 #reset-cells = <1>; 74 }; 75 76 reset4: reset-controller@98000050 { 77 compatible = "snps,dw-low-reset"; 78 reg = <0x98000050 0x4>; 79 #reset-cells = <1>; 80 }; 81 82 iso_reset: reset-controller@98007088 { 83 compatible = "snps,dw-low-reset"; 84 reg = <0x98007088 0x4>; 85 #reset-cells = <1>; 86 }; 87 88 wdt: watchdog@98007680 { 89 compatible = "realtek,rtd1295-watchdog"; 90 reg = <0x98007680 0x100>; 91 clocks = <&osc27M>; 92 }; 93 94 uart0: serial@98007800 { 95 compatible = "snps,dw-apb-uart"; 96 reg = <0x98007800 0x400>; 97 reg-shift = <2>; 98 reg-io-width = <4>; 99 clock-frequency = <27000000>; 100 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; 101 status = "disabled"; 102 }; 103 104 uart1: serial@9801b200 { 105 compatible = "snps,dw-apb-uart"; 106 reg = <0x9801b200 0x100>; 107 reg-shift = <2>; 108 reg-io-width = <4>; 109 clock-frequency = <432000000>; 110 resets = <&reset2 RTD1295_RSTN_UR1>; 111 status = "disabled"; 112 }; 113 114 uart2: serial@9801b400 { 115 compatible = "snps,dw-apb-uart"; 116 reg = <0x9801b400 0x100>; 117 reg-shift = <2>; 118 reg-io-width = <4>; 119 clock-frequency = <432000000>; 120 resets = <&reset2 RTD1295_RSTN_UR2>; 121 status = "disabled"; 122 }; 123 124 gic: interrupt-controller@ff011000 { 125 compatible = "arm,gic-400"; 126 reg = <0xff011000 0x1000>, 127 <0xff012000 0x2000>, 128 <0xff014000 0x2000>, 129 <0xff016000 0x2000>; 130 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 131 interrupt-controller; 132 #interrupt-cells = <3>; 133 }; 134 }; 135}; 136