1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2/* 3 * Realtek RTD1293/RTD1295/RTD1296 SoC 4 * 5 * Copyright (c) 2016-2019 Andreas Färber 6 */ 7 8/memreserve/ 0x0000000000000000 0x000000000001f000; 9/memreserve/ 0x000000000001f000 0x00000000000e1000; 10/memreserve/ 0x0000000001b00000 0x00000000004be000; 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/realtek,rtd1295.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 reserved-memory { 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges; 24 25 rpc_comm: rpc@1f000 { 26 reg = <0x1f000 0x1000>; 27 }; 28 29 rpc_ringbuf: rpc@1ffe000 { 30 reg = <0x1ffe000 0x4000>; 31 }; 32 33 tee: tee@10100000 { 34 reg = <0x10100000 0xf00000>; 35 no-map; 36 }; 37 }; 38 39 arm_pmu: arm-pmu { 40 compatible = "arm,cortex-a53-pmu"; 41 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 42 }; 43 44 osc27M: osc { 45 compatible = "fixed-clock"; 46 clock-frequency = <27000000>; 47 #clock-cells = <0>; 48 clock-output-names = "osc27M"; 49 }; 50 51 soc { 52 compatible = "simple-bus"; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ 56 /* Exclude up to 2 GiB of RAM */ 57 <0x80000000 0x80000000 0x80000000>; 58 59 rbus: bus@98000000 { 60 compatible = "simple-bus"; 61 reg = <0x98000000 0x200000>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges = <0x0 0x98000000 0x200000>; 65 66 reset1: reset-controller@0 { 67 compatible = "snps,dw-low-reset"; 68 reg = <0x0 0x4>; 69 #reset-cells = <1>; 70 }; 71 72 reset2: reset-controller@4 { 73 compatible = "snps,dw-low-reset"; 74 reg = <0x4 0x4>; 75 #reset-cells = <1>; 76 }; 77 78 reset3: reset-controller@8 { 79 compatible = "snps,dw-low-reset"; 80 reg = <0x8 0x4>; 81 #reset-cells = <1>; 82 }; 83 84 reset4: reset-controller@50 { 85 compatible = "snps,dw-low-reset"; 86 reg = <0x50 0x4>; 87 #reset-cells = <1>; 88 }; 89 90 iso_reset: reset-controller@7088 { 91 compatible = "snps,dw-low-reset"; 92 reg = <0x7088 0x4>; 93 #reset-cells = <1>; 94 }; 95 96 wdt: watchdog@7680 { 97 compatible = "realtek,rtd1295-watchdog"; 98 reg = <0x7680 0x100>; 99 clocks = <&osc27M>; 100 }; 101 102 uart0: serial@7800 { 103 compatible = "snps,dw-apb-uart"; 104 reg = <0x7800 0x400>; 105 reg-shift = <2>; 106 reg-io-width = <4>; 107 clock-frequency = <27000000>; 108 resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; 109 status = "disabled"; 110 }; 111 112 uart1: serial@1b200 { 113 compatible = "snps,dw-apb-uart"; 114 reg = <0x1b200 0x100>; 115 reg-shift = <2>; 116 reg-io-width = <4>; 117 clock-frequency = <432000000>; 118 resets = <&reset2 RTD1295_RSTN_UR1>; 119 status = "disabled"; 120 }; 121 122 uart2: serial@1b400 { 123 compatible = "snps,dw-apb-uart"; 124 reg = <0x1b400 0x100>; 125 reg-shift = <2>; 126 reg-io-width = <4>; 127 clock-frequency = <432000000>; 128 resets = <&reset2 RTD1295_RSTN_UR2>; 129 status = "disabled"; 130 }; 131 }; 132 133 gic: interrupt-controller@ff011000 { 134 compatible = "arm,gic-400"; 135 reg = <0xff011000 0x1000>, 136 <0xff012000 0x2000>, 137 <0xff014000 0x2000>, 138 <0xff016000 0x2000>; 139 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 140 interrupt-controller; 141 #interrupt-cells = <3>; 142 }; 143 }; 144}; 145