1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sm6350-camcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm6350.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <76800000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 clock-frequency = <32764>; 38 #clock-cells = <0>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo560"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 enable-method = "psci"; 52 capacity-dmips-mhz = <1024>; 53 dynamic-power-coefficient = <100>; 54 next-level-cache = <&L2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 58 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 59 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 #cooling-cells = <2>; 63 L2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&L3_0>; 68 L3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 CPU1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo560"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <1024>; 83 dynamic-power-coefficient = <100>; 84 next-level-cache = <&L2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 operating-points-v2 = <&cpu0_opp_table>; 87 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 88 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 89 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 90 power-domains = <&CPU_PD1>; 91 power-domain-names = "psci"; 92 #cooling-cells = <2>; 93 L2_100: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&L3_0>; 98 }; 99 }; 100 101 CPU2: cpu@200 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo560"; 104 reg = <0x0 0x200>; 105 clocks = <&cpufreq_hw 0>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <1024>; 108 dynamic-power-coefficient = <100>; 109 next-level-cache = <&L2_200>; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 operating-points-v2 = <&cpu0_opp_table>; 112 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 113 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 114 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 115 power-domains = <&CPU_PD2>; 116 power-domain-names = "psci"; 117 #cooling-cells = <2>; 118 L2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo560"; 129 reg = <0x0 0x300>; 130 clocks = <&cpufreq_hw 0>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <1024>; 133 dynamic-power-coefficient = <100>; 134 next-level-cache = <&L2_300>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 operating-points-v2 = <&cpu0_opp_table>; 137 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 138 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 140 power-domains = <&CPU_PD3>; 141 power-domain-names = "psci"; 142 #cooling-cells = <2>; 143 L2_300: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-unified; 147 next-level-cache = <&L3_0>; 148 }; 149 }; 150 151 CPU4: cpu@400 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo560"; 154 reg = <0x0 0x400>; 155 clocks = <&cpufreq_hw 0>; 156 enable-method = "psci"; 157 capacity-dmips-mhz = <1024>; 158 dynamic-power-coefficient = <100>; 159 next-level-cache = <&L2_400>; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 operating-points-v2 = <&cpu0_opp_table>; 162 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 163 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 164 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 165 power-domains = <&CPU_PD4>; 166 power-domain-names = "psci"; 167 #cooling-cells = <2>; 168 L2_400: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 cache-unified; 172 next-level-cache = <&L3_0>; 173 }; 174 }; 175 176 CPU5: cpu@500 { 177 device_type = "cpu"; 178 compatible = "qcom,kryo560"; 179 reg = <0x0 0x500>; 180 clocks = <&cpufreq_hw 0>; 181 enable-method = "psci"; 182 capacity-dmips-mhz = <1024>; 183 dynamic-power-coefficient = <100>; 184 next-level-cache = <&L2_500>; 185 qcom,freq-domain = <&cpufreq_hw 0>; 186 operating-points-v2 = <&cpu0_opp_table>; 187 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 188 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 189 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 190 power-domains = <&CPU_PD5>; 191 power-domain-names = "psci"; 192 #cooling-cells = <2>; 193 L2_500: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&L3_0>; 198 }; 199 }; 200 201 CPU6: cpu@600 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo560"; 204 reg = <0x0 0x600>; 205 clocks = <&cpufreq_hw 1>; 206 enable-method = "psci"; 207 capacity-dmips-mhz = <1894>; 208 dynamic-power-coefficient = <703>; 209 next-level-cache = <&L2_600>; 210 qcom,freq-domain = <&cpufreq_hw 1>; 211 operating-points-v2 = <&cpu6_opp_table>; 212 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 213 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 214 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 215 power-domains = <&CPU_PD6>; 216 power-domain-names = "psci"; 217 #cooling-cells = <2>; 218 L2_600: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-unified; 222 next-level-cache = <&L3_0>; 223 }; 224 }; 225 226 CPU7: cpu@700 { 227 device_type = "cpu"; 228 compatible = "qcom,kryo560"; 229 reg = <0x0 0x700>; 230 clocks = <&cpufreq_hw 1>; 231 enable-method = "psci"; 232 capacity-dmips-mhz = <1894>; 233 dynamic-power-coefficient = <703>; 234 next-level-cache = <&L2_700>; 235 qcom,freq-domain = <&cpufreq_hw 1>; 236 operating-points-v2 = <&cpu6_opp_table>; 237 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 238 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 239 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 240 power-domains = <&CPU_PD7>; 241 power-domain-names = "psci"; 242 #cooling-cells = <2>; 243 L2_700: l2-cache { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-unified; 247 next-level-cache = <&L3_0>; 248 }; 249 }; 250 251 cpu-map { 252 cluster0 { 253 core0 { 254 cpu = <&CPU0>; 255 }; 256 257 core1 { 258 cpu = <&CPU1>; 259 }; 260 261 core2 { 262 cpu = <&CPU2>; 263 }; 264 265 core3 { 266 cpu = <&CPU3>; 267 }; 268 269 core4 { 270 cpu = <&CPU4>; 271 }; 272 273 core5 { 274 cpu = <&CPU5>; 275 }; 276 277 core6 { 278 cpu = <&CPU6>; 279 }; 280 281 core7 { 282 cpu = <&CPU7>; 283 }; 284 }; 285 }; 286 287 domain-idle-states { 288 CLUSTER_SLEEP_PC: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 arm,psci-suspend-param = <0x41000044>; 291 entry-latency-us = <2752>; 292 exit-latency-us = <3048>; 293 min-residency-us = <6118>; 294 }; 295 296 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 297 compatible = "domain-idle-state"; 298 arm,psci-suspend-param = <0x41001244>; 299 entry-latency-us = <3638>; 300 exit-latency-us = <4562>; 301 min-residency-us = <8467>; 302 }; 303 304 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 305 compatible = "domain-idle-state"; 306 arm,psci-suspend-param = <0x4100b244>; 307 entry-latency-us = <3263>; 308 exit-latency-us = <6562>; 309 min-residency-us = <9987>; 310 }; 311 }; 312 313 cpu_idle_states: idle-states { 314 entry-method = "psci"; 315 316 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 317 compatible = "arm,idle-state"; 318 idle-state-name = "little-power-collapse"; 319 arm,psci-suspend-param = <0x40000003>; 320 entry-latency-us = <549>; 321 exit-latency-us = <901>; 322 min-residency-us = <1774>; 323 local-timer-stop; 324 }; 325 326 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 327 compatible = "arm,idle-state"; 328 idle-state-name = "little-rail-power-collapse"; 329 arm,psci-suspend-param = <0x40000004>; 330 entry-latency-us = <702>; 331 exit-latency-us = <915>; 332 min-residency-us = <4001>; 333 local-timer-stop; 334 }; 335 336 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 337 compatible = "arm,idle-state"; 338 idle-state-name = "big-power-collapse"; 339 arm,psci-suspend-param = <0x40000003>; 340 entry-latency-us = <523>; 341 exit-latency-us = <1244>; 342 min-residency-us = <2207>; 343 local-timer-stop; 344 }; 345 346 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 347 compatible = "arm,idle-state"; 348 idle-state-name = "big-rail-power-collapse"; 349 arm,psci-suspend-param = <0x40000004>; 350 entry-latency-us = <526>; 351 exit-latency-us = <1854>; 352 min-residency-us = <5555>; 353 local-timer-stop; 354 }; 355 }; 356 }; 357 358 firmware { 359 scm: scm { 360 compatible = "qcom,scm-sm6350", "qcom,scm"; 361 #reset-cells = <1>; 362 }; 363 }; 364 365 memory@80000000 { 366 device_type = "memory"; 367 /* We expect the bootloader to fill in the size */ 368 reg = <0x0 0x80000000 0x0 0x0>; 369 }; 370 371 cpu0_opp_table: opp-table-cpu0 { 372 compatible = "operating-points-v2"; 373 opp-shared; 374 375 opp-300000000 { 376 opp-hz = /bits/ 64 <300000000>; 377 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 378 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 379 }; 380 381 opp-576000000 { 382 opp-hz = /bits/ 64 <576000000>; 383 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 384 }; 385 386 opp-768000000 { 387 opp-hz = /bits/ 64 <768000000>; 388 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 389 }; 390 391 opp-1017600000 { 392 opp-hz = /bits/ 64 <1017600000>; 393 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 394 }; 395 396 opp-1248000000 { 397 opp-hz = /bits/ 64 <1248000000>; 398 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 399 }; 400 401 opp-1324800000 { 402 opp-hz = /bits/ 64 <1324800000>; 403 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 404 }; 405 406 opp-1516800000 { 407 opp-hz = /bits/ 64 <1516800000>; 408 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 409 }; 410 411 opp-1612800000 { 412 opp-hz = /bits/ 64 <1612800000>; 413 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 414 }; 415 416 opp-1708800000 { 417 opp-hz = /bits/ 64 <1708800000>; 418 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 419 }; 420 }; 421 422 cpu6_opp_table: opp-table-cpu6 { 423 compatible = "operating-points-v2"; 424 opp-shared; 425 426 opp-300000000 { 427 opp-hz = /bits/ 64 <300000000>; 428 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 429 }; 430 431 opp-787200000 { 432 opp-hz = /bits/ 64 <787200000>; 433 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 434 }; 435 436 opp-979200000 { 437 opp-hz = /bits/ 64 <979200000>; 438 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 439 }; 440 441 opp-1036800000 { 442 opp-hz = /bits/ 64 <1036800000>; 443 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 444 }; 445 446 opp-1248000000 { 447 opp-hz = /bits/ 64 <1248000000>; 448 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 449 }; 450 451 opp-1401600000 { 452 opp-hz = /bits/ 64 <1401600000>; 453 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 454 }; 455 456 opp-1555200000 { 457 opp-hz = /bits/ 64 <1555200000>; 458 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 459 }; 460 461 opp-1766400000 { 462 opp-hz = /bits/ 64 <1766400000>; 463 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 464 }; 465 466 opp-1900800000 { 467 opp-hz = /bits/ 64 <1900800000>; 468 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 469 }; 470 471 opp-2073600000 { 472 opp-hz = /bits/ 64 <2073600000>; 473 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 474 }; 475 }; 476 477 qup_opp_table: opp-table-qup { 478 compatible = "operating-points-v2"; 479 480 opp-75000000 { 481 opp-hz = /bits/ 64 <75000000>; 482 required-opps = <&rpmhpd_opp_low_svs>; 483 }; 484 485 opp-100000000 { 486 opp-hz = /bits/ 64 <100000000>; 487 required-opps = <&rpmhpd_opp_svs>; 488 }; 489 490 opp-128000000 { 491 opp-hz = /bits/ 64 <128000000>; 492 required-opps = <&rpmhpd_opp_nom>; 493 }; 494 }; 495 496 pmu { 497 compatible = "arm,armv8-pmuv3"; 498 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 499 }; 500 501 psci { 502 compatible = "arm,psci-1.0"; 503 method = "smc"; 504 505 CPU_PD0: power-domain-cpu0 { 506 #power-domain-cells = <0>; 507 power-domains = <&CLUSTER_PD>; 508 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 509 }; 510 511 CPU_PD1: power-domain-cpu1 { 512 #power-domain-cells = <0>; 513 power-domains = <&CLUSTER_PD>; 514 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 515 }; 516 517 CPU_PD2: power-domain-cpu2 { 518 #power-domain-cells = <0>; 519 power-domains = <&CLUSTER_PD>; 520 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 521 }; 522 523 CPU_PD3: power-domain-cpu3 { 524 #power-domain-cells = <0>; 525 power-domains = <&CLUSTER_PD>; 526 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 527 }; 528 529 CPU_PD4: power-domain-cpu4 { 530 #power-domain-cells = <0>; 531 power-domains = <&CLUSTER_PD>; 532 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 533 }; 534 535 CPU_PD5: power-domain-cpu5 { 536 #power-domain-cells = <0>; 537 power-domains = <&CLUSTER_PD>; 538 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 539 }; 540 541 CPU_PD6: power-domain-cpu6 { 542 #power-domain-cells = <0>; 543 power-domains = <&CLUSTER_PD>; 544 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 545 }; 546 547 CPU_PD7: power-domain-cpu7 { 548 #power-domain-cells = <0>; 549 power-domains = <&CLUSTER_PD>; 550 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 551 }; 552 553 CLUSTER_PD: power-domain-cpu-cluster0 { 554 #power-domain-cells = <0>; 555 domain-idle-states = <&CLUSTER_SLEEP_PC 556 &CLUSTER_SLEEP_CX_RET 557 &CLUSTER_AOSS_SLEEP>; 558 }; 559 }; 560 561 reserved_memory: reserved-memory { 562 #address-cells = <2>; 563 #size-cells = <2>; 564 ranges; 565 566 hyp_mem: memory@80000000 { 567 reg = <0 0x80000000 0 0x600000>; 568 no-map; 569 }; 570 571 xbl_aop_mem: memory@80700000 { 572 reg = <0 0x80700000 0 0x160000>; 573 no-map; 574 }; 575 576 cmd_db: memory@80860000 { 577 compatible = "qcom,cmd-db"; 578 reg = <0 0x80860000 0 0x20000>; 579 no-map; 580 }; 581 582 sec_apps_mem: memory@808ff000 { 583 reg = <0 0x808ff000 0 0x1000>; 584 no-map; 585 }; 586 587 smem_mem: memory@80900000 { 588 reg = <0 0x80900000 0 0x200000>; 589 no-map; 590 }; 591 592 cdsp_sec_mem: memory@80b00000 { 593 reg = <0 0x80b00000 0 0x1e00000>; 594 no-map; 595 }; 596 597 pil_camera_mem: memory@86000000 { 598 reg = <0 0x86000000 0 0x500000>; 599 no-map; 600 }; 601 602 pil_npu_mem: memory@86500000 { 603 reg = <0 0x86500000 0 0x500000>; 604 no-map; 605 }; 606 607 pil_video_mem: memory@86a00000 { 608 reg = <0 0x86a00000 0 0x500000>; 609 no-map; 610 }; 611 612 pil_cdsp_mem: memory@86f00000 { 613 reg = <0 0x86f00000 0 0x1e00000>; 614 no-map; 615 }; 616 617 pil_adsp_mem: memory@88d00000 { 618 reg = <0 0x88d00000 0 0x2800000>; 619 no-map; 620 }; 621 622 wlan_fw_mem: memory@8b500000 { 623 reg = <0 0x8b500000 0 0x200000>; 624 no-map; 625 }; 626 627 pil_ipa_fw_mem: memory@8b700000 { 628 reg = <0 0x8b700000 0 0x10000>; 629 no-map; 630 }; 631 632 pil_ipa_gsi_mem: memory@8b710000 { 633 reg = <0 0x8b710000 0 0x5400>; 634 no-map; 635 }; 636 637 pil_modem_mem: memory@8b800000 { 638 reg = <0 0x8b800000 0 0xf800000>; 639 no-map; 640 }; 641 642 cont_splash_memory: memory@a0000000 { 643 reg = <0 0xa0000000 0 0x2300000>; 644 no-map; 645 }; 646 647 dfps_data_memory: memory@a2300000 { 648 reg = <0 0xa2300000 0 0x100000>; 649 no-map; 650 }; 651 652 removed_region: memory@c0000000 { 653 reg = <0 0xc0000000 0 0x3900000>; 654 no-map; 655 }; 656 657 pil_gpu_mem: memory@f0d00000 { 658 reg = <0 0xf0d00000 0 0x1000>; 659 no-map; 660 }; 661 662 debug_region: memory@ffb00000 { 663 reg = <0 0xffb00000 0 0xc0000>; 664 no-map; 665 }; 666 667 last_log_region: memory@ffbc0000 { 668 reg = <0 0xffbc0000 0 0x40000>; 669 no-map; 670 }; 671 672 ramoops: ramoops@ffc00000 { 673 compatible = "ramoops"; 674 reg = <0 0xffc00000 0 0x100000>; 675 record-size = <0x1000>; 676 console-size = <0x40000>; 677 msg-size = <0x20000 0x20000>; 678 ecc-size = <16>; 679 no-map; 680 }; 681 682 cmdline_region: memory@ffd00000 { 683 reg = <0 0xffd00000 0 0x1000>; 684 no-map; 685 }; 686 }; 687 688 smem { 689 compatible = "qcom,smem"; 690 memory-region = <&smem_mem>; 691 hwlocks = <&tcsr_mutex 3>; 692 }; 693 694 smp2p-adsp { 695 compatible = "qcom,smp2p"; 696 qcom,smem = <443>, <429>; 697 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 698 IPCC_MPROC_SIGNAL_SMP2P 699 IRQ_TYPE_EDGE_RISING>; 700 mboxes = <&ipcc IPCC_CLIENT_LPASS 701 IPCC_MPROC_SIGNAL_SMP2P>; 702 703 qcom,local-pid = <0>; 704 qcom,remote-pid = <2>; 705 706 smp2p_adsp_out: master-kernel { 707 qcom,entry-name = "master-kernel"; 708 #qcom,smem-state-cells = <1>; 709 }; 710 711 smp2p_adsp_in: slave-kernel { 712 qcom,entry-name = "slave-kernel"; 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 }; 717 718 smp2p-cdsp { 719 compatible = "qcom,smp2p"; 720 qcom,smem = <94>, <432>; 721 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 722 IPCC_MPROC_SIGNAL_SMP2P 723 IRQ_TYPE_EDGE_RISING>; 724 mboxes = <&ipcc IPCC_CLIENT_CDSP 725 IPCC_MPROC_SIGNAL_SMP2P>; 726 727 qcom,local-pid = <0>; 728 qcom,remote-pid = <5>; 729 730 smp2p_cdsp_out: master-kernel { 731 qcom,entry-name = "master-kernel"; 732 #qcom,smem-state-cells = <1>; 733 }; 734 735 smp2p_cdsp_in: slave-kernel { 736 qcom,entry-name = "slave-kernel"; 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 }; 740 }; 741 742 smp2p-mpss { 743 compatible = "qcom,smp2p"; 744 qcom,smem = <435>, <428>; 745 746 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 747 IPCC_MPROC_SIGNAL_SMP2P 748 IRQ_TYPE_EDGE_RISING>; 749 mboxes = <&ipcc IPCC_CLIENT_MPSS 750 IPCC_MPROC_SIGNAL_SMP2P>; 751 752 qcom,local-pid = <0>; 753 qcom,remote-pid = <1>; 754 755 modem_smp2p_out: master-kernel { 756 qcom,entry-name = "master-kernel"; 757 #qcom,smem-state-cells = <1>; 758 }; 759 760 modem_smp2p_in: slave-kernel { 761 qcom,entry-name = "slave-kernel"; 762 interrupt-controller; 763 #interrupt-cells = <2>; 764 }; 765 766 ipa_smp2p_out: ipa-ap-to-modem { 767 qcom,entry-name = "ipa"; 768 #qcom,smem-state-cells = <1>; 769 }; 770 771 ipa_smp2p_in: ipa-modem-to-ap { 772 qcom,entry-name = "ipa"; 773 interrupt-controller; 774 #interrupt-cells = <2>; 775 }; 776 }; 777 778 soc: soc@0 { 779 #address-cells = <2>; 780 #size-cells = <2>; 781 ranges = <0 0 0 0 0x10 0>; 782 dma-ranges = <0 0 0 0 0x10 0>; 783 compatible = "simple-bus"; 784 785 gcc: clock-controller@100000 { 786 compatible = "qcom,gcc-sm6350"; 787 reg = <0 0x00100000 0 0x1f0000>; 788 #clock-cells = <1>; 789 #reset-cells = <1>; 790 #power-domain-cells = <1>; 791 clock-names = "bi_tcxo", 792 "bi_tcxo_ao", 793 "sleep_clk"; 794 clocks = <&rpmhcc RPMH_CXO_CLK>, 795 <&rpmhcc RPMH_CXO_CLK_A>, 796 <&sleep_clk>; 797 }; 798 799 ipcc: mailbox@408000 { 800 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 801 reg = <0 0x00408000 0 0x1000>; 802 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 803 interrupt-controller; 804 #interrupt-cells = <3>; 805 #mbox-cells = <2>; 806 }; 807 808 qfprom: qfprom@784000 { 809 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 810 reg = <0 0x00784000 0 0x3000>; 811 #address-cells = <1>; 812 #size-cells = <1>; 813 814 gpu_speed_bin: gpu-speed-bin@2015 { 815 reg = <0x2015 0x1>; 816 bits = <0 8>; 817 }; 818 }; 819 820 rng: rng@793000 { 821 compatible = "qcom,prng-ee"; 822 reg = <0 0x00793000 0 0x1000>; 823 clocks = <&gcc GCC_PRNG_AHB_CLK>; 824 clock-names = "core"; 825 }; 826 827 sdhc_1: mmc@7c4000 { 828 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 829 reg = <0 0x007c4000 0 0x1000>, 830 <0 0x007c5000 0 0x1000>, 831 <0 0x007c8000 0 0x8000>; 832 reg-names = "hc", "cqhci", "ice"; 833 834 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "hc_irq", "pwr_irq"; 837 iommus = <&apps_smmu 0x60 0x0>; 838 839 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 840 <&gcc GCC_SDCC1_APPS_CLK>, 841 <&rpmhcc RPMH_CXO_CLK>; 842 clock-names = "iface", "core", "xo"; 843 resets = <&gcc GCC_SDCC1_BCR>; 844 qcom,dll-config = <0x000f642c>; 845 qcom,ddr-config = <0x80040868>; 846 power-domains = <&rpmhpd SM6350_CX>; 847 operating-points-v2 = <&sdhc1_opp_table>; 848 bus-width = <8>; 849 non-removable; 850 supports-cqe; 851 852 status = "disabled"; 853 854 sdhc1_opp_table: opp-table { 855 compatible = "operating-points-v2"; 856 857 opp-19200000 { 858 opp-hz = /bits/ 64 <19200000>; 859 required-opps = <&rpmhpd_opp_min_svs>; 860 }; 861 862 opp-100000000 { 863 opp-hz = /bits/ 64 <100000000>; 864 required-opps = <&rpmhpd_opp_low_svs>; 865 }; 866 867 opp-384000000 { 868 opp-hz = /bits/ 64 <384000000>; 869 required-opps = <&rpmhpd_opp_svs_l1>; 870 }; 871 }; 872 }; 873 874 gpi_dma0: dma-controller@800000 { 875 compatible = "qcom,sm6350-gpi-dma"; 876 reg = <0 0x00800000 0 0x60000>; 877 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 887 dma-channels = <10>; 888 dma-channel-mask = <0x1f>; 889 iommus = <&apps_smmu 0x56 0x0>; 890 #dma-cells = <3>; 891 status = "disabled"; 892 }; 893 894 qupv3_id_0: geniqup@8c0000 { 895 compatible = "qcom,geni-se-qup"; 896 reg = <0x0 0x008c0000 0x0 0x2000>; 897 clock-names = "m-ahb", "s-ahb"; 898 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 899 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 900 #address-cells = <2>; 901 #size-cells = <2>; 902 iommus = <&apps_smmu 0x43 0x0>; 903 ranges; 904 status = "disabled"; 905 906 i2c0: i2c@880000 { 907 compatible = "qcom,geni-i2c"; 908 reg = <0 0x00880000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_i2c0_default>; 913 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 914 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 915 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 920 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 921 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 922 interconnect-names = "qup-core", "qup-config", "qup-memory"; 923 status = "disabled"; 924 }; 925 926 uart1: serial@884000 { 927 compatible = "qcom,geni-uart"; 928 reg = <0 0x00884000 0 0x4000>; 929 clock-names = "se"; 930 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 933 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 934 power-domains = <&rpmhpd SM6350_CX>; 935 operating-points-v2 = <&qup_opp_table>; 936 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 937 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 938 interconnect-names = "qup-core", "qup-config"; 939 status = "disabled"; 940 }; 941 942 i2c2: i2c@888000 { 943 compatible = "qcom,geni-i2c"; 944 reg = <0 0x00888000 0 0x4000>; 945 clock-names = "se"; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&qup_i2c2_default>; 949 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 950 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 951 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 952 dma-names = "tx", "rx"; 953 #address-cells = <1>; 954 #size-cells = <0>; 955 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 956 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 957 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 958 interconnect-names = "qup-core", "qup-config", "qup-memory"; 959 status = "disabled"; 960 }; 961 }; 962 963 gpi_dma1: dma-controller@900000 { 964 compatible = "qcom,sm6350-gpi-dma"; 965 reg = <0 0x00900000 0 0x60000>; 966 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 976 dma-channels = <10>; 977 dma-channel-mask = <0x3f>; 978 iommus = <&apps_smmu 0x4d6 0x0>; 979 #dma-cells = <3>; 980 status = "disabled"; 981 }; 982 983 qupv3_id_1: geniqup@9c0000 { 984 compatible = "qcom,geni-se-qup"; 985 reg = <0x0 0x009c0000 0x0 0x2000>; 986 clock-names = "m-ahb", "s-ahb"; 987 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 988 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 989 #address-cells = <2>; 990 #size-cells = <2>; 991 iommus = <&apps_smmu 0x4c3 0x0>; 992 ranges; 993 status = "disabled"; 994 995 i2c6: i2c@980000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0 0x00980000 0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c6_default>; 1002 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1003 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1004 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1005 dma-names = "tx", "rx"; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1009 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1010 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1011 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1012 status = "disabled"; 1013 }; 1014 1015 i2c7: i2c@984000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00984000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c7_default>; 1022 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1023 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1024 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1025 dma-names = "tx", "rx"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1029 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1030 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1031 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1032 status = "disabled"; 1033 }; 1034 1035 i2c8: i2c@988000 { 1036 compatible = "qcom,geni-i2c"; 1037 reg = <0 0x00988000 0 0x4000>; 1038 clock-names = "se"; 1039 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_i2c8_default>; 1042 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1043 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1044 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1045 dma-names = "tx", "rx"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1049 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1050 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1051 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1052 status = "disabled"; 1053 }; 1054 1055 uart9: serial@98c000 { 1056 compatible = "qcom,geni-debug-uart"; 1057 reg = <0 0x0098c000 0 0x4000>; 1058 clock-names = "se"; 1059 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&qup_uart9_default>; 1062 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1064 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 status = "disabled"; 1067 }; 1068 1069 i2c10: i2c@990000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0 0x00990000 0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_i2c10_default>; 1076 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1077 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1078 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1083 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1084 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1085 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1086 status = "disabled"; 1087 }; 1088 }; 1089 1090 config_noc: interconnect@1500000 { 1091 compatible = "qcom,sm6350-config-noc"; 1092 reg = <0 0x01500000 0 0x28000>; 1093 #interconnect-cells = <2>; 1094 qcom,bcm-voters = <&apps_bcm_voter>; 1095 }; 1096 1097 system_noc: interconnect@1620000 { 1098 compatible = "qcom,sm6350-system-noc"; 1099 reg = <0 0x01620000 0 0x17080>; 1100 #interconnect-cells = <2>; 1101 qcom,bcm-voters = <&apps_bcm_voter>; 1102 1103 clk_virt: interconnect-clk-virt { 1104 compatible = "qcom,sm6350-clk-virt"; 1105 #interconnect-cells = <2>; 1106 qcom,bcm-voters = <&apps_bcm_voter>; 1107 }; 1108 }; 1109 1110 aggre1_noc: interconnect@16e0000 { 1111 compatible = "qcom,sm6350-aggre1-noc"; 1112 reg = <0 0x016e0000 0 0x15080>; 1113 #interconnect-cells = <2>; 1114 qcom,bcm-voters = <&apps_bcm_voter>; 1115 }; 1116 1117 aggre2_noc: interconnect@1700000 { 1118 compatible = "qcom,sm6350-aggre2-noc"; 1119 reg = <0 0x01700000 0 0x1f880>; 1120 #interconnect-cells = <2>; 1121 qcom,bcm-voters = <&apps_bcm_voter>; 1122 1123 compute_noc: interconnect-compute-noc { 1124 compatible = "qcom,sm6350-compute-noc"; 1125 #interconnect-cells = <2>; 1126 qcom,bcm-voters = <&apps_bcm_voter>; 1127 }; 1128 }; 1129 1130 mmss_noc: interconnect@1740000 { 1131 compatible = "qcom,sm6350-mmss-noc"; 1132 reg = <0 0x01740000 0 0x1c100>; 1133 #interconnect-cells = <2>; 1134 qcom,bcm-voters = <&apps_bcm_voter>; 1135 }; 1136 1137 ufs_mem_hc: ufs@1d84000 { 1138 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1139 "jedec,ufs-2.0"; 1140 reg = <0 0x01d84000 0 0x3000>, 1141 <0 0x01d90000 0 0x8000>; 1142 reg-names = "std", "ice"; 1143 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1144 phys = <&ufs_mem_phy_lanes>; 1145 phy-names = "ufsphy"; 1146 lanes-per-direction = <2>; 1147 #reset-cells = <1>; 1148 resets = <&gcc GCC_UFS_PHY_BCR>; 1149 reset-names = "rst"; 1150 1151 power-domains = <&gcc UFS_PHY_GDSC>; 1152 1153 iommus = <&apps_smmu 0x80 0x0>; 1154 1155 clock-names = "core_clk", 1156 "bus_aggr_clk", 1157 "iface_clk", 1158 "core_clk_unipro", 1159 "ref_clk", 1160 "tx_lane0_sync_clk", 1161 "rx_lane0_sync_clk", 1162 "rx_lane1_sync_clk", 1163 "ice_core_clk"; 1164 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1165 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1166 <&gcc GCC_UFS_PHY_AHB_CLK>, 1167 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1168 <&rpmhcc RPMH_QLINK_CLK>, 1169 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1170 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1171 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1172 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1173 freq-table-hz = 1174 <50000000 200000000>, 1175 <0 0>, 1176 <0 0>, 1177 <37500000 150000000>, 1178 <75000000 300000000>, 1179 <0 0>, 1180 <0 0>, 1181 <0 0>, 1182 <0 0>; 1183 1184 status = "disabled"; 1185 }; 1186 1187 ufs_mem_phy: phy@1d87000 { 1188 compatible = "qcom,sm6350-qmp-ufs-phy"; 1189 reg = <0 0x01d87000 0 0x18c>; 1190 #address-cells = <2>; 1191 #size-cells = <2>; 1192 ranges; 1193 1194 clock-names = "ref", 1195 "ref_aux"; 1196 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1197 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1198 1199 resets = <&ufs_mem_hc 0>; 1200 reset-names = "ufsphy"; 1201 1202 status = "disabled"; 1203 1204 ufs_mem_phy_lanes: phy@1d87400 { 1205 reg = <0 0x01d87400 0 0x128>, 1206 <0 0x01d87600 0 0x1fc>, 1207 <0 0x01d87c00 0 0x1dc>, 1208 <0 0x01d87800 0 0x128>, 1209 <0 0x01d87a00 0 0x1fc>; 1210 #phy-cells = <0>; 1211 }; 1212 }; 1213 1214 ipa: ipa@1e40000 { 1215 compatible = "qcom,sm6350-ipa"; 1216 1217 iommus = <&apps_smmu 0x440 0x0>, 1218 <&apps_smmu 0x442 0x0>; 1219 reg = <0 0x01e40000 0 0x8000>, 1220 <0 0x01e50000 0 0x3000>, 1221 <0 0x01e04000 0 0x23000>; 1222 reg-names = "ipa-reg", 1223 "ipa-shared", 1224 "gsi"; 1225 1226 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1227 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1228 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1229 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1230 interrupt-names = "ipa", 1231 "gsi", 1232 "ipa-clock-query", 1233 "ipa-setup-ready"; 1234 1235 clocks = <&rpmhcc RPMH_IPA_CLK>; 1236 clock-names = "core"; 1237 1238 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1239 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1240 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1241 interconnect-names = "memory", "imem", "config"; 1242 1243 qcom,smem-states = <&ipa_smp2p_out 0>, 1244 <&ipa_smp2p_out 1>; 1245 qcom,smem-state-names = "ipa-clock-enabled-valid", 1246 "ipa-clock-enabled"; 1247 1248 status = "disabled"; 1249 }; 1250 1251 tcsr_mutex: hwlock@1f40000 { 1252 compatible = "qcom,tcsr-mutex"; 1253 reg = <0x0 0x01f40000 0x0 0x40000>; 1254 #hwlock-cells = <1>; 1255 }; 1256 1257 adsp: remoteproc@3000000 { 1258 compatible = "qcom,sm6350-adsp-pas"; 1259 reg = <0 0x03000000 0 0x100>; 1260 1261 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1262 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1263 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1264 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1265 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1266 interrupt-names = "wdog", "fatal", "ready", 1267 "handover", "stop-ack"; 1268 1269 clocks = <&rpmhcc RPMH_CXO_CLK>; 1270 clock-names = "xo"; 1271 1272 power-domains = <&rpmhpd SM6350_LCX>, 1273 <&rpmhpd SM6350_LMX>; 1274 power-domain-names = "lcx", "lmx"; 1275 1276 memory-region = <&pil_adsp_mem>; 1277 1278 qcom,qmp = <&aoss_qmp>; 1279 1280 qcom,smem-states = <&smp2p_adsp_out 0>; 1281 qcom,smem-state-names = "stop"; 1282 1283 status = "disabled"; 1284 1285 glink-edge { 1286 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1287 IPCC_MPROC_SIGNAL_GLINK_QMP 1288 IRQ_TYPE_EDGE_RISING>; 1289 mboxes = <&ipcc IPCC_CLIENT_LPASS 1290 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1291 1292 label = "lpass"; 1293 qcom,remote-pid = <2>; 1294 1295 fastrpc { 1296 compatible = "qcom,fastrpc"; 1297 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1298 label = "adsp"; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 1302 compute-cb@3 { 1303 compatible = "qcom,fastrpc-compute-cb"; 1304 reg = <3>; 1305 iommus = <&apps_smmu 0x1003 0x0>; 1306 }; 1307 1308 compute-cb@4 { 1309 compatible = "qcom,fastrpc-compute-cb"; 1310 reg = <4>; 1311 iommus = <&apps_smmu 0x1004 0x0>; 1312 }; 1313 1314 compute-cb@5 { 1315 compatible = "qcom,fastrpc-compute-cb"; 1316 reg = <5>; 1317 iommus = <&apps_smmu 0x1005 0x0>; 1318 qcom,nsessions = <5>; 1319 }; 1320 }; 1321 }; 1322 }; 1323 1324 gpu: gpu@3d00000 { 1325 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1326 reg = <0 0x03d00000 0 0x40000>, 1327 <0 0x03d9e000 0 0x1000>; 1328 reg-names = "kgsl_3d0_reg_memory", 1329 "cx_mem"; 1330 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1331 1332 iommus = <&adreno_smmu 0>; 1333 operating-points-v2 = <&gpu_opp_table>; 1334 qcom,gmu = <&gmu>; 1335 nvmem-cells = <&gpu_speed_bin>; 1336 nvmem-cell-names = "speed_bin"; 1337 1338 status = "disabled"; 1339 1340 zap-shader { 1341 memory-region = <&pil_gpu_mem>; 1342 }; 1343 1344 gpu_opp_table: opp-table { 1345 compatible = "operating-points-v2"; 1346 1347 opp-850000000 { 1348 opp-hz = /bits/ 64 <850000000>; 1349 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1350 opp-supported-hw = <0x02>; 1351 }; 1352 1353 opp-800000000 { 1354 opp-hz = /bits/ 64 <800000000>; 1355 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1356 opp-supported-hw = <0x04>; 1357 }; 1358 1359 opp-650000000 { 1360 opp-hz = /bits/ 64 <650000000>; 1361 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1362 opp-supported-hw = <0x08>; 1363 }; 1364 1365 opp-565000000 { 1366 opp-hz = /bits/ 64 <565000000>; 1367 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1368 opp-supported-hw = <0x10>; 1369 }; 1370 1371 opp-430000000 { 1372 opp-hz = /bits/ 64 <430000000>; 1373 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1374 opp-supported-hw = <0xff>; 1375 }; 1376 1377 opp-355000000 { 1378 opp-hz = /bits/ 64 <355000000>; 1379 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1380 opp-supported-hw = <0xff>; 1381 }; 1382 1383 opp-253000000 { 1384 opp-hz = /bits/ 64 <253000000>; 1385 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1386 opp-supported-hw = <0xff>; 1387 }; 1388 }; 1389 }; 1390 1391 adreno_smmu: iommu@3d40000 { 1392 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1393 reg = <0 0x03d40000 0 0x10000>; 1394 #iommu-cells = <1>; 1395 #global-interrupts = <2>; 1396 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1406 1407 clocks = <&gpucc GPU_CC_AHB_CLK>, 1408 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1409 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1410 clock-names = "ahb", 1411 "bus", 1412 "iface"; 1413 1414 power-domains = <&gpucc GPU_CX_GDSC>; 1415 }; 1416 1417 gmu: gmu@3d6a000 { 1418 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1419 reg = <0 0x03d6a000 0 0x31000>, 1420 <0 0x0b290000 0 0x10000>, 1421 <0 0x0b490000 0 0x10000>; 1422 reg-names = "gmu", 1423 "gmu_pdc", 1424 "gmu_pdc_seq"; 1425 1426 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1428 interrupt-names = "hfi", 1429 "gmu"; 1430 1431 clocks = <&gpucc GPU_CC_AHB_CLK>, 1432 <&gpucc GPU_CC_CX_GMU_CLK>, 1433 <&gpucc GPU_CC_CXO_CLK>, 1434 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1435 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1436 clock-names = "ahb", 1437 "gmu", 1438 "cxo", 1439 "axi", 1440 "memnoc"; 1441 1442 power-domains = <&gpucc GPU_CX_GDSC>, 1443 <&gpucc GPU_GX_GDSC>; 1444 power-domain-names = "cx", 1445 "gx"; 1446 1447 iommus = <&adreno_smmu 5>; 1448 1449 operating-points-v2 = <&gmu_opp_table>; 1450 1451 status = "disabled"; 1452 1453 gmu_opp_table: opp-table { 1454 compatible = "operating-points-v2"; 1455 1456 opp-200000000 { 1457 opp-hz = /bits/ 64 <200000000>; 1458 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1459 }; 1460 }; 1461 }; 1462 1463 gpucc: clock-controller@3d90000 { 1464 compatible = "qcom,sm6350-gpucc"; 1465 reg = <0 0x03d90000 0 0x9000>; 1466 clocks = <&rpmhcc RPMH_CXO_CLK>, 1467 <&gcc GCC_GPU_GPLL0_CLK>, 1468 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1469 clock-names = "bi_tcxo", 1470 "gcc_gpu_gpll0_clk_src", 1471 "gcc_gpu_gpll0_div_clk_src"; 1472 #clock-cells = <1>; 1473 #reset-cells = <1>; 1474 #power-domain-cells = <1>; 1475 }; 1476 1477 mpss: remoteproc@4080000 { 1478 compatible = "qcom,sm6350-mpss-pas"; 1479 reg = <0x0 0x04080000 0x0 0x4040>; 1480 1481 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1482 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1483 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1484 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1485 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1486 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1487 interrupt-names = "wdog", "fatal", "ready", "handover", 1488 "stop-ack", "shutdown-ack"; 1489 1490 clocks = <&rpmhcc RPMH_CXO_CLK>; 1491 clock-names = "xo"; 1492 1493 power-domains = <&rpmhpd SM6350_CX>, 1494 <&rpmhpd SM6350_MSS>; 1495 power-domain-names = "cx", "mss"; 1496 1497 memory-region = <&pil_modem_mem>; 1498 1499 qcom,qmp = <&aoss_qmp>; 1500 1501 qcom,smem-states = <&modem_smp2p_out 0>; 1502 qcom,smem-state-names = "stop"; 1503 1504 status = "disabled"; 1505 1506 glink-edge { 1507 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1508 IPCC_MPROC_SIGNAL_GLINK_QMP 1509 IRQ_TYPE_EDGE_RISING>; 1510 mboxes = <&ipcc IPCC_CLIENT_MPSS 1511 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1512 label = "modem"; 1513 qcom,remote-pid = <1>; 1514 }; 1515 }; 1516 1517 cdsp: remoteproc@8300000 { 1518 compatible = "qcom,sm6350-cdsp-pas"; 1519 reg = <0 0x08300000 0 0x10000>; 1520 1521 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1522 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1523 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1524 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1525 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1526 interrupt-names = "wdog", "fatal", "ready", 1527 "handover", "stop-ack"; 1528 1529 clocks = <&rpmhcc RPMH_CXO_CLK>; 1530 clock-names = "xo"; 1531 1532 power-domains = <&rpmhpd SM6350_CX>, 1533 <&rpmhpd SM6350_MX>; 1534 power-domain-names = "cx", "mx"; 1535 1536 memory-region = <&pil_cdsp_mem>; 1537 1538 qcom,qmp = <&aoss_qmp>; 1539 1540 qcom,smem-states = <&smp2p_cdsp_out 0>; 1541 qcom,smem-state-names = "stop"; 1542 1543 status = "disabled"; 1544 1545 glink-edge { 1546 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1547 IPCC_MPROC_SIGNAL_GLINK_QMP 1548 IRQ_TYPE_EDGE_RISING>; 1549 mboxes = <&ipcc IPCC_CLIENT_CDSP 1550 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1551 1552 label = "cdsp"; 1553 qcom,remote-pid = <5>; 1554 1555 fastrpc { 1556 compatible = "qcom,fastrpc"; 1557 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1558 label = "cdsp"; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 compute-cb@1 { 1563 compatible = "qcom,fastrpc-compute-cb"; 1564 reg = <1>; 1565 iommus = <&apps_smmu 0x1401 0x20>; 1566 }; 1567 1568 compute-cb@2 { 1569 compatible = "qcom,fastrpc-compute-cb"; 1570 reg = <2>; 1571 iommus = <&apps_smmu 0x1402 0x20>; 1572 }; 1573 1574 compute-cb@3 { 1575 compatible = "qcom,fastrpc-compute-cb"; 1576 reg = <3>; 1577 iommus = <&apps_smmu 0x1403 0x20>; 1578 }; 1579 1580 compute-cb@4 { 1581 compatible = "qcom,fastrpc-compute-cb"; 1582 reg = <4>; 1583 iommus = <&apps_smmu 0x1404 0x20>; 1584 }; 1585 1586 compute-cb@5 { 1587 compatible = "qcom,fastrpc-compute-cb"; 1588 reg = <5>; 1589 iommus = <&apps_smmu 0x1405 0x20>; 1590 }; 1591 1592 compute-cb@6 { 1593 compatible = "qcom,fastrpc-compute-cb"; 1594 reg = <6>; 1595 iommus = <&apps_smmu 0x1406 0x20>; 1596 }; 1597 1598 compute-cb@7 { 1599 compatible = "qcom,fastrpc-compute-cb"; 1600 reg = <7>; 1601 iommus = <&apps_smmu 0x1407 0x20>; 1602 }; 1603 1604 compute-cb@8 { 1605 compatible = "qcom,fastrpc-compute-cb"; 1606 reg = <8>; 1607 iommus = <&apps_smmu 0x1408 0x20>; 1608 }; 1609 1610 /* note: secure cb9 in downstream */ 1611 }; 1612 }; 1613 }; 1614 1615 sdhc_2: mmc@8804000 { 1616 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1617 reg = <0 0x08804000 0 0x1000>; 1618 1619 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1620 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1621 interrupt-names = "hc_irq", "pwr_irq"; 1622 iommus = <&apps_smmu 0x560 0x0>; 1623 1624 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1625 <&gcc GCC_SDCC2_APPS_CLK>, 1626 <&rpmhcc RPMH_CXO_CLK>; 1627 clock-names = "iface", "core", "xo"; 1628 resets = <&gcc GCC_SDCC2_BCR>; 1629 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1630 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1631 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1632 1633 pinctrl-0 = <&sdc2_on_state>; 1634 pinctrl-1 = <&sdc2_off_state>; 1635 pinctrl-names = "default", "sleep"; 1636 1637 qcom,dll-config = <0x0007642c>; 1638 qcom,ddr-config = <0x80040868>; 1639 power-domains = <&rpmhpd SM6350_CX>; 1640 operating-points-v2 = <&sdhc2_opp_table>; 1641 bus-width = <4>; 1642 1643 status = "disabled"; 1644 1645 sdhc2_opp_table: opp-table { 1646 compatible = "operating-points-v2"; 1647 1648 opp-100000000 { 1649 opp-hz = /bits/ 64 <100000000>; 1650 required-opps = <&rpmhpd_opp_svs_l1>; 1651 opp-peak-kBps = <790000 131000>; 1652 opp-avg-kBps = <50000 50000>; 1653 }; 1654 1655 opp-202000000 { 1656 opp-hz = /bits/ 64 <202000000>; 1657 required-opps = <&rpmhpd_opp_nom>; 1658 opp-peak-kBps = <3190000 294000>; 1659 opp-avg-kBps = <261438 300000>; 1660 }; 1661 }; 1662 }; 1663 1664 usb_1_hsphy: phy@88e3000 { 1665 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1666 reg = <0 0x088e3000 0 0x400>; 1667 status = "disabled"; 1668 #phy-cells = <0>; 1669 1670 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1671 clock-names = "cfg_ahb", "ref"; 1672 1673 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1674 }; 1675 1676 usb_1_qmpphy: phy@88e8000 { 1677 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1678 reg = <0 0x088e8000 0 0x3000>; 1679 1680 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1681 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1682 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1683 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1684 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1685 1686 power-domains = <&gcc USB30_PRIM_GDSC>; 1687 1688 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1689 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1690 reset-names = "phy", "common"; 1691 1692 #clock-cells = <1>; 1693 #phy-cells = <1>; 1694 1695 status = "disabled"; 1696 }; 1697 1698 dc_noc: interconnect@9160000 { 1699 compatible = "qcom,sm6350-dc-noc"; 1700 reg = <0 0x09160000 0 0x3200>; 1701 #interconnect-cells = <2>; 1702 qcom,bcm-voters = <&apps_bcm_voter>; 1703 }; 1704 1705 system-cache-controller@9200000 { 1706 compatible = "qcom,sm6350-llcc"; 1707 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1708 reg-names = "llcc0_base", "llcc_broadcast_base"; 1709 }; 1710 1711 gem_noc: interconnect@9680000 { 1712 compatible = "qcom,sm6350-gem-noc"; 1713 reg = <0 0x09680000 0 0x3e200>; 1714 #interconnect-cells = <2>; 1715 qcom,bcm-voters = <&apps_bcm_voter>; 1716 }; 1717 1718 npu_noc: interconnect@9990000 { 1719 compatible = "qcom,sm6350-npu-noc"; 1720 reg = <0 0x09990000 0 0x1600>; 1721 #interconnect-cells = <2>; 1722 qcom,bcm-voters = <&apps_bcm_voter>; 1723 }; 1724 1725 usb_1: usb@a6f8800 { 1726 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1727 reg = <0 0x0a6f8800 0 0x400>; 1728 status = "disabled"; 1729 #address-cells = <2>; 1730 #size-cells = <2>; 1731 ranges; 1732 1733 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1734 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1735 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1736 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1737 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1738 clock-names = "cfg_noc", 1739 "core", 1740 "iface", 1741 "sleep", 1742 "mock_utmi"; 1743 1744 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1745 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1746 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1747 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1748 1749 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1750 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1751 1752 power-domains = <&gcc USB30_PRIM_GDSC>; 1753 1754 resets = <&gcc GCC_USB30_PRIM_BCR>; 1755 1756 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1757 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1758 interconnect-names = "usb-ddr", "apps-usb"; 1759 1760 usb_1_dwc3: usb@a600000 { 1761 compatible = "snps,dwc3"; 1762 reg = <0 0x0a600000 0 0xcd00>; 1763 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1764 iommus = <&apps_smmu 0x540 0x0>; 1765 snps,dis_u2_susphy_quirk; 1766 snps,dis_enblslpm_quirk; 1767 snps,has-lpm-erratum; 1768 snps,hird-threshold = /bits/ 8 <0x10>; 1769 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1770 phy-names = "usb2-phy", "usb3-phy"; 1771 }; 1772 }; 1773 1774 cci0: cci@ac4a000 { 1775 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1776 reg = <0 0x0ac4a000 0 0x1000>; 1777 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1778 power-domains = <&camcc TITAN_TOP_GDSC>; 1779 1780 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1781 <&camcc CAMCC_SOC_AHB_CLK>, 1782 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1783 <&camcc CAMCC_CPAS_AHB_CLK>, 1784 <&camcc CAMCC_CCI_0_CLK>, 1785 <&camcc CAMCC_CCI_0_CLK_SRC>; 1786 clock-names = "camnoc_axi", 1787 "soc_ahb", 1788 "slow_ahb_src", 1789 "cpas_ahb", 1790 "cci", 1791 "cci_src"; 1792 1793 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1794 <&camcc CAMCC_CCI_0_CLK>; 1795 assigned-clock-rates = <80000000>, <37500000>; 1796 1797 pinctrl-0 = <&cci0_default &cci1_default>; 1798 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1799 pinctrl-names = "default", "sleep"; 1800 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 1804 status = "disabled"; 1805 1806 cci0_i2c0: i2c-bus@0 { 1807 reg = <0>; 1808 clock-frequency = <1000000>; 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 }; 1812 1813 cci0_i2c1: i2c-bus@1 { 1814 reg = <1>; 1815 clock-frequency = <1000000>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 }; 1819 }; 1820 1821 cci1: cci@ac4b000 { 1822 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1823 reg = <0 0x0ac4b000 0 0x1000>; 1824 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1825 power-domains = <&camcc TITAN_TOP_GDSC>; 1826 1827 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1828 <&camcc CAMCC_SOC_AHB_CLK>, 1829 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1830 <&camcc CAMCC_CPAS_AHB_CLK>, 1831 <&camcc CAMCC_CCI_1_CLK>, 1832 <&camcc CAMCC_CCI_1_CLK_SRC>; 1833 clock-names = "camnoc_axi", 1834 "soc_ahb", 1835 "slow_ahb_src", 1836 "cpas_ahb", 1837 "cci", 1838 "cci_src"; 1839 1840 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1841 <&camcc CAMCC_CCI_1_CLK>; 1842 assigned-clock-rates = <80000000>, <37500000>; 1843 1844 pinctrl-0 = <&cci2_default>; 1845 pinctrl-1 = <&cci2_sleep>; 1846 pinctrl-names = "default", "sleep"; 1847 1848 #address-cells = <1>; 1849 #size-cells = <0>; 1850 1851 status = "disabled"; 1852 1853 cci1_i2c0: i2c-bus@0 { 1854 reg = <0>; 1855 clock-frequency = <1000000>; 1856 #address-cells = <1>; 1857 #size-cells = <0>; 1858 }; 1859 1860 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1861 }; 1862 1863 camcc: clock-controller@ad00000 { 1864 compatible = "qcom,sm6350-camcc"; 1865 reg = <0 0x0ad00000 0 0x16000>; 1866 clocks = <&rpmhcc RPMH_CXO_CLK>; 1867 #clock-cells = <1>; 1868 #reset-cells = <1>; 1869 #power-domain-cells = <1>; 1870 }; 1871 1872 pdc: interrupt-controller@b220000 { 1873 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1874 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1875 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1876 <125 63 1>, <126 655 12>, <138 139 15>; 1877 #interrupt-cells = <2>; 1878 interrupt-parent = <&intc>; 1879 interrupt-controller; 1880 }; 1881 1882 tsens0: thermal-sensor@c263000 { 1883 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1884 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1885 <0 0x0c222000 0 0x8>; /* SROT */ 1886 #qcom,sensors = <16>; 1887 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1888 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1889 interrupt-names = "uplow", "critical"; 1890 #thermal-sensor-cells = <1>; 1891 }; 1892 1893 tsens1: thermal-sensor@c265000 { 1894 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1895 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1896 <0 0x0c223000 0 0x8>; /* SROT */ 1897 #qcom,sensors = <16>; 1898 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1899 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1900 interrupt-names = "uplow", "critical"; 1901 #thermal-sensor-cells = <1>; 1902 }; 1903 1904 aoss_qmp: power-management@c300000 { 1905 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1906 reg = <0 0x0c300000 0 0x1000>; 1907 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1908 IRQ_TYPE_EDGE_RISING>; 1909 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1910 1911 #clock-cells = <0>; 1912 }; 1913 1914 spmi_bus: spmi@c440000 { 1915 compatible = "qcom,spmi-pmic-arb"; 1916 reg = <0 0x0c440000 0 0x1100>, 1917 <0 0x0c600000 0 0x2000000>, 1918 <0 0x0e600000 0 0x100000>, 1919 <0 0x0e700000 0 0xa0000>, 1920 <0 0x0c40a000 0 0x26000>; 1921 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1922 interrupt-names = "periph_irq"; 1923 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1924 qcom,ee = <0>; 1925 qcom,channel = <0>; 1926 #address-cells = <2>; 1927 #size-cells = <0>; 1928 interrupt-controller; 1929 #interrupt-cells = <4>; 1930 }; 1931 1932 tlmm: pinctrl@f100000 { 1933 compatible = "qcom,sm6350-tlmm"; 1934 reg = <0 0x0f100000 0 0x300000>; 1935 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1944 gpio-controller; 1945 #gpio-cells = <2>; 1946 interrupt-controller; 1947 #interrupt-cells = <2>; 1948 gpio-ranges = <&tlmm 0 0 157>; 1949 1950 cci0_default: cci0-default-state { 1951 pins = "gpio39", "gpio40"; 1952 function = "cci_i2c"; 1953 drive-strength = <2>; 1954 bias-pull-up; 1955 }; 1956 1957 cci0_sleep: cci0-sleep-state { 1958 pins = "gpio39", "gpio40"; 1959 function = "cci_i2c"; 1960 drive-strength = <2>; 1961 bias-pull-down; 1962 }; 1963 1964 cci1_default: cci1-default-state { 1965 pins = "gpio41", "gpio42"; 1966 function = "cci_i2c"; 1967 drive-strength = <2>; 1968 bias-pull-up; 1969 }; 1970 1971 cci1_sleep: cci1-sleep-state { 1972 pins = "gpio41", "gpio42"; 1973 function = "cci_i2c"; 1974 drive-strength = <2>; 1975 bias-pull-down; 1976 }; 1977 1978 cci2_default: cci2-default-state { 1979 pins = "gpio43", "gpio44"; 1980 function = "cci_i2c"; 1981 drive-strength = <2>; 1982 bias-pull-up; 1983 }; 1984 1985 cci2_sleep: cci2-sleep-state { 1986 pins = "gpio43", "gpio44"; 1987 function = "cci_i2c"; 1988 drive-strength = <2>; 1989 bias-pull-down; 1990 }; 1991 1992 sdc2_off_state: sdc2-off-state { 1993 clk-pins { 1994 pins = "sdc2_clk"; 1995 drive-strength = <2>; 1996 bias-disable; 1997 }; 1998 1999 cmd-pins { 2000 pins = "sdc2_cmd"; 2001 drive-strength = <2>; 2002 bias-pull-up; 2003 }; 2004 2005 data-pins { 2006 pins = "sdc2_data"; 2007 drive-strength = <2>; 2008 bias-pull-up; 2009 }; 2010 }; 2011 2012 sdc2_on_state: sdc2-on-state { 2013 clk-pins { 2014 pins = "sdc2_clk"; 2015 drive-strength = <16>; 2016 bias-disable; 2017 }; 2018 2019 cmd-pins { 2020 pins = "sdc2_cmd"; 2021 drive-strength = <10>; 2022 bias-pull-up; 2023 }; 2024 2025 data-pins { 2026 pins = "sdc2_data"; 2027 drive-strength = <10>; 2028 bias-pull-up; 2029 }; 2030 }; 2031 2032 qup_uart9_default: qup-uart9-default-state { 2033 pins = "gpio25", "gpio26"; 2034 function = "qup13_f2"; 2035 drive-strength = <2>; 2036 bias-disable; 2037 }; 2038 2039 qup_i2c0_default: qup-i2c0-default-state { 2040 pins = "gpio0", "gpio1"; 2041 function = "qup00"; 2042 drive-strength = <2>; 2043 bias-pull-up; 2044 }; 2045 2046 qup_i2c2_default: qup-i2c2-default-state { 2047 pins = "gpio45", "gpio46"; 2048 function = "qup02"; 2049 drive-strength = <2>; 2050 bias-pull-up; 2051 }; 2052 2053 qup_i2c6_default: qup-i2c6-default-state { 2054 pins = "gpio13", "gpio14"; 2055 function = "qup10"; 2056 drive-strength = <2>; 2057 bias-pull-up; 2058 }; 2059 2060 qup_i2c7_default: qup-i2c7-default-state { 2061 pins = "gpio27", "gpio28"; 2062 function = "qup11"; 2063 drive-strength = <2>; 2064 bias-pull-up; 2065 }; 2066 2067 qup_i2c8_default: qup-i2c8-default-state { 2068 pins = "gpio19", "gpio20"; 2069 function = "qup12"; 2070 drive-strength = <2>; 2071 bias-pull-up; 2072 }; 2073 2074 qup_i2c10_default: qup-i2c10-default-state { 2075 pins = "gpio4", "gpio5"; 2076 function = "qup14"; 2077 drive-strength = <2>; 2078 bias-pull-up; 2079 }; 2080 2081 qup_uart1_cts: qup-uart1-cts-default-state { 2082 pins = "gpio61"; 2083 function = "qup01"; 2084 drive-strength = <2>; 2085 bias-disable; 2086 }; 2087 2088 qup_uart1_rts: qup-uart1-rts-default-state { 2089 pins = "gpio62"; 2090 function = "qup01"; 2091 drive-strength = <2>; 2092 bias-pull-down; 2093 }; 2094 2095 qup_uart1_rx: qup-uart1-rx-default-state { 2096 pins = "gpio64"; 2097 function = "qup01"; 2098 drive-strength = <2>; 2099 bias-disable; 2100 }; 2101 2102 qup_uart1_tx: qup-uart1-tx-default-state { 2103 pins = "gpio63"; 2104 function = "qup01"; 2105 drive-strength = <2>; 2106 bias-pull-up; 2107 }; 2108 }; 2109 2110 apps_smmu: iommu@15000000 { 2111 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2112 reg = <0 0x15000000 0 0x100000>; 2113 #iommu-cells = <2>; 2114 #global-interrupts = <1>; 2115 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2196 }; 2197 2198 intc: interrupt-controller@17a00000 { 2199 compatible = "arm,gic-v3"; 2200 #interrupt-cells = <3>; 2201 interrupt-controller; 2202 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2203 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2204 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2205 }; 2206 2207 watchdog@17c10000 { 2208 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2209 reg = <0 0x17c10000 0 0x1000>; 2210 clocks = <&sleep_clk>; 2211 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 2212 }; 2213 2214 timer@17c20000 { 2215 compatible = "arm,armv7-timer-mem"; 2216 reg = <0x0 0x17c20000 0x0 0x1000>; 2217 clock-frequency = <19200000>; 2218 #address-cells = <1>; 2219 #size-cells = <1>; 2220 ranges = <0 0 0 0x20000000>; 2221 2222 frame@17c21000 { 2223 frame-number = <0>; 2224 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2226 reg = <0x17c21000 0x1000>, 2227 <0x17c22000 0x1000>; 2228 }; 2229 2230 frame@17c23000 { 2231 frame-number = <1>; 2232 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2233 reg = <0x17c23000 0x1000>; 2234 status = "disabled"; 2235 }; 2236 2237 frame@17c25000 { 2238 frame-number = <2>; 2239 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2240 reg = <0x17c25000 0x1000>; 2241 status = "disabled"; 2242 }; 2243 2244 frame@17c27000 { 2245 frame-number = <3>; 2246 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2247 reg = <0x17c27000 0x1000>; 2248 status = "disabled"; 2249 }; 2250 2251 frame@17c29000 { 2252 frame-number = <4>; 2253 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2254 reg = <0x17c29000 0x1000>; 2255 status = "disabled"; 2256 }; 2257 2258 frame@17c2b000 { 2259 frame-number = <5>; 2260 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2261 reg = <0x17c2b000 0x1000>; 2262 status = "disabled"; 2263 }; 2264 2265 frame@17c2d000 { 2266 frame-number = <6>; 2267 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2268 reg = <0x17c2d000 0x1000>; 2269 status = "disabled"; 2270 }; 2271 }; 2272 2273 apps_rsc: rsc@18200000 { 2274 compatible = "qcom,rpmh-rsc"; 2275 label = "apps_rsc"; 2276 reg = <0x0 0x18200000 0x0 0x10000>, 2277 <0x0 0x18210000 0x0 0x10000>, 2278 <0x0 0x18220000 0x0 0x10000>; 2279 reg-names = "drv-0", "drv-1", "drv-2"; 2280 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2281 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2282 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2283 qcom,tcs-offset = <0xd00>; 2284 qcom,drv-id = <2>; 2285 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2286 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2287 power-domains = <&CLUSTER_PD>; 2288 2289 rpmhcc: clock-controller { 2290 compatible = "qcom,sm6350-rpmh-clk"; 2291 #clock-cells = <1>; 2292 clock-names = "xo"; 2293 clocks = <&xo_board>; 2294 }; 2295 2296 rpmhpd: power-controller { 2297 compatible = "qcom,sm6350-rpmhpd"; 2298 #power-domain-cells = <1>; 2299 operating-points-v2 = <&rpmhpd_opp_table>; 2300 2301 rpmhpd_opp_table: opp-table { 2302 compatible = "operating-points-v2"; 2303 2304 rpmhpd_opp_ret: opp1 { 2305 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2306 }; 2307 2308 rpmhpd_opp_min_svs: opp2 { 2309 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2310 }; 2311 2312 rpmhpd_opp_low_svs: opp3 { 2313 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2314 }; 2315 2316 rpmhpd_opp_svs: opp4 { 2317 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2318 }; 2319 2320 rpmhpd_opp_svs_l1: opp5 { 2321 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2322 }; 2323 2324 rpmhpd_opp_nom: opp6 { 2325 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2326 }; 2327 2328 rpmhpd_opp_nom_l1: opp7 { 2329 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2330 }; 2331 2332 rpmhpd_opp_nom_l2: opp8 { 2333 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2334 }; 2335 2336 rpmhpd_opp_turbo: opp9 { 2337 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2338 }; 2339 2340 rpmhpd_opp_turbo_l1: opp10 { 2341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2342 }; 2343 }; 2344 }; 2345 2346 apps_bcm_voter: bcm-voter { 2347 compatible = "qcom,bcm-voter"; 2348 }; 2349 }; 2350 2351 osm_l3: interconnect@18321000 { 2352 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2353 reg = <0x0 0x18321000 0x0 0x1000>; 2354 2355 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2356 clock-names = "xo", "alternate"; 2357 2358 #interconnect-cells = <1>; 2359 }; 2360 2361 cpufreq_hw: cpufreq@18323000 { 2362 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2363 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2364 reg-names = "freq-domain0", "freq-domain1"; 2365 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2366 clock-names = "xo", "alternate"; 2367 2368 #freq-domain-cells = <1>; 2369 #clock-cells = <1>; 2370 }; 2371 2372 wifi: wifi@18800000 { 2373 compatible = "qcom,wcn3990-wifi"; 2374 reg = <0 0x18800000 0 0x800000>; 2375 reg-names = "membase"; 2376 memory-region = <&wlan_fw_mem>; 2377 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2389 iommus = <&apps_smmu 0x20 0x1>; 2390 qcom,msa-fixed-perm; 2391 status = "disabled"; 2392 }; 2393 }; 2394 2395 timer { 2396 compatible = "arm,armv8-timer"; 2397 clock-frequency = <19200000>; 2398 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2399 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2400 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2401 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2402 }; 2403}; 2404