1*79e7739fSRob Clark// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*79e7739fSRob Clark/* 3*79e7739fSRob Clark * Google Cheza board device tree source 4*79e7739fSRob Clark * 5*79e7739fSRob Clark * Copyright 2018 Google LLC. 6*79e7739fSRob Clark */ 7*79e7739fSRob Clark 8*79e7739fSRob Clark/dts-v1/; 9*79e7739fSRob Clark 10*79e7739fSRob Clark#include "sdm845-cheza.dtsi" 11*79e7739fSRob Clark 12*79e7739fSRob Clark/ { 13*79e7739fSRob Clark model = "Google Cheza (rev3+)"; 14*79e7739fSRob Clark compatible = "google,cheza", "qcom,sdm845"; 15*79e7739fSRob Clark}; 16*79e7739fSRob Clark 17*79e7739fSRob Clark/* PINCTRL - board-specific pinctrl */ 18*79e7739fSRob Clark 19*79e7739fSRob Clark&tlmm { 20*79e7739fSRob Clark gpio-line-names = "AP_SPI_FP_MISO", 21*79e7739fSRob Clark "AP_SPI_FP_MOSI", 22*79e7739fSRob Clark "AP_SPI_FP_CLK", 23*79e7739fSRob Clark "AP_SPI_FP_CS_L", 24*79e7739fSRob Clark "UART_AP_TX_DBG_RX", 25*79e7739fSRob Clark "UART_DBG_TX_AP_RX", 26*79e7739fSRob Clark "BRIJ_SUSPEND", 27*79e7739fSRob Clark "FP_RST_L", 28*79e7739fSRob Clark "FCAM_EN", 29*79e7739fSRob Clark "", 30*79e7739fSRob Clark "EDP_BRIJ_IRQ", 31*79e7739fSRob Clark "EC_IN_RW_ODL", 32*79e7739fSRob Clark "", 33*79e7739fSRob Clark "RCAM_MCLK", 34*79e7739fSRob Clark "FCAM_MCLK", 35*79e7739fSRob Clark "", 36*79e7739fSRob Clark "RCAM_EN", 37*79e7739fSRob Clark "CCI0_SDA", 38*79e7739fSRob Clark "CCI0_SCL", 39*79e7739fSRob Clark "CCI1_SDA", 40*79e7739fSRob Clark "CCI1_SCL", 41*79e7739fSRob Clark "FCAM_RST_L", 42*79e7739fSRob Clark "FPMCU_BOOT0", 43*79e7739fSRob Clark "PEN_RST_L", 44*79e7739fSRob Clark "PEN_IRQ_L", 45*79e7739fSRob Clark "FPMCU_SEL_OD", 46*79e7739fSRob Clark "RCAM_VSYNC", 47*79e7739fSRob Clark "ESIM_MISO", 48*79e7739fSRob Clark "ESIM_MOSI", 49*79e7739fSRob Clark "ESIM_CLK", 50*79e7739fSRob Clark "ESIM_CS_L", 51*79e7739fSRob Clark "AP_PEN_1V8_SDA", 52*79e7739fSRob Clark "AP_PEN_1V8_SCL", 53*79e7739fSRob Clark "AP_TS_I2C_SDA", 54*79e7739fSRob Clark "AP_TS_I2C_SCL", 55*79e7739fSRob Clark "RCAM_RST_L", 56*79e7739fSRob Clark "", 57*79e7739fSRob Clark "AP_EDP_BKLTEN", 58*79e7739fSRob Clark "AP_BRD_ID0", 59*79e7739fSRob Clark "BOOT_CONFIG_4", 60*79e7739fSRob Clark "AMP_IRQ_L", 61*79e7739fSRob Clark "EDP_BRIJ_I2C_SDA", 62*79e7739fSRob Clark "EDP_BRIJ_I2C_SCL", 63*79e7739fSRob Clark "EN_PP3300_DX_EDP", 64*79e7739fSRob Clark "SD_CD_ODL", 65*79e7739fSRob Clark "BT_UART_RTS", 66*79e7739fSRob Clark "BT_UART_CTS", 67*79e7739fSRob Clark "BT_UART_RXD", 68*79e7739fSRob Clark "BT_UART_TXD", 69*79e7739fSRob Clark "AMP_I2C_SDA", 70*79e7739fSRob Clark "AMP_I2C_SCL", 71*79e7739fSRob Clark "AP_BRD_ID2", 72*79e7739fSRob Clark "", 73*79e7739fSRob Clark "AP_EC_SPI_CLK", 74*79e7739fSRob Clark "AP_EC_SPI_CS_L", 75*79e7739fSRob Clark "AP_EC_SPI_MISO", 76*79e7739fSRob Clark "AP_EC_SPI_MOSI", 77*79e7739fSRob Clark "FORCED_USB_BOOT", 78*79e7739fSRob Clark "AMP_BCLK", 79*79e7739fSRob Clark "AMP_LRCLK", 80*79e7739fSRob Clark "AMP_DOUT", 81*79e7739fSRob Clark "AMP_DIN", 82*79e7739fSRob Clark "AP_BRD_ID1", 83*79e7739fSRob Clark "PEN_PDCT_L", 84*79e7739fSRob Clark "HP_MCLK", 85*79e7739fSRob Clark "HP_BCLK", 86*79e7739fSRob Clark "HP_LRCLK", 87*79e7739fSRob Clark "HP_DOUT", 88*79e7739fSRob Clark "HP_DIN", 89*79e7739fSRob Clark "", 90*79e7739fSRob Clark "", 91*79e7739fSRob Clark "", 92*79e7739fSRob Clark "", 93*79e7739fSRob Clark "BT_SLIMBUS_DATA", 94*79e7739fSRob Clark "BT_SLIMBUS_CLK", 95*79e7739fSRob Clark "AMP_RESET_L", 96*79e7739fSRob Clark "", 97*79e7739fSRob Clark "FCAM_VSYNC", 98*79e7739fSRob Clark "", 99*79e7739fSRob Clark "AP_SKU_ID0", 100*79e7739fSRob Clark "EC_WOV_BCLK", 101*79e7739fSRob Clark "EC_WOV_LRCLK", 102*79e7739fSRob Clark "EC_WOV_DOUT", 103*79e7739fSRob Clark "", 104*79e7739fSRob Clark "", 105*79e7739fSRob Clark "AP_H1_SPI_MISO", 106*79e7739fSRob Clark "AP_H1_SPI_MOSI", 107*79e7739fSRob Clark "AP_H1_SPI_CLK", 108*79e7739fSRob Clark "AP_H1_SPI_CS_L", 109*79e7739fSRob Clark "", 110*79e7739fSRob Clark "AP_SPI_CS0_L", 111*79e7739fSRob Clark "AP_SPI_MOSI", 112*79e7739fSRob Clark "AP_SPI_MISO", 113*79e7739fSRob Clark "", 114*79e7739fSRob Clark "", 115*79e7739fSRob Clark "AP_SPI_CLK", 116*79e7739fSRob Clark "", 117*79e7739fSRob Clark "RFFE6_CLK", 118*79e7739fSRob Clark "RFFE6_DATA", 119*79e7739fSRob Clark "BOOT_CONFIG_1", 120*79e7739fSRob Clark "BOOT_CONFIG_2", 121*79e7739fSRob Clark "BOOT_CONFIG_0", 122*79e7739fSRob Clark "EDP_BRIJ_EN", 123*79e7739fSRob Clark "", 124*79e7739fSRob Clark "USB_HS_TX_EN", 125*79e7739fSRob Clark "UIM2_DATA", 126*79e7739fSRob Clark "UIM2_CLK", 127*79e7739fSRob Clark "UIM2_RST", 128*79e7739fSRob Clark "UIM2_PRESENT", 129*79e7739fSRob Clark "UIM1_DATA", 130*79e7739fSRob Clark "UIM1_CLK", 131*79e7739fSRob Clark "UIM1_RST", 132*79e7739fSRob Clark "", 133*79e7739fSRob Clark "AP_SKU_ID1", 134*79e7739fSRob Clark "SDM_GRFC_8", 135*79e7739fSRob Clark "SDM_GRFC_9", 136*79e7739fSRob Clark "AP_RST_REQ", 137*79e7739fSRob Clark "HP_IRQ", 138*79e7739fSRob Clark "TS_RESET_L", 139*79e7739fSRob Clark "PEN_EJECT_ODL", 140*79e7739fSRob Clark "HUB_RST_L", 141*79e7739fSRob Clark "FP_TO_AP_IRQ", 142*79e7739fSRob Clark "AP_EC_INT_L", 143*79e7739fSRob Clark "", 144*79e7739fSRob Clark "", 145*79e7739fSRob Clark "TS_INT_L", 146*79e7739fSRob Clark "AP_SUSPEND_L", 147*79e7739fSRob Clark "SDM_GRFC_3", 148*79e7739fSRob Clark /* 149*79e7739fSRob Clark * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics 150*79e7739fSRob Clark * call it BIOS_FLASH_WP_R_L. 151*79e7739fSRob Clark */ 152*79e7739fSRob Clark "AP_FLASH_WP_L", 153*79e7739fSRob Clark "H1_AP_INT_ODL", 154*79e7739fSRob Clark "QLINK_REQ", 155*79e7739fSRob Clark "QLINK_EN", 156*79e7739fSRob Clark "SDM_GRFC_2", 157*79e7739fSRob Clark "BOOT_CONFIG_3", 158*79e7739fSRob Clark "WMSS_RESET_L", 159*79e7739fSRob Clark "SDM_GRFC_0", 160*79e7739fSRob Clark "SDM_GRFC_1", 161*79e7739fSRob Clark "RFFE3_DATA", 162*79e7739fSRob Clark "RFFE3_CLK", 163*79e7739fSRob Clark "RFFE4_DATA", 164*79e7739fSRob Clark "RFFE4_CLK", 165*79e7739fSRob Clark "RFFE5_DATA", 166*79e7739fSRob Clark "RFFE5_CLK", 167*79e7739fSRob Clark "GNSS_EN", 168*79e7739fSRob Clark "WCI2_LTE_COEX_RXD", 169*79e7739fSRob Clark "WCI2_LTE_COEX_TXD", 170*79e7739fSRob Clark "AP_RAM_ID0", 171*79e7739fSRob Clark "AP_RAM_ID1", 172*79e7739fSRob Clark "RFFE1_DATA", 173*79e7739fSRob Clark "RFFE1_CLK"; 174*79e7739fSRob Clark}; 175