1*79e7739fSRob Clark// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*79e7739fSRob Clark/* 3*79e7739fSRob Clark * Google Cheza board device tree source 4*79e7739fSRob Clark * 5*79e7739fSRob Clark * Copyright 2018 Google LLC. 6*79e7739fSRob Clark */ 7*79e7739fSRob Clark 8*79e7739fSRob Clark/dts-v1/; 9*79e7739fSRob Clark 10*79e7739fSRob Clark#include "sdm845-cheza.dtsi" 11*79e7739fSRob Clark 12*79e7739fSRob Clark/ { 13*79e7739fSRob Clark model = "Google Cheza (rev2)"; 14*79e7739fSRob Clark compatible = "google,cheza-rev2", "qcom,sdm845"; 15*79e7739fSRob Clark 16*79e7739fSRob Clark /* 17*79e7739fSRob Clark * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children 18*79e7739fSRob Clark */ 19*79e7739fSRob Clark 20*79e7739fSRob Clark /* 21*79e7739fSRob Clark * NOTE: Technically pp3500_a is not the exact same signal as 22*79e7739fSRob Clark * pp3500_a_vbob (there's a load switch between them and the EC can 23*79e7739fSRob Clark * control pp3500_a via "en_pp3300_a"), but from the AP's point of 24*79e7739fSRob Clark * view they are the same. 25*79e7739fSRob Clark */ 26*79e7739fSRob Clark pp3500_a: 27*79e7739fSRob Clark pp3500_a_vbob: pp3500-a-vbob-regulator { 28*79e7739fSRob Clark compatible = "regulator-fixed"; 29*79e7739fSRob Clark regulator-name = "vreg_bob"; 30*79e7739fSRob Clark 31*79e7739fSRob Clark /* 32*79e7739fSRob Clark * Comes on automatically when pp5000_ldo comes on, which 33*79e7739fSRob Clark * comes on automatically when ppvar_sys comes on 34*79e7739fSRob Clark */ 35*79e7739fSRob Clark regulator-always-on; 36*79e7739fSRob Clark regulator-boot-on; 37*79e7739fSRob Clark regulator-min-microvolt = <3500000>; 38*79e7739fSRob Clark regulator-max-microvolt = <3500000>; 39*79e7739fSRob Clark 40*79e7739fSRob Clark vin-supply = <&ppvar_sys>; 41*79e7739fSRob Clark }; 42*79e7739fSRob Clark 43*79e7739fSRob Clark pp3300_dx_edp: pp3300-dx-edp-regulator { 44*79e7739fSRob Clark /* Yes, it's really 3.5 despite the name of the signal */ 45*79e7739fSRob Clark regulator-min-microvolt = <3500000>; 46*79e7739fSRob Clark regulator-max-microvolt = <3500000>; 47*79e7739fSRob Clark 48*79e7739fSRob Clark vin-supply = <&pp3500_a>; 49*79e7739fSRob Clark }; 50*79e7739fSRob Clark}; 51*79e7739fSRob Clark 52*79e7739fSRob Clark/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */ 53*79e7739fSRob Clark 54*79e7739fSRob Clark/* 55*79e7739fSRob Clark * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware 56*79e7739fSRob Clark * that limits them to 3.0, and trying to run at 3.3V with that old firmware 57*79e7739fSRob Clark * prevents the system from booting. 58*79e7739fSRob Clark */ 59*79e7739fSRob Clark&src_pp3000_l19a { 60*79e7739fSRob Clark regulator-min-microvolt = <3008000>; 61*79e7739fSRob Clark regulator-max-microvolt = <3008000>; 62*79e7739fSRob Clark}; 63*79e7739fSRob Clark 64*79e7739fSRob Clark&src_pp3300_l22a { 65*79e7739fSRob Clark /delete-property/regulator-boot-on; 66*79e7739fSRob Clark /delete-property/regulator-always-on; 67*79e7739fSRob Clark}; 68*79e7739fSRob Clark 69*79e7739fSRob Clark&src_pp3300_l28a { 70*79e7739fSRob Clark regulator-min-microvolt = <3008000>; 71*79e7739fSRob Clark regulator-max-microvolt = <3008000>; 72*79e7739fSRob Clark}; 73*79e7739fSRob Clark 74*79e7739fSRob Clark&src_vreg_bob { 75*79e7739fSRob Clark regulator-min-microvolt = <3500000>; 76*79e7739fSRob Clark regulator-max-microvolt = <3500000>; 77*79e7739fSRob Clark vin-supply = <&pp3500_a_vbob>; 78*79e7739fSRob Clark}; 79*79e7739fSRob Clark 80*79e7739fSRob Clark/* 81*79e7739fSRob Clark * NON-REGULATOR OVERRIDES 82*79e7739fSRob Clark * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label 83*79e7739fSRob Clark */ 84*79e7739fSRob Clark 85*79e7739fSRob Clark/* PINCTRL - board-specific pinctrl */ 86*79e7739fSRob Clark 87*79e7739fSRob Clark&tlmm { 88*79e7739fSRob Clark gpio-line-names = "AP_SPI_FP_MISO", 89*79e7739fSRob Clark "AP_SPI_FP_MOSI", 90*79e7739fSRob Clark "AP_SPI_FP_CLK", 91*79e7739fSRob Clark "AP_SPI_FP_CS_L", 92*79e7739fSRob Clark "UART_AP_TX_DBG_RX", 93*79e7739fSRob Clark "UART_DBG_TX_AP_RX", 94*79e7739fSRob Clark "BRIJ_SUSPEND", 95*79e7739fSRob Clark "FP_RST_L", 96*79e7739fSRob Clark "FCAM_EN", 97*79e7739fSRob Clark "", 98*79e7739fSRob Clark "EDP_BRIJ_IRQ", 99*79e7739fSRob Clark "EC_IN_RW_ODL", 100*79e7739fSRob Clark "", 101*79e7739fSRob Clark "RCAM_MCLK", 102*79e7739fSRob Clark "FCAM_MCLK", 103*79e7739fSRob Clark "", 104*79e7739fSRob Clark "RCAM_EN", 105*79e7739fSRob Clark "CCI0_SDA", 106*79e7739fSRob Clark "CCI0_SCL", 107*79e7739fSRob Clark "CCI1_SDA", 108*79e7739fSRob Clark "CCI1_SCL", 109*79e7739fSRob Clark "FCAM_RST_L", 110*79e7739fSRob Clark "FPMCU_BOOT0", 111*79e7739fSRob Clark "PEN_RST_L", 112*79e7739fSRob Clark "PEN_IRQ_L", 113*79e7739fSRob Clark "FPMCU_SEL_OD", 114*79e7739fSRob Clark "RCAM_VSYNC", 115*79e7739fSRob Clark "ESIM_MISO", 116*79e7739fSRob Clark "ESIM_MOSI", 117*79e7739fSRob Clark "ESIM_CLK", 118*79e7739fSRob Clark "ESIM_CS_L", 119*79e7739fSRob Clark "AP_PEN_1V8_SDA", 120*79e7739fSRob Clark "AP_PEN_1V8_SCL", 121*79e7739fSRob Clark "AP_TS_I2C_SDA", 122*79e7739fSRob Clark "AP_TS_I2C_SCL", 123*79e7739fSRob Clark "RCAM_RST_L", 124*79e7739fSRob Clark "", 125*79e7739fSRob Clark "AP_EDP_BKLTEN", 126*79e7739fSRob Clark "AP_BRD_ID1", 127*79e7739fSRob Clark "BOOT_CONFIG_4", 128*79e7739fSRob Clark "AMP_IRQ_L", 129*79e7739fSRob Clark "EDP_BRIJ_I2C_SDA", 130*79e7739fSRob Clark "EDP_BRIJ_I2C_SCL", 131*79e7739fSRob Clark "EN_PP3300_DX_EDP", 132*79e7739fSRob Clark "SD_CD_ODL", 133*79e7739fSRob Clark "BT_UART_RTS", 134*79e7739fSRob Clark "BT_UART_CTS", 135*79e7739fSRob Clark "BT_UART_RXD", 136*79e7739fSRob Clark "BT_UART_TXD", 137*79e7739fSRob Clark "AMP_I2C_SDA", 138*79e7739fSRob Clark "AMP_I2C_SCL", 139*79e7739fSRob Clark "AP_BRD_ID3", 140*79e7739fSRob Clark "", 141*79e7739fSRob Clark "AP_EC_SPI_CLK", 142*79e7739fSRob Clark "AP_EC_SPI_CS_L", 143*79e7739fSRob Clark "AP_EC_SPI_MISO", 144*79e7739fSRob Clark "AP_EC_SPI_MOSI", 145*79e7739fSRob Clark "FORCED_USB_BOOT", 146*79e7739fSRob Clark "AMP_BCLK", 147*79e7739fSRob Clark "AMP_LRCLK", 148*79e7739fSRob Clark "AMP_DOUT", 149*79e7739fSRob Clark "AMP_DIN", 150*79e7739fSRob Clark "AP_BRD_ID2", 151*79e7739fSRob Clark "PEN_PDCT_L", 152*79e7739fSRob Clark "HP_MCLK", 153*79e7739fSRob Clark "HP_BCLK", 154*79e7739fSRob Clark "HP_LRCLK", 155*79e7739fSRob Clark "HP_DOUT", 156*79e7739fSRob Clark "HP_DIN", 157*79e7739fSRob Clark "", 158*79e7739fSRob Clark "", 159*79e7739fSRob Clark "", 160*79e7739fSRob Clark "", 161*79e7739fSRob Clark "BT_SLIMBUS_DATA", 162*79e7739fSRob Clark "BT_SLIMBUS_CLK", 163*79e7739fSRob Clark "AMP_RESET_L", 164*79e7739fSRob Clark "", 165*79e7739fSRob Clark "FCAM_VSYNC", 166*79e7739fSRob Clark "", 167*79e7739fSRob Clark "AP_SKU_ID1", 168*79e7739fSRob Clark "EC_WOV_BCLK", 169*79e7739fSRob Clark "EC_WOV_LRCLK", 170*79e7739fSRob Clark "EC_WOV_DOUT", 171*79e7739fSRob Clark "", 172*79e7739fSRob Clark "", 173*79e7739fSRob Clark "AP_H1_SPI_MISO", 174*79e7739fSRob Clark "AP_H1_SPI_MOSI", 175*79e7739fSRob Clark "AP_H1_SPI_CLK", 176*79e7739fSRob Clark "AP_H1_SPI_CS_L", 177*79e7739fSRob Clark "", 178*79e7739fSRob Clark "AP_SPI_CS0_L", 179*79e7739fSRob Clark "AP_SPI_MOSI", 180*79e7739fSRob Clark "AP_SPI_MISO", 181*79e7739fSRob Clark "", 182*79e7739fSRob Clark "", 183*79e7739fSRob Clark "AP_SPI_CLK", 184*79e7739fSRob Clark "", 185*79e7739fSRob Clark "RFFE6_CLK", 186*79e7739fSRob Clark "RFFE6_DATA", 187*79e7739fSRob Clark "BOOT_CONFIG_1", 188*79e7739fSRob Clark "BOOT_CONFIG_2", 189*79e7739fSRob Clark "BOOT_CONFIG_0", 190*79e7739fSRob Clark "EDP_BRIJ_EN", 191*79e7739fSRob Clark "", 192*79e7739fSRob Clark "USB_HS_TX_EN", 193*79e7739fSRob Clark "UIM2_DATA", 194*79e7739fSRob Clark "UIM2_CLK", 195*79e7739fSRob Clark "UIM2_RST", 196*79e7739fSRob Clark "UIM2_PRESENT", 197*79e7739fSRob Clark "UIM1_DATA", 198*79e7739fSRob Clark "UIM1_CLK", 199*79e7739fSRob Clark "UIM1_RST", 200*79e7739fSRob Clark "", 201*79e7739fSRob Clark "AP_SKU_ID2", 202*79e7739fSRob Clark "SDM_GRFC_8", 203*79e7739fSRob Clark "SDM_GRFC_9", 204*79e7739fSRob Clark "AP_RST_REQ", 205*79e7739fSRob Clark "HP_IRQ", 206*79e7739fSRob Clark "TS_RESET_L", 207*79e7739fSRob Clark "PEN_EJECT_ODL", 208*79e7739fSRob Clark "HUB_RST_L", 209*79e7739fSRob Clark "FP_TO_AP_IRQ", 210*79e7739fSRob Clark "AP_EC_INT_L", 211*79e7739fSRob Clark "", 212*79e7739fSRob Clark "", 213*79e7739fSRob Clark "TS_INT_L", 214*79e7739fSRob Clark "AP_SUSPEND_L", 215*79e7739fSRob Clark "SDM_GRFC_3", 216*79e7739fSRob Clark "", 217*79e7739fSRob Clark "H1_AP_INT_ODL", 218*79e7739fSRob Clark "QLINK_REQ", 219*79e7739fSRob Clark "QLINK_EN", 220*79e7739fSRob Clark "SDM_GRFC_2", 221*79e7739fSRob Clark "BOOT_CONFIG_3", 222*79e7739fSRob Clark "WMSS_RESET_L", 223*79e7739fSRob Clark "SDM_GRFC_0", 224*79e7739fSRob Clark "SDM_GRFC_1", 225*79e7739fSRob Clark "RFFE3_DATA", 226*79e7739fSRob Clark "RFFE3_CLK", 227*79e7739fSRob Clark "RFFE4_DATA", 228*79e7739fSRob Clark "RFFE4_CLK", 229*79e7739fSRob Clark "RFFE5_DATA", 230*79e7739fSRob Clark "RFFE5_CLK", 231*79e7739fSRob Clark "GNSS_EN", 232*79e7739fSRob Clark "WCI2_LTE_COEX_RXD", 233*79e7739fSRob Clark "WCI2_LTE_COEX_TXD", 234*79e7739fSRob Clark "AP_RAM_ID1", 235*79e7739fSRob Clark "AP_RAM_ID2", 236*79e7739fSRob Clark "RFFE1_DATA", 237*79e7739fSRob Clark "RFFE1_CLK"; 238*79e7739fSRob Clark}; 239