xref: /openbmc/linux/arch/arm64/boot/dts/qcom/sdm660.dtsi (revision 05aa0eb325c98f7e06eeb3f251cbab1b27586c8e)

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2018, Craig Tatlor.
 * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
 * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
 */

#include "sdm630.dtsi"

&adreno_gpu {
	compatible = "qcom,adreno-512.0", "qcom,adreno";
	operating-points-v2 = <&gpu_sdm660_opp_table>;

	gpu_sdm660_opp_table: opp-table {
		compatible  = "operating-points-v2";

		/*
		 * 775MHz is only available on the highest speed bin
		 * Though it cannot be used for now due to interconnect
		 * framework not supporting multiple frequencies
		 * at the same opp-level

		opp-750000000 {
			opp-hz = /bits/ 64 <750000000>;
			opp-level = <RPM_SMD_LEVEL_TURBO>;
			opp-peak-kBps = <5412000>;
			opp-supported-hw = <0xCHECKME>;
		};

		* These OPPs are correct, but we are lacking support for the
		* GPU regulator. Hence, disable them for now to prevent the
		* platform from hanging on high graphics loads.

		opp-700000000 {
			opp-hz = /bits/ 64 <700000000>;
			opp-level = <RPM_SMD_LEVEL_TURBO>;
			opp-peak-kBps = <5184000>;
			opp-supported-hw = <0xFF>;
		};

		opp-647000000 {
			opp-hz = /bits/ 64 <647000000>;
			opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
			opp-peak-kBps = <4068000>;
			opp-supported-hw = <0xFF>;
		};

		opp-588000000 {
			opp-hz = /bits/ 64 <588000000>;
			opp-level = <RPM_SMD_LEVEL_NOM>;
			opp-peak-kBps = <3072000>;
			opp-supported-hw = <0xFF>;
		};

		opp-465000000 {
			opp-hz = /bits/ 64 <465000000>;
			opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
			opp-peak-kBps = <2724000>;
			opp-supported-hw = <0xFF>;
		};

		opp-370000000 {
			opp-hz = /bits/ 64 <370000000>;
			opp-level = <RPM_SMD_LEVEL_SVS>;
			opp-peak-kBps = <2188000>;
			opp-supported-hw = <0xFF>;
		};
		*/

		opp-266000000 {
			opp-hz = /bits/ 64 <266000000>;
			opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
			opp-peak-kBps = <1648000>;
			opp-supported-hw = <0xFF>;
		};

		opp-160000000 {
			opp-hz = /bits/ 64 <160000000>;
			opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
			opp-peak-kBps = <1200000>;
			opp-supported-hw = <0xFF>;
		};
	};
};

&CPU0 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <1024>;
	/delete-property/ operating-points-v2;
};

&CPU1 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <1024>;
	/delete-property/ operating-points-v2;
};

&CPU2 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <1024>;
	/delete-property/ operating-points-v2;
};

&CPU3 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <1024>;
	/delete-property/ operating-points-v2;
};

&CPU4 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <640>;
	/delete-property/ operating-points-v2;
};

&CPU5 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <640>;
	/delete-property/ operating-points-v2;
};

&CPU6 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <640>;
	/delete-property/ operating-points-v2;
};

&CPU7 {
	compatible = "qcom,kryo260";
	capacity-dmips-mhz = <640>;
	/delete-property/ operating-points-v2;
};

&gcc {
	compatible = "qcom,gcc-sdm660";
};

&gpucc {
	compatible = "qcom,gpucc-sdm660";
};

&mmcc {
	compatible = "qcom,mmcc-sdm660";
	/*
	 * 660 has one more dsi host/phy, which - when implemented
	 * and tested - should be added to the clocks property.
	 */
};

&tlmm {
	compatible = "qcom,sdm660-pinctrl";
};

&tsens {
	#qcom,sensors = <14>;
};