1dd03aeefSMark Zhang// SPDX-License-Identifier: GPL-2.0 2dd03aeefSMark Zhang 37152879dSMark Zhang#include <dt-bindings/input/input.h> 47152879dSMark Zhang#include <dt-bindings/input/gpio-keys.h> 551e5e018SMark Zhang#include <dt-bindings/mfd/max77620.h> 66ec2c716SMark Zhang#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7dd03aeefSMark Zhang#include "tegra210.dtsi" 8dd03aeefSMark Zhang 9dd03aeefSMark Zhang/ { 10dd03aeefSMark Zhang aliases { 11dd03aeefSMark Zhang serial0 = &uarta; 12dd03aeefSMark Zhang }; 13dd03aeefSMark Zhang 14dd03aeefSMark Zhang chosen { 15dd03aeefSMark Zhang bootargs = "earlycon"; 16dd03aeefSMark Zhang stdout-path = "serial0:115200n8"; 17dd03aeefSMark Zhang }; 18dd03aeefSMark Zhang 19772a6a7bSThierry Reding memory@80000000 { 20dd03aeefSMark Zhang device_type = "memory"; 21dd03aeefSMark Zhang reg = <0x0 0x80000000 0x0 0xc0000000>; 22dd03aeefSMark Zhang }; 23dd03aeefSMark Zhang 246ec2c716SMark Zhang pinmux: pinmux@700008d4 { 256ec2c716SMark Zhang status = "okay"; 266ec2c716SMark Zhang pinctrl-names = "boot"; 276ec2c716SMark Zhang pinctrl-0 = <&state_boot>; 286ec2c716SMark Zhang 296ec2c716SMark Zhang state_boot: pinmux { 306ec2c716SMark Zhang pex_l0_rst_n_pa0 { 316ec2c716SMark Zhang nvidia,pins = "pex_l0_rst_n_pa0"; 326ec2c716SMark Zhang nvidia,function = "rsvd1"; 336ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 346ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 356ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 366ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 376ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 386ec2c716SMark Zhang }; 396ec2c716SMark Zhang pex_l0_clkreq_n_pa1 { 406ec2c716SMark Zhang nvidia,pins = "pex_l0_clkreq_n_pa1"; 416ec2c716SMark Zhang nvidia,function = "pe0"; 426ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 436ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 446ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 456ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 466ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 476ec2c716SMark Zhang }; 486ec2c716SMark Zhang pex_wake_n_pa2 { 496ec2c716SMark Zhang nvidia,pins = "pex_wake_n_pa2"; 506ec2c716SMark Zhang nvidia,function = "pe"; 516ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 526ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 536ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 546ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 556ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 566ec2c716SMark Zhang }; 576ec2c716SMark Zhang pex_l1_rst_n_pa3 { 586ec2c716SMark Zhang nvidia,pins = "pex_l1_rst_n_pa3"; 596ec2c716SMark Zhang nvidia,function = "pe1"; 606ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 616ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 626ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 636ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 646ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 656ec2c716SMark Zhang }; 666ec2c716SMark Zhang pex_l1_clkreq_n_pa4 { 676ec2c716SMark Zhang nvidia,pins = "pex_l1_clkreq_n_pa4"; 686ec2c716SMark Zhang nvidia,function = "pe1"; 696ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 706ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 716ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 726ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 736ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 746ec2c716SMark Zhang }; 756ec2c716SMark Zhang sata_led_active_pa5 { 766ec2c716SMark Zhang nvidia,pins = "sata_led_active_pa5"; 776ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 786ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 796ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 806ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 816ec2c716SMark Zhang }; 826ec2c716SMark Zhang pa6 { 836ec2c716SMark Zhang nvidia,pins = "pa6"; 846ec2c716SMark Zhang nvidia,function = "rsvd1"; 856ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 866ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 876ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 886ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 896ec2c716SMark Zhang }; 906ec2c716SMark Zhang dap1_fs_pb0 { 916ec2c716SMark Zhang nvidia,pins = "dap1_fs_pb0"; 926ec2c716SMark Zhang nvidia,function = "rsvd1"; 936ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 946ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 956ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 966ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 976ec2c716SMark Zhang }; 986ec2c716SMark Zhang dap1_din_pb1 { 996ec2c716SMark Zhang nvidia,pins = "dap1_din_pb1"; 1006ec2c716SMark Zhang nvidia,function = "rsvd1"; 1016ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1026ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1036ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1046ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1056ec2c716SMark Zhang }; 1066ec2c716SMark Zhang dap1_dout_pb2 { 1076ec2c716SMark Zhang nvidia,pins = "dap1_dout_pb2"; 1086ec2c716SMark Zhang nvidia,function = "rsvd1"; 1096ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1106ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1116ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1126ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1136ec2c716SMark Zhang }; 1146ec2c716SMark Zhang dap1_sclk_pb3 { 1156ec2c716SMark Zhang nvidia,pins = "dap1_sclk_pb3"; 1166ec2c716SMark Zhang nvidia,function = "rsvd1"; 1176ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1186ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1196ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1206ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1216ec2c716SMark Zhang }; 1226ec2c716SMark Zhang spi2_mosi_pb4 { 1236ec2c716SMark Zhang nvidia,pins = "spi2_mosi_pb4"; 1246ec2c716SMark Zhang nvidia,function = "rsvd2"; 1256ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1266ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1276ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1286ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1296ec2c716SMark Zhang }; 1306ec2c716SMark Zhang spi2_miso_pb5 { 1316ec2c716SMark Zhang nvidia,pins = "spi2_miso_pb5"; 1326ec2c716SMark Zhang nvidia,function = "rsvd2"; 1336ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1346ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1356ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1366ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1376ec2c716SMark Zhang }; 1386ec2c716SMark Zhang spi2_sck_pb6 { 1396ec2c716SMark Zhang nvidia,pins = "spi2_sck_pb6"; 1406ec2c716SMark Zhang nvidia,function = "rsvd2"; 1416ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1426ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1436ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1446ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1456ec2c716SMark Zhang }; 1466ec2c716SMark Zhang spi2_cs0_pb7 { 1476ec2c716SMark Zhang nvidia,pins = "spi2_cs0_pb7"; 1486ec2c716SMark Zhang nvidia,function = "rsvd2"; 1496ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1506ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1516ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1526ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1536ec2c716SMark Zhang }; 1546ec2c716SMark Zhang spi1_mosi_pc0 { 1556ec2c716SMark Zhang nvidia,pins = "spi1_mosi_pc0"; 1566ec2c716SMark Zhang nvidia,function = "rsvd1"; 1576ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1586ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1596ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1606ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1616ec2c716SMark Zhang }; 1626ec2c716SMark Zhang spi1_miso_pc1 { 1636ec2c716SMark Zhang nvidia,pins = "spi1_miso_pc1"; 1646ec2c716SMark Zhang nvidia,function = "rsvd1"; 1656ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1666ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1676ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1686ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1696ec2c716SMark Zhang }; 1706ec2c716SMark Zhang spi1_sck_pc2 { 1716ec2c716SMark Zhang nvidia,pins = "spi1_sck_pc2"; 1726ec2c716SMark Zhang nvidia,function = "rsvd1"; 1736ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1746ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1756ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1766ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1776ec2c716SMark Zhang }; 1786ec2c716SMark Zhang spi1_cs0_pc3 { 1796ec2c716SMark Zhang nvidia,pins = "spi1_cs0_pc3"; 1806ec2c716SMark Zhang nvidia,function = "rsvd1"; 1816ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1826ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1836ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1846ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1856ec2c716SMark Zhang }; 1866ec2c716SMark Zhang spi1_cs1_pc4 { 1876ec2c716SMark Zhang nvidia,pins = "spi1_cs1_pc4"; 1886ec2c716SMark Zhang nvidia,function = "rsvd1"; 1896ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1906ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1916ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1926ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 1936ec2c716SMark Zhang }; 1946ec2c716SMark Zhang spi4_sck_pc5 { 1956ec2c716SMark Zhang nvidia,pins = "spi4_sck_pc5"; 1966ec2c716SMark Zhang nvidia,function = "rsvd1"; 1976ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1986ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 1996ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2006ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2016ec2c716SMark Zhang }; 2026ec2c716SMark Zhang spi4_cs0_pc6 { 2036ec2c716SMark Zhang nvidia,pins = "spi4_cs0_pc6"; 2046ec2c716SMark Zhang nvidia,function = "rsvd1"; 2056ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2066ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2076ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2086ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2096ec2c716SMark Zhang }; 2106ec2c716SMark Zhang spi4_mosi_pc7 { 2116ec2c716SMark Zhang nvidia,pins = "spi4_mosi_pc7"; 2126ec2c716SMark Zhang nvidia,function = "rsvd1"; 2136ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2146ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2156ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2166ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2176ec2c716SMark Zhang }; 2186ec2c716SMark Zhang spi4_miso_pd0 { 2196ec2c716SMark Zhang nvidia,pins = "spi4_miso_pd0"; 2206ec2c716SMark Zhang nvidia,function = "rsvd1"; 2216ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2226ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2236ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2246ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2256ec2c716SMark Zhang }; 2266ec2c716SMark Zhang uart3_tx_pd1 { 2276ec2c716SMark Zhang nvidia,pins = "uart3_tx_pd1"; 2286ec2c716SMark Zhang nvidia,function = "rsvd2"; 2296ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2306ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2316ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2326ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2336ec2c716SMark Zhang }; 2346ec2c716SMark Zhang uart3_rx_pd2 { 2356ec2c716SMark Zhang nvidia,pins = "uart3_rx_pd2"; 2366ec2c716SMark Zhang nvidia,function = "rsvd2"; 2376ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2386ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2396ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2406ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2416ec2c716SMark Zhang }; 2426ec2c716SMark Zhang uart3_rts_pd3 { 2436ec2c716SMark Zhang nvidia,pins = "uart3_rts_pd3"; 2446ec2c716SMark Zhang nvidia,function = "rsvd2"; 2456ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2466ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2476ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2486ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2496ec2c716SMark Zhang }; 2506ec2c716SMark Zhang uart3_cts_pd4 { 2516ec2c716SMark Zhang nvidia,pins = "uart3_cts_pd4"; 2526ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 2536ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 2546ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2556ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2566ec2c716SMark Zhang }; 2576ec2c716SMark Zhang dmic1_clk_pe0 { 2586ec2c716SMark Zhang nvidia,pins = "dmic1_clk_pe0"; 2596ec2c716SMark Zhang nvidia,function = "rsvd2"; 2606ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2616ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2626ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2636ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2646ec2c716SMark Zhang }; 2656ec2c716SMark Zhang dmic1_dat_pe1 { 2666ec2c716SMark Zhang nvidia,pins = "dmic1_dat_pe1"; 2676ec2c716SMark Zhang nvidia,function = "rsvd2"; 2686ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2696ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2706ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2716ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2726ec2c716SMark Zhang }; 2736ec2c716SMark Zhang dmic2_clk_pe2 { 2746ec2c716SMark Zhang nvidia,pins = "dmic2_clk_pe2"; 2756ec2c716SMark Zhang nvidia,function = "rsvd2"; 2766ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2776ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2786ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2796ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2806ec2c716SMark Zhang }; 2816ec2c716SMark Zhang dmic2_dat_pe3 { 2826ec2c716SMark Zhang nvidia,pins = "dmic2_dat_pe3"; 2836ec2c716SMark Zhang nvidia,function = "rsvd2"; 2846ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 2856ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 2866ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2876ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2886ec2c716SMark Zhang }; 2896ec2c716SMark Zhang dmic3_clk_pe4 { 2906ec2c716SMark Zhang nvidia,pins = "dmic3_clk_pe4"; 2916ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 2926ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 2936ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 2946ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 2956ec2c716SMark Zhang }; 2966ec2c716SMark Zhang dmic3_dat_pe5 { 2976ec2c716SMark Zhang nvidia,pins = "dmic3_dat_pe5"; 2986ec2c716SMark Zhang nvidia,function = "rsvd2"; 2996ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 3006ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 3016ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3026ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3036ec2c716SMark Zhang }; 3046ec2c716SMark Zhang pe6 { 3056ec2c716SMark Zhang nvidia,pins = "pe6"; 3066ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 3076ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3086ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 3096ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3106ec2c716SMark Zhang }; 3116ec2c716SMark Zhang pe7 { 3126ec2c716SMark Zhang nvidia,pins = "pe7"; 3136ec2c716SMark Zhang nvidia,function = "pwm3"; 3146ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 3156ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3166ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3176ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3186ec2c716SMark Zhang }; 3196ec2c716SMark Zhang gen3_i2c_scl_pf0 { 3206ec2c716SMark Zhang nvidia,pins = "gen3_i2c_scl_pf0"; 3216ec2c716SMark Zhang nvidia,function = "i2c3"; 3226ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 3236ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3246ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 3256ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3266ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 3276ec2c716SMark Zhang }; 3286ec2c716SMark Zhang gen3_i2c_sda_pf1 { 3296ec2c716SMark Zhang nvidia,pins = "gen3_i2c_sda_pf1"; 3306ec2c716SMark Zhang nvidia,function = "i2c3"; 3316ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 3326ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3336ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 3346ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3356ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 3366ec2c716SMark Zhang }; 3376ec2c716SMark Zhang uart2_tx_pg0 { 3386ec2c716SMark Zhang nvidia,pins = "uart2_tx_pg0"; 3396ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 3406ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3416ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 3426ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3436ec2c716SMark Zhang }; 3446ec2c716SMark Zhang uart2_rx_pg1 { 3456ec2c716SMark Zhang nvidia,pins = "uart2_rx_pg1"; 3466ec2c716SMark Zhang nvidia,function = "uartb"; 3476ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 3486ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 3496ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3506ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3516ec2c716SMark Zhang }; 3526ec2c716SMark Zhang uart2_rts_pg2 { 3536ec2c716SMark Zhang nvidia,pins = "uart2_rts_pg2"; 3546ec2c716SMark Zhang nvidia,function = "rsvd2"; 3556ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 3566ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 3576ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3586ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3596ec2c716SMark Zhang }; 3606ec2c716SMark Zhang uart2_cts_pg3 { 3616ec2c716SMark Zhang nvidia,pins = "uart2_cts_pg3"; 3626ec2c716SMark Zhang nvidia,function = "rsvd2"; 3636ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 3646ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 3656ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3666ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3676ec2c716SMark Zhang }; 3686ec2c716SMark Zhang wifi_en_ph0 { 3696ec2c716SMark Zhang nvidia,pins = "wifi_en_ph0"; 3706ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 3716ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3726ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3736ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3746ec2c716SMark Zhang }; 3756ec2c716SMark Zhang wifi_rst_ph1 { 3766ec2c716SMark Zhang nvidia,pins = "wifi_rst_ph1"; 3776ec2c716SMark Zhang nvidia,function = "rsvd0"; 3786ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 3796ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 3806ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3816ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3826ec2c716SMark Zhang }; 3836ec2c716SMark Zhang wifi_wake_ap_ph2 { 3846ec2c716SMark Zhang nvidia,pins = "wifi_wake_ap_ph2"; 3856ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 3866ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3876ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 3886ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3896ec2c716SMark Zhang }; 3906ec2c716SMark Zhang ap_wake_bt_ph3 { 3916ec2c716SMark Zhang nvidia,pins = "ap_wake_bt_ph3"; 3926ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 3936ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 3946ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 3956ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 3966ec2c716SMark Zhang }; 3976ec2c716SMark Zhang bt_rst_ph4 { 3986ec2c716SMark Zhang nvidia,pins = "bt_rst_ph4"; 3996ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 4006ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 4016ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4026ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4036ec2c716SMark Zhang }; 4046ec2c716SMark Zhang bt_wake_ap_ph5 { 4056ec2c716SMark Zhang nvidia,pins = "bt_wake_ap_ph5"; 4066ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 4076ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 4086ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 4096ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4106ec2c716SMark Zhang }; 4116ec2c716SMark Zhang ph6 { 4126ec2c716SMark Zhang nvidia,pins = "ph6"; 4136ec2c716SMark Zhang nvidia,function = "rsvd0"; 4146ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 4156ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 4166ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4176ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4186ec2c716SMark Zhang }; 4196ec2c716SMark Zhang ap_wake_nfc_ph7 { 4206ec2c716SMark Zhang nvidia,pins = "ap_wake_nfc_ph7"; 4216ec2c716SMark Zhang nvidia,function = "rsvd0"; 4226ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 4236ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 4246ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4256ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4266ec2c716SMark Zhang }; 4276ec2c716SMark Zhang nfc_en_pi0 { 4286ec2c716SMark Zhang nvidia,pins = "nfc_en_pi0"; 4296ec2c716SMark Zhang nvidia,function = "rsvd0"; 4306ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 4316ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 4326ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4336ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4346ec2c716SMark Zhang }; 4356ec2c716SMark Zhang nfc_int_pi1 { 4366ec2c716SMark Zhang nvidia,pins = "nfc_int_pi1"; 4376ec2c716SMark Zhang nvidia,function = "rsvd0"; 4386ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 4396ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 4406ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4416ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4426ec2c716SMark Zhang }; 4436ec2c716SMark Zhang gps_en_pi2 { 4446ec2c716SMark Zhang nvidia,pins = "gps_en_pi2"; 4456ec2c716SMark Zhang nvidia,function = "rsvd0"; 4466ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 4476ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 4486ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4496ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4506ec2c716SMark Zhang }; 4516ec2c716SMark Zhang gps_rst_pi3 { 4526ec2c716SMark Zhang nvidia,pins = "gps_rst_pi3"; 4536ec2c716SMark Zhang nvidia,function = "rsvd0"; 4546ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 4556ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 4566ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4576ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4586ec2c716SMark Zhang }; 4596ec2c716SMark Zhang uart4_tx_pi4 { 4606ec2c716SMark Zhang nvidia,pins = "uart4_tx_pi4"; 4616ec2c716SMark Zhang nvidia,function = "uartd"; 4626ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 4636ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 4646ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4656ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4666ec2c716SMark Zhang }; 4676ec2c716SMark Zhang uart4_rx_pi5 { 4686ec2c716SMark Zhang nvidia,pins = "uart4_rx_pi5"; 4696ec2c716SMark Zhang nvidia,function = "uartd"; 4706ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 4716ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 4726ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 4736ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4746ec2c716SMark Zhang }; 4756ec2c716SMark Zhang uart4_rts_pi6 { 4766ec2c716SMark Zhang nvidia,pins = "uart4_rts_pi6"; 4776ec2c716SMark Zhang nvidia,function = "uartd"; 4786ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 4796ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 4806ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 4816ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4826ec2c716SMark Zhang }; 4836ec2c716SMark Zhang uart4_cts_pi7 { 4846ec2c716SMark Zhang nvidia,pins = "uart4_cts_pi7"; 4856ec2c716SMark Zhang nvidia,function = "uartd"; 4866ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 4876ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 4886ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 4896ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4906ec2c716SMark Zhang }; 4916ec2c716SMark Zhang gen1_i2c_sda_pj0 { 4926ec2c716SMark Zhang nvidia,pins = "gen1_i2c_sda_pj0"; 4936ec2c716SMark Zhang nvidia,function = "i2c1"; 4946ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 4956ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 4966ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 4976ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 4986ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 4996ec2c716SMark Zhang }; 5006ec2c716SMark Zhang gen1_i2c_scl_pj1 { 5016ec2c716SMark Zhang nvidia,pins = "gen1_i2c_scl_pj1"; 5026ec2c716SMark Zhang nvidia,function = "i2c1"; 5036ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 5046ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 5056ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5066ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5076ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 5086ec2c716SMark Zhang }; 5096ec2c716SMark Zhang gen2_i2c_scl_pj2 { 5106ec2c716SMark Zhang nvidia,pins = "gen2_i2c_scl_pj2"; 5116ec2c716SMark Zhang nvidia,function = "i2c2"; 5126ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 5136ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 5146ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5156ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5166ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 5176ec2c716SMark Zhang }; 5186ec2c716SMark Zhang gen2_i2c_sda_pj3 { 5196ec2c716SMark Zhang nvidia,pins = "gen2_i2c_sda_pj3"; 5206ec2c716SMark Zhang nvidia,function = "i2c2"; 5216ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 5226ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 5236ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 5246ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5256ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 5266ec2c716SMark Zhang }; 5276ec2c716SMark Zhang dap4_fs_pj4 { 5286ec2c716SMark Zhang nvidia,pins = "dap4_fs_pj4"; 5296ec2c716SMark Zhang nvidia,function = "rsvd1"; 5306ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5316ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5326ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5336ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5346ec2c716SMark Zhang }; 5356ec2c716SMark Zhang dap4_din_pj5 { 5366ec2c716SMark Zhang nvidia,pins = "dap4_din_pj5"; 5376ec2c716SMark Zhang nvidia,function = "rsvd1"; 5386ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5396ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5406ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5416ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5426ec2c716SMark Zhang }; 5436ec2c716SMark Zhang dap4_dout_pj6 { 5446ec2c716SMark Zhang nvidia,pins = "dap4_dout_pj6"; 5456ec2c716SMark Zhang nvidia,function = "rsvd1"; 5466ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5476ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5486ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5496ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5506ec2c716SMark Zhang }; 5516ec2c716SMark Zhang dap4_sclk_pj7 { 5526ec2c716SMark Zhang nvidia,pins = "dap4_sclk_pj7"; 5536ec2c716SMark Zhang nvidia,function = "rsvd1"; 5546ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5556ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5566ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5576ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5586ec2c716SMark Zhang }; 5596ec2c716SMark Zhang pk0 { 5606ec2c716SMark Zhang nvidia,pins = "pk0"; 5616ec2c716SMark Zhang nvidia,function = "rsvd2"; 5626ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5636ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5646ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5656ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5666ec2c716SMark Zhang }; 5676ec2c716SMark Zhang pk1 { 5686ec2c716SMark Zhang nvidia,pins = "pk1"; 5696ec2c716SMark Zhang nvidia,function = "rsvd2"; 5706ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5716ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5726ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5736ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5746ec2c716SMark Zhang }; 5756ec2c716SMark Zhang pk2 { 5766ec2c716SMark Zhang nvidia,pins = "pk2"; 5776ec2c716SMark Zhang nvidia,function = "rsvd2"; 5786ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5796ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5806ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5816ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5826ec2c716SMark Zhang }; 5836ec2c716SMark Zhang pk3 { 5846ec2c716SMark Zhang nvidia,pins = "pk3"; 5856ec2c716SMark Zhang nvidia,function = "rsvd2"; 5866ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5876ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5886ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5896ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5906ec2c716SMark Zhang }; 5916ec2c716SMark Zhang pk4 { 5926ec2c716SMark Zhang nvidia,pins = "pk4"; 5936ec2c716SMark Zhang nvidia,function = "rsvd1"; 5946ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 5956ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 5966ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 5976ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 5986ec2c716SMark Zhang }; 5996ec2c716SMark Zhang pk5 { 6006ec2c716SMark Zhang nvidia,pins = "pk5"; 6016ec2c716SMark Zhang nvidia,function = "rsvd1"; 6026ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6036ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6046ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6056ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6066ec2c716SMark Zhang }; 6076ec2c716SMark Zhang pk6 { 6086ec2c716SMark Zhang nvidia,pins = "pk6"; 6096ec2c716SMark Zhang nvidia,function = "rsvd1"; 6106ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6116ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6126ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6136ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6146ec2c716SMark Zhang }; 6156ec2c716SMark Zhang pk7 { 6166ec2c716SMark Zhang nvidia,pins = "pk7"; 6176ec2c716SMark Zhang nvidia,function = "rsvd1"; 6186ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6196ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6206ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6216ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6226ec2c716SMark Zhang }; 6236ec2c716SMark Zhang pl0 { 6246ec2c716SMark Zhang nvidia,pins = "pl0"; 6256ec2c716SMark Zhang nvidia,function = "rsvd0"; 6266ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6276ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6286ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6296ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6306ec2c716SMark Zhang }; 6316ec2c716SMark Zhang pl1 { 6326ec2c716SMark Zhang nvidia,pins = "pl1"; 6336ec2c716SMark Zhang nvidia,function = "rsvd1"; 6346ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6356ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6366ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6376ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6386ec2c716SMark Zhang }; 6396ec2c716SMark Zhang sdmmc1_clk_pm0 { 6406ec2c716SMark Zhang nvidia,pins = "sdmmc1_clk_pm0"; 6416ec2c716SMark Zhang nvidia,function = "rsvd1"; 6426ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6436ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6446ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6456ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6466ec2c716SMark Zhang }; 6476ec2c716SMark Zhang sdmmc1_cmd_pm1 { 6486ec2c716SMark Zhang nvidia,pins = "sdmmc1_cmd_pm1"; 6496ec2c716SMark Zhang nvidia,function = "rsvd2"; 6506ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6516ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6526ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6536ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6546ec2c716SMark Zhang }; 6556ec2c716SMark Zhang sdmmc1_dat3_pm2 { 6566ec2c716SMark Zhang nvidia,pins = "sdmmc1_dat3_pm2"; 6576ec2c716SMark Zhang nvidia,function = "rsvd2"; 6586ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6596ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6606ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6616ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6626ec2c716SMark Zhang }; 6636ec2c716SMark Zhang sdmmc1_dat2_pm3 { 6646ec2c716SMark Zhang nvidia,pins = "sdmmc1_dat2_pm3"; 6656ec2c716SMark Zhang nvidia,function = "rsvd2"; 6666ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6676ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6686ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6696ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6706ec2c716SMark Zhang }; 6716ec2c716SMark Zhang sdmmc1_dat1_pm4 { 6726ec2c716SMark Zhang nvidia,pins = "sdmmc1_dat1_pm4"; 6736ec2c716SMark Zhang nvidia,function = "rsvd2"; 6746ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6756ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6766ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6776ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6786ec2c716SMark Zhang }; 6796ec2c716SMark Zhang sdmmc1_dat0_pm5 { 6806ec2c716SMark Zhang nvidia,pins = "sdmmc1_dat0_pm5"; 6816ec2c716SMark Zhang nvidia,function = "rsvd1"; 6826ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6836ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6846ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6856ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6866ec2c716SMark Zhang }; 6876ec2c716SMark Zhang sdmmc3_clk_pp0 { 6886ec2c716SMark Zhang nvidia,pins = "sdmmc3_clk_pp0"; 6896ec2c716SMark Zhang nvidia,function = "rsvd1"; 6906ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6916ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 6926ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 6936ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 6946ec2c716SMark Zhang }; 6956ec2c716SMark Zhang sdmmc3_cmd_pp1 { 6966ec2c716SMark Zhang nvidia,pins = "sdmmc3_cmd_pp1"; 6976ec2c716SMark Zhang nvidia,function = "rsvd1"; 6986ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 6996ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7006ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7016ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7026ec2c716SMark Zhang }; 7036ec2c716SMark Zhang sdmmc3_dat3_pp2 { 7046ec2c716SMark Zhang nvidia,pins = "sdmmc3_dat3_pp2"; 7056ec2c716SMark Zhang nvidia,function = "rsvd1"; 7066ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7076ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7086ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7096ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7106ec2c716SMark Zhang }; 7116ec2c716SMark Zhang sdmmc3_dat2_pp3 { 7126ec2c716SMark Zhang nvidia,pins = "sdmmc3_dat2_pp3"; 7136ec2c716SMark Zhang nvidia,function = "rsvd1"; 7146ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7156ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7166ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7176ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7186ec2c716SMark Zhang }; 7196ec2c716SMark Zhang sdmmc3_dat1_pp4 { 7206ec2c716SMark Zhang nvidia,pins = "sdmmc3_dat1_pp4"; 7216ec2c716SMark Zhang nvidia,function = "rsvd1"; 7226ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7236ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7246ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7256ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7266ec2c716SMark Zhang }; 7276ec2c716SMark Zhang sdmmc3_dat0_pp5 { 7286ec2c716SMark Zhang nvidia,pins = "sdmmc3_dat0_pp5"; 7296ec2c716SMark Zhang nvidia,function = "rsvd1"; 7306ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7316ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7326ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7336ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7346ec2c716SMark Zhang }; 7356ec2c716SMark Zhang cam1_mclk_ps0 { 7366ec2c716SMark Zhang nvidia,pins = "cam1_mclk_ps0"; 7376ec2c716SMark Zhang nvidia,function = "rsvd1"; 7386ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7396ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7406ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7416ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7426ec2c716SMark Zhang }; 7436ec2c716SMark Zhang cam2_mclk_ps1 { 7446ec2c716SMark Zhang nvidia,pins = "cam2_mclk_ps1"; 7456ec2c716SMark Zhang nvidia,function = "rsvd1"; 7466ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7476ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7486ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7496ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7506ec2c716SMark Zhang }; 7516ec2c716SMark Zhang cam_i2c_scl_ps2 { 7526ec2c716SMark Zhang nvidia,pins = "cam_i2c_scl_ps2"; 7536ec2c716SMark Zhang nvidia,function = "rsvd2"; 7546ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7556ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7566ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7576ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7586ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 7596ec2c716SMark Zhang }; 7606ec2c716SMark Zhang cam_i2c_sda_ps3 { 7616ec2c716SMark Zhang nvidia,pins = "cam_i2c_sda_ps3"; 7626ec2c716SMark Zhang nvidia,function = "rsvd2"; 7636ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7646ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7656ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7666ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7676ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 7686ec2c716SMark Zhang }; 7696ec2c716SMark Zhang cam_rst_ps4 { 7706ec2c716SMark Zhang nvidia,pins = "cam_rst_ps4"; 7716ec2c716SMark Zhang nvidia,function = "rsvd1"; 7726ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7736ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7746ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7756ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7766ec2c716SMark Zhang }; 7776ec2c716SMark Zhang cam_af_en_ps5 { 7786ec2c716SMark Zhang nvidia,pins = "cam_af_en_ps5"; 7796ec2c716SMark Zhang nvidia,function = "rsvd2"; 7806ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7816ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7826ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7836ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7846ec2c716SMark Zhang }; 7856ec2c716SMark Zhang cam_flash_en_ps6 { 7866ec2c716SMark Zhang nvidia,pins = "cam_flash_en_ps6"; 7876ec2c716SMark Zhang nvidia,function = "rsvd2"; 7886ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7896ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7906ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7916ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 7926ec2c716SMark Zhang }; 7936ec2c716SMark Zhang cam1_pwdn_ps7 { 7946ec2c716SMark Zhang nvidia,pins = "cam1_pwdn_ps7"; 7956ec2c716SMark Zhang nvidia,function = "rsvd1"; 7966ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 7976ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 7986ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 7996ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8006ec2c716SMark Zhang }; 8016ec2c716SMark Zhang cam2_pwdn_pt0 { 8026ec2c716SMark Zhang nvidia,pins = "cam2_pwdn_pt0"; 8036ec2c716SMark Zhang nvidia,function = "rsvd1"; 8046ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 8056ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 8066ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8076ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8086ec2c716SMark Zhang }; 8096ec2c716SMark Zhang cam1_strobe_pt1 { 8106ec2c716SMark Zhang nvidia,pins = "cam1_strobe_pt1"; 8116ec2c716SMark Zhang nvidia,function = "rsvd1"; 8126ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 8136ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 8146ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8156ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8166ec2c716SMark Zhang }; 8176ec2c716SMark Zhang uart1_tx_pu0 { 8186ec2c716SMark Zhang nvidia,pins = "uart1_tx_pu0"; 8196ec2c716SMark Zhang nvidia,function = "uarta"; 8206ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 8216ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 8226ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8236ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8246ec2c716SMark Zhang }; 8256ec2c716SMark Zhang uart1_rx_pu1 { 8266ec2c716SMark Zhang nvidia,pins = "uart1_rx_pu1"; 8276ec2c716SMark Zhang nvidia,function = "uarta"; 8286ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 8296ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 8306ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 8316ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8326ec2c716SMark Zhang }; 8336ec2c716SMark Zhang uart1_rts_pu2 { 8346ec2c716SMark Zhang nvidia,pins = "uart1_rts_pu2"; 8356ec2c716SMark Zhang nvidia,function = "uarta"; 8366ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 8376ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 8386ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8396ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8406ec2c716SMark Zhang }; 8416ec2c716SMark Zhang uart1_cts_pu3 { 8426ec2c716SMark Zhang nvidia,pins = "uart1_cts_pu3"; 8436ec2c716SMark Zhang nvidia,function = "uarta"; 8446ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 8456ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 8466ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 8476ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8486ec2c716SMark Zhang }; 8496ec2c716SMark Zhang lcd_bl_pwm_pv0 { 8506ec2c716SMark Zhang nvidia,pins = "lcd_bl_pwm_pv0"; 8516ec2c716SMark Zhang nvidia,function = "pwm0"; 8526ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 8536ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 8546ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8556ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8566ec2c716SMark Zhang }; 8576ec2c716SMark Zhang lcd_bl_en_pv1 { 8586ec2c716SMark Zhang nvidia,pins = "lcd_bl_en_pv1"; 8596ec2c716SMark Zhang nvidia,function = "rsvd0"; 8606ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 8616ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 8626ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8636ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8646ec2c716SMark Zhang }; 8656ec2c716SMark Zhang lcd_rst_pv2 { 8666ec2c716SMark Zhang nvidia,pins = "lcd_rst_pv2"; 8676ec2c716SMark Zhang nvidia,function = "rsvd0"; 8686ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 8696ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 8706ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8716ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8726ec2c716SMark Zhang }; 8736ec2c716SMark Zhang lcd_gpio1_pv3 { 8746ec2c716SMark Zhang nvidia,pins = "lcd_gpio1_pv3"; 8756ec2c716SMark Zhang nvidia,function = "rsvd1"; 8766ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 8776ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 8786ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8796ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8806ec2c716SMark Zhang }; 8816ec2c716SMark Zhang lcd_gpio2_pv4 { 8826ec2c716SMark Zhang nvidia,pins = "lcd_gpio2_pv4"; 8836ec2c716SMark Zhang nvidia,function = "pwm1"; 8846ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 8856ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 8866ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8876ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8886ec2c716SMark Zhang }; 8896ec2c716SMark Zhang ap_ready_pv5 { 8906ec2c716SMark Zhang nvidia,pins = "ap_ready_pv5"; 8916ec2c716SMark Zhang nvidia,function = "rsvd0"; 8926ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 8936ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 8946ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 8956ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 8966ec2c716SMark Zhang }; 8976ec2c716SMark Zhang touch_rst_pv6 { 8986ec2c716SMark Zhang nvidia,pins = "touch_rst_pv6"; 8996ec2c716SMark Zhang nvidia,function = "rsvd0"; 9006ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9016ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9026ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9036ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9046ec2c716SMark Zhang }; 9056ec2c716SMark Zhang touch_clk_pv7 { 9066ec2c716SMark Zhang nvidia,pins = "touch_clk_pv7"; 9076ec2c716SMark Zhang nvidia,function = "rsvd1"; 9086ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9096ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9106ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9116ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9126ec2c716SMark Zhang }; 9136ec2c716SMark Zhang modem_wake_ap_px0 { 9146ec2c716SMark Zhang nvidia,pins = "modem_wake_ap_px0"; 9156ec2c716SMark Zhang nvidia,function = "rsvd0"; 9166ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9176ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9186ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9196ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9206ec2c716SMark Zhang }; 9216ec2c716SMark Zhang touch_int_px1 { 9226ec2c716SMark Zhang nvidia,pins = "touch_int_px1"; 9236ec2c716SMark Zhang nvidia,function = "rsvd0"; 9246ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9256ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9266ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9276ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9286ec2c716SMark Zhang }; 9296ec2c716SMark Zhang motion_int_px2 { 9306ec2c716SMark Zhang nvidia,pins = "motion_int_px2"; 9316ec2c716SMark Zhang nvidia,function = "rsvd0"; 9326ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9336ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9346ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9356ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9366ec2c716SMark Zhang }; 9376ec2c716SMark Zhang als_prox_int_px3 { 9386ec2c716SMark Zhang nvidia,pins = "als_prox_int_px3"; 9396ec2c716SMark Zhang nvidia,function = "rsvd0"; 9406ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9416ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9426ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9436ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9446ec2c716SMark Zhang }; 9456ec2c716SMark Zhang temp_alert_px4 { 9466ec2c716SMark Zhang nvidia,pins = "temp_alert_px4"; 9476ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 9486ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 9496ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 9506ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9516ec2c716SMark Zhang }; 9526ec2c716SMark Zhang button_power_on_px5 { 9536ec2c716SMark Zhang nvidia,pins = "button_power_on_px5"; 9546ec2c716SMark Zhang nvidia,function = "rsvd0"; 9556ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9566ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9576ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9586ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9596ec2c716SMark Zhang }; 9606ec2c716SMark Zhang button_vol_up_px6 { 9616ec2c716SMark Zhang nvidia,pins = "button_vol_up_px6"; 9626ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 9636ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 9646ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 9656ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9666ec2c716SMark Zhang }; 9676ec2c716SMark Zhang button_vol_down_px7 { 9686ec2c716SMark Zhang nvidia,pins = "button_vol_down_px7"; 9696ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 9706ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 9716ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 9726ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9736ec2c716SMark Zhang }; 9746ec2c716SMark Zhang button_slide_sw_py0 { 9756ec2c716SMark Zhang nvidia,pins = "button_slide_sw_py0"; 9766ec2c716SMark Zhang nvidia,function = "rsvd0"; 9776ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9786ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9796ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9806ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9816ec2c716SMark Zhang }; 9826ec2c716SMark Zhang button_home_py1 { 9836ec2c716SMark Zhang nvidia,pins = "button_home_py1"; 9846ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 9856ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 9866ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 9876ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9886ec2c716SMark Zhang }; 9896ec2c716SMark Zhang lcd_te_py2 { 9906ec2c716SMark Zhang nvidia,pins = "lcd_te_py2"; 9916ec2c716SMark Zhang nvidia,function = "rsvd1"; 9926ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 9936ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 9946ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 9956ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 9966ec2c716SMark Zhang }; 9976ec2c716SMark Zhang pwr_i2c_scl_py3 { 9986ec2c716SMark Zhang nvidia,pins = "pwr_i2c_scl_py3"; 9996ec2c716SMark Zhang nvidia,function = "i2cpmu"; 10006ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 10016ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10026ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 10036ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10046ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 10056ec2c716SMark Zhang }; 10066ec2c716SMark Zhang pwr_i2c_sda_py4 { 10076ec2c716SMark Zhang nvidia,pins = "pwr_i2c_sda_py4"; 10086ec2c716SMark Zhang nvidia,function = "i2cpmu"; 10096ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 10106ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10116ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 10126ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10136ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 10146ec2c716SMark Zhang }; 10156ec2c716SMark Zhang clk_32k_out_py5 { 10166ec2c716SMark Zhang nvidia,pins = "clk_32k_out_py5"; 10176ec2c716SMark Zhang nvidia,function = "rsvd2"; 10186ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 10196ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 10206ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 10216ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10226ec2c716SMark Zhang }; 10236ec2c716SMark Zhang pz0 { 10246ec2c716SMark Zhang nvidia,pins = "pz0"; 10256ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 10266ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10276ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 10286ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10296ec2c716SMark Zhang }; 10306ec2c716SMark Zhang pz1 { 10316ec2c716SMark Zhang nvidia,pins = "pz1"; 10326ec2c716SMark Zhang nvidia,function = "rsvd2"; 10336ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 10346ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 10356ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 10366ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10376ec2c716SMark Zhang }; 10386ec2c716SMark Zhang pz2 { 10396ec2c716SMark Zhang nvidia,pins = "pz2"; 10406ec2c716SMark Zhang nvidia,function = "rsvd2"; 10416ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 10426ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 10436ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 10446ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10456ec2c716SMark Zhang }; 10466ec2c716SMark Zhang pz3 { 10476ec2c716SMark Zhang nvidia,pins = "pz3"; 10486ec2c716SMark Zhang nvidia,function = "rsvd1"; 10496ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 10506ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 10516ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 10526ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10536ec2c716SMark Zhang }; 10546ec2c716SMark Zhang pz4 { 10556ec2c716SMark Zhang nvidia,pins = "pz4"; 10566ec2c716SMark Zhang nvidia,function = "rsvd1"; 10576ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 10586ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 10596ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 10606ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10616ec2c716SMark Zhang }; 10626ec2c716SMark Zhang pz5 { 10636ec2c716SMark Zhang nvidia,pins = "pz5"; 10646ec2c716SMark Zhang nvidia,function = "soc"; 10656ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 10666ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10676ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 10686ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10696ec2c716SMark Zhang }; 10706ec2c716SMark Zhang dap2_fs_paa0 { 10716ec2c716SMark Zhang nvidia,pins = "dap2_fs_paa0"; 10726ec2c716SMark Zhang nvidia,function = "i2s2"; 10736ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 10746ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10756ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 10766ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10776ec2c716SMark Zhang }; 10786ec2c716SMark Zhang dap2_sclk_paa1 { 10796ec2c716SMark Zhang nvidia,pins = "dap2_sclk_paa1"; 10806ec2c716SMark Zhang nvidia,function = "i2s2"; 10816ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 10826ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10836ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 10846ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10856ec2c716SMark Zhang }; 10866ec2c716SMark Zhang dap2_din_paa2 { 10876ec2c716SMark Zhang nvidia,pins = "dap2_din_paa2"; 10886ec2c716SMark Zhang nvidia,function = "i2s2"; 10896ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 10906ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10916ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 10926ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 10936ec2c716SMark Zhang }; 10946ec2c716SMark Zhang dap2_dout_paa3 { 10956ec2c716SMark Zhang nvidia,pins = "dap2_dout_paa3"; 10966ec2c716SMark Zhang nvidia,function = "i2s2"; 10976ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 10986ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 10996ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 11006ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11016ec2c716SMark Zhang }; 11026ec2c716SMark Zhang aud_mclk_pbb0 { 11036ec2c716SMark Zhang nvidia,pins = "aud_mclk_pbb0"; 11046ec2c716SMark Zhang nvidia,function = "rsvd1"; 11056ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 11066ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 11076ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11086ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11096ec2c716SMark Zhang }; 11106ec2c716SMark Zhang dvfs_pwm_pbb1 { 11116ec2c716SMark Zhang nvidia,pins = "dvfs_pwm_pbb1"; 11126ec2c716SMark Zhang nvidia,function = "cldvfs"; 11136ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 11146ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 11156ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11166ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11176ec2c716SMark Zhang }; 11186ec2c716SMark Zhang dvfs_clk_pbb2 { 11196ec2c716SMark Zhang nvidia,pins = "dvfs_clk_pbb2"; 11206ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 11216ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 11226ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11236ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11246ec2c716SMark Zhang }; 11256ec2c716SMark Zhang gpio_x1_aud_pbb3 { 11266ec2c716SMark Zhang nvidia,pins = "gpio_x1_aud_pbb3"; 11276ec2c716SMark Zhang nvidia,function = "rsvd0"; 11286ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 11296ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 11306ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11316ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11326ec2c716SMark Zhang }; 11336ec2c716SMark Zhang gpio_x3_aud_pbb4 { 11346ec2c716SMark Zhang nvidia,pins = "gpio_x3_aud_pbb4"; 11356ec2c716SMark Zhang nvidia,function = "rsvd0"; 11366ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 11376ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 11386ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11396ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11406ec2c716SMark Zhang }; 11416ec2c716SMark Zhang hdmi_cec_pcc0 { 11426ec2c716SMark Zhang nvidia,pins = "hdmi_cec_pcc0"; 11436ec2c716SMark Zhang nvidia,function = "cec"; 11446ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 11456ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 11466ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 11476ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11486ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 11496ec2c716SMark Zhang }; 11506ec2c716SMark Zhang hdmi_int_dp_hpd_pcc1 { 11516ec2c716SMark Zhang nvidia,pins = "hdmi_int_dp_hpd_pcc1"; 11526ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 11536ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 11546ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 11556ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11566ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 11576ec2c716SMark Zhang }; 11586ec2c716SMark Zhang spdif_out_pcc2 { 11596ec2c716SMark Zhang nvidia,pins = "spdif_out_pcc2"; 11606ec2c716SMark Zhang nvidia,function = "rsvd1"; 11616ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 11626ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 11636ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11646ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11656ec2c716SMark Zhang }; 11666ec2c716SMark Zhang spdif_in_pcc3 { 11676ec2c716SMark Zhang nvidia,pins = "spdif_in_pcc3"; 11686ec2c716SMark Zhang nvidia,function = "rsvd1"; 11696ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 11706ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 11716ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11726ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11736ec2c716SMark Zhang }; 11746ec2c716SMark Zhang usb_vbus_en0_pcc4 { 11756ec2c716SMark Zhang nvidia,pins = "usb_vbus_en0_pcc4"; 11766ec2c716SMark Zhang nvidia,function = "usb"; 11776ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 11786ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 11796ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 11806ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11816ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 11826ec2c716SMark Zhang }; 11836ec2c716SMark Zhang usb_vbus_en1_pcc5 { 11846ec2c716SMark Zhang nvidia,pins = "usb_vbus_en1_pcc5"; 11856ec2c716SMark Zhang nvidia,function = "usb"; 11866ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 11876ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 11886ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 11896ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11906ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_ENABLE>; 11916ec2c716SMark Zhang }; 11926ec2c716SMark Zhang dp_hpd0_pcc6 { 11936ec2c716SMark Zhang nvidia,pins = "dp_hpd0_pcc6"; 11946ec2c716SMark Zhang nvidia,function = "rsvd1"; 11956ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 11966ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 11976ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 11986ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 11996ec2c716SMark Zhang }; 12006ec2c716SMark Zhang pcc7 { 12016ec2c716SMark Zhang nvidia,pins = "pcc7"; 12026ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 12036ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 12046ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12056ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12066ec2c716SMark Zhang nvidia,io-hv = <TEGRA_PIN_DISABLE>; 12076ec2c716SMark Zhang }; 12086ec2c716SMark Zhang spi2_cs1_pdd0 { 12096ec2c716SMark Zhang nvidia,pins = "spi2_cs1_pdd0"; 12106ec2c716SMark Zhang nvidia,function = "rsvd1"; 12116ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12126ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12136ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12146ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12156ec2c716SMark Zhang }; 12166ec2c716SMark Zhang qspi_sck_pee0 { 12176ec2c716SMark Zhang nvidia,pins = "qspi_sck_pee0"; 12186ec2c716SMark Zhang nvidia,function = "rsvd1"; 12196ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12206ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12216ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12226ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12236ec2c716SMark Zhang }; 12246ec2c716SMark Zhang qspi_cs_n_pee1 { 12256ec2c716SMark Zhang nvidia,pins = "qspi_cs_n_pee1"; 12266ec2c716SMark Zhang nvidia,function = "rsvd1"; 12276ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12286ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12296ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12306ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12316ec2c716SMark Zhang }; 12326ec2c716SMark Zhang qspi_io0_pee2 { 12336ec2c716SMark Zhang nvidia,pins = "qspi_io0_pee2"; 12346ec2c716SMark Zhang nvidia,function = "rsvd1"; 12356ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12366ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12376ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12386ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12396ec2c716SMark Zhang }; 12406ec2c716SMark Zhang qspi_io1_pee3 { 12416ec2c716SMark Zhang nvidia,pins = "qspi_io1_pee3"; 12426ec2c716SMark Zhang nvidia,function = "rsvd1"; 12436ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12446ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12456ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12466ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12476ec2c716SMark Zhang }; 12486ec2c716SMark Zhang qspi_io2_pee4 { 12496ec2c716SMark Zhang nvidia,pins = "qspi_io2_pee4"; 12506ec2c716SMark Zhang nvidia,function = "rsvd1"; 12516ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12526ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12536ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12546ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12556ec2c716SMark Zhang }; 12566ec2c716SMark Zhang qspi_io3_pee5 { 12576ec2c716SMark Zhang nvidia,pins = "qspi_io3_pee5"; 12586ec2c716SMark Zhang nvidia,function = "rsvd1"; 12596ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12606ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12616ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12626ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12636ec2c716SMark Zhang }; 12646ec2c716SMark Zhang core_pwr_req { 12656ec2c716SMark Zhang nvidia,pins = "core_pwr_req"; 12666ec2c716SMark Zhang nvidia,function = "core"; 12676ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 12686ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 12696ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12706ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12716ec2c716SMark Zhang }; 12726ec2c716SMark Zhang cpu_pwr_req { 12736ec2c716SMark Zhang nvidia,pins = "cpu_pwr_req"; 12746ec2c716SMark Zhang nvidia,function = "rsvd1"; 12756ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 12766ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 12776ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 12786ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12796ec2c716SMark Zhang }; 12806ec2c716SMark Zhang pwr_int_n { 12816ec2c716SMark Zhang nvidia,pins = "pwr_int_n"; 12826ec2c716SMark Zhang nvidia,function = "pmi"; 12836ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_UP>; 12846ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 12856ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 12866ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12876ec2c716SMark Zhang }; 12886ec2c716SMark Zhang clk_32k_in { 12896ec2c716SMark Zhang nvidia,pins = "clk_32k_in"; 12906ec2c716SMark Zhang nvidia,function = "clk"; 12916ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 12926ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 12936ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_ENABLE>; 12946ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 12956ec2c716SMark Zhang }; 12966ec2c716SMark Zhang jtag_rtck { 12976ec2c716SMark Zhang nvidia,pins = "jtag_rtck"; 12986ec2c716SMark Zhang nvidia,function = "jtag"; 12996ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 13006ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 13016ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 13026ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 13036ec2c716SMark Zhang }; 13046ec2c716SMark Zhang clk_req { 13056ec2c716SMark Zhang nvidia,pins = "clk_req"; 13066ec2c716SMark Zhang nvidia,function = "rsvd1"; 13076ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 13086ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_ENABLE>; 13096ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 13106ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 13116ec2c716SMark Zhang }; 13126ec2c716SMark Zhang shutdown { 13136ec2c716SMark Zhang nvidia,pins = "shutdown"; 13146ec2c716SMark Zhang nvidia,function = "shutdown"; 13156ec2c716SMark Zhang nvidia,pull = <TEGRA_PIN_PULL_NONE>; 13166ec2c716SMark Zhang nvidia,tristate = <TEGRA_PIN_DISABLE>; 13176ec2c716SMark Zhang nvidia,enable-input = <TEGRA_PIN_DISABLE>; 13186ec2c716SMark Zhang nvidia,open-drain = <TEGRA_PIN_DISABLE>; 13196ec2c716SMark Zhang }; 13206ec2c716SMark Zhang }; 13216ec2c716SMark Zhang }; 13226ec2c716SMark Zhang 1323dd03aeefSMark Zhang serial@70006000 { 1324dd03aeefSMark Zhang status = "okay"; 1325dd03aeefSMark Zhang }; 1326dd03aeefSMark Zhang 132751e5e018SMark Zhang i2c@7000d000 { 132851e5e018SMark Zhang status = "okay"; 132951e5e018SMark Zhang clock-frequency = <400000>; 133051e5e018SMark Zhang 1331bb678298SThierry Reding pmic: pmic@3c { 133251e5e018SMark Zhang compatible = "maxim,max77620"; 133351e5e018SMark Zhang reg = <0x3c>; 133451e5e018SMark Zhang interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 133551e5e018SMark Zhang 133651e5e018SMark Zhang #interrupt-cells = <2>; 133751e5e018SMark Zhang interrupt-controller; 133851e5e018SMark Zhang 133951e5e018SMark Zhang gpio-controller; 134051e5e018SMark Zhang #gpio-cells = <2>; 134151e5e018SMark Zhang 134251e5e018SMark Zhang pinctrl-names = "default"; 134351e5e018SMark Zhang pinctrl-0 = <&max77620_default>; 134451e5e018SMark Zhang 134551e5e018SMark Zhang max77620_default: pinmux@0 { 1346bb678298SThierry Reding gpio0 { 134751e5e018SMark Zhang pins = "gpio0"; 134851e5e018SMark Zhang function = "gpio"; 134951e5e018SMark Zhang }; 135051e5e018SMark Zhang 1351bb678298SThierry Reding gpio1 { 135251e5e018SMark Zhang pins = "gpio1"; 135351e5e018SMark Zhang function = "fps-out"; 135451e5e018SMark Zhang drive-push-pull = <1>; 135551e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 135651e5e018SMark Zhang maxim,active-fps-power-up-slot = <7>; 135751e5e018SMark Zhang maxim,active-fps-power-down-slot = <0>; 135851e5e018SMark Zhang }; 135951e5e018SMark Zhang 1360bb678298SThierry Reding gpio2 { 1361bb678298SThierry Reding pins = "gpio2"; 136251e5e018SMark Zhang function = "fps-out"; 136351e5e018SMark Zhang drive-open-drain = <1>; 136451e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 136551e5e018SMark Zhang }; 136651e5e018SMark Zhang 1367bb678298SThierry Reding gpio3 { 1368bb678298SThierry Reding pins = "gpio3"; 1369bb678298SThierry Reding function = "fps-out"; 1370bb678298SThierry Reding drive-open-drain = <1>; 1371bb678298SThierry Reding maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 1372bb678298SThierry Reding }; 1373bb678298SThierry Reding 1374bb678298SThierry Reding gpio4 { 137551e5e018SMark Zhang pins = "gpio4"; 137651e5e018SMark Zhang function = "32k-out1"; 137751e5e018SMark Zhang }; 137851e5e018SMark Zhang 1379bb678298SThierry Reding gpio5_6_7 { 138051e5e018SMark Zhang pins = "gpio5", "gpio6", "gpio7"; 138151e5e018SMark Zhang function = "gpio"; 138251e5e018SMark Zhang drive-push-pull = <1>; 138351e5e018SMark Zhang }; 138451e5e018SMark Zhang }; 138551e5e018SMark Zhang 1386bb678298SThierry Reding gpio@0 { 138751e5e018SMark Zhang gpio-hog; 138851e5e018SMark Zhang output-high; 1389644c569dSThierry Reding gpios = <2 GPIO_ACTIVE_HIGH>, 1390644c569dSThierry Reding <7 GPIO_ACTIVE_HIGH>; 139151e5e018SMark Zhang }; 139251e5e018SMark Zhang 139351e5e018SMark Zhang fps { 139451e5e018SMark Zhang #address-cells = <1>; 139551e5e018SMark Zhang #size-cells = <0>; 139651e5e018SMark Zhang 139751e5e018SMark Zhang fps0 { 139851e5e018SMark Zhang reg = <0>; 139951e5e018SMark Zhang maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 140051e5e018SMark Zhang }; 140151e5e018SMark Zhang 140251e5e018SMark Zhang fps1 { 140351e5e018SMark Zhang reg = <1>; 140451e5e018SMark Zhang maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; 140551e5e018SMark Zhang maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; 140651e5e018SMark Zhang }; 140751e5e018SMark Zhang 140851e5e018SMark Zhang fps2 { 140951e5e018SMark Zhang reg = <2>; 141051e5e018SMark Zhang maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; 141151e5e018SMark Zhang }; 141251e5e018SMark Zhang }; 141351e5e018SMark Zhang 141451e5e018SMark Zhang regulators { 141551e5e018SMark Zhang in-ldo0-1-supply = <&max77620_sd2>; 141651e5e018SMark Zhang in-ldo7-8-supply = <&max77620_sd2>; 141751e5e018SMark Zhang 141851e5e018SMark Zhang max77620_sd0: sd0 { 141951e5e018SMark Zhang regulator-name = "vdd-core"; 142051e5e018SMark Zhang regulator-enable-ramp-delay = <146>; 142151e5e018SMark Zhang regulator-min-microvolt = <600000>; 142251e5e018SMark Zhang regulator-max-microvolt = <1400000>; 142351e5e018SMark Zhang regulator-ramp-delay = <27500>; 142451e5e018SMark Zhang regulator-always-on; 142551e5e018SMark Zhang regulator-boot-on; 142651e5e018SMark Zhang 142751e5e018SMark Zhang maxim,active-fps-power-up-slot = <0>; 142851e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 142951e5e018SMark Zhang }; 143051e5e018SMark Zhang 143151e5e018SMark Zhang max77620_sd1: sd1 { 143251e5e018SMark Zhang regulator-name = "vddio-ddr"; 143351e5e018SMark Zhang regulator-enable-ramp-delay = <130>; 143451e5e018SMark Zhang regulator-ramp-delay = <27500>; 143551e5e018SMark Zhang regulator-always-on; 143651e5e018SMark Zhang regulator-boot-on; 143751e5e018SMark Zhang 143851e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 143951e5e018SMark Zhang }; 144051e5e018SMark Zhang 144151e5e018SMark Zhang max77620_sd2: sd2 { 144251e5e018SMark Zhang regulator-name = "vdd-pre-reg"; 144351e5e018SMark Zhang regulator-enable-ramp-delay = <176>; 144451e5e018SMark Zhang regulator-min-microvolt = <3000000>; 144551e5e018SMark Zhang regulator-max-microvolt = <3000000>; 144651e5e018SMark Zhang regulator-ramp-delay = <27500>; 144751e5e018SMark Zhang regulator-always-on; 144851e5e018SMark Zhang regulator-boot-on; 144951e5e018SMark Zhang 145051e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 145151e5e018SMark Zhang maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>; 145251e5e018SMark Zhang }; 145351e5e018SMark Zhang 145451e5e018SMark Zhang max77620_sd3: sd3 { 145551e5e018SMark Zhang regulator-name = "vdd-1v8"; 145651e5e018SMark Zhang regulator-enable-ramp-delay = <242>; 145751e5e018SMark Zhang regulator-min-microvolt = <1800000>; 145851e5e018SMark Zhang regulator-max-microvolt = <1800000>; 145951e5e018SMark Zhang regulator-ramp-delay = <27500>; 146051e5e018SMark Zhang regulator-always-on; 146151e5e018SMark Zhang regulator-boot-on; 146251e5e018SMark Zhang 146351e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 146451e5e018SMark Zhang }; 146551e5e018SMark Zhang 146651e5e018SMark Zhang max77620_ldo0: ldo0 { 146751e5e018SMark Zhang regulator-name = "avdd-sys"; 146851e5e018SMark Zhang regulator-enable-ramp-delay = <26>; 146951e5e018SMark Zhang regulator-min-microvolt = <1200000>; 147051e5e018SMark Zhang regulator-max-microvolt = <1200000>; 147151e5e018SMark Zhang regulator-ramp-delay = <100000>; 147251e5e018SMark Zhang regulator-boot-on; 147351e5e018SMark Zhang 147451e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 147551e5e018SMark Zhang }; 147651e5e018SMark Zhang 147751e5e018SMark Zhang max77620_ldo1: ldo1 { 147851e5e018SMark Zhang regulator-name = "vdd-pex"; 147951e5e018SMark Zhang regulator-enable-ramp-delay = <22>; 148051e5e018SMark Zhang regulator-min-microvolt = <1075000>; 148151e5e018SMark Zhang regulator-max-microvolt = <1075000>; 148251e5e018SMark Zhang regulator-ramp-delay = <100000>; 148351e5e018SMark Zhang regulator-always-on; 148451e5e018SMark Zhang 148551e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 148651e5e018SMark Zhang }; 148751e5e018SMark Zhang 148851e5e018SMark Zhang max77620_ldo2: ldo2 { 148951e5e018SMark Zhang regulator-name = "vddio-sdmmc3"; 149051e5e018SMark Zhang regulator-enable-ramp-delay = <62>; 149151e5e018SMark Zhang regulator-min-microvolt = <1800000>; 149251e5e018SMark Zhang regulator-max-microvolt = <3300000>; 149351e5e018SMark Zhang regulator-ramp-delay = <100000>; 149451e5e018SMark Zhang 149551e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 149651e5e018SMark Zhang }; 149751e5e018SMark Zhang 149851e5e018SMark Zhang max77620_ldo3: ldo3 { 149951e5e018SMark Zhang regulator-name = "vdd-3v3-eth"; 150051e5e018SMark Zhang regulator-enable-ramp-delay = <50>; 150151e5e018SMark Zhang regulator-min-microvolt = <3300000>; 150251e5e018SMark Zhang regulator-max-microvolt = <3300000>; 150351e5e018SMark Zhang regulator-ramp-delay = <100000>; 150451e5e018SMark Zhang regulator-always-on; 150551e5e018SMark Zhang regulator-boot-on; 150651e5e018SMark Zhang 150751e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 150851e5e018SMark Zhang }; 150951e5e018SMark Zhang 151051e5e018SMark Zhang max77620_ldo4: ldo4 { 151151e5e018SMark Zhang regulator-name = "vdd-rtc"; 151251e5e018SMark Zhang regulator-enable-ramp-delay = <22>; 151351e5e018SMark Zhang regulator-min-microvolt = <850000>; 151451e5e018SMark Zhang regulator-max-microvolt = <850000>; 151551e5e018SMark Zhang regulator-ramp-delay = <100000>; 151651e5e018SMark Zhang regulator-always-on; 151751e5e018SMark Zhang regulator-boot-on; 151851e5e018SMark Zhang 151951e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_0>; 152051e5e018SMark Zhang }; 152151e5e018SMark Zhang 152251e5e018SMark Zhang max77620_ldo5: ldo5 { 152351e5e018SMark Zhang regulator-name = "avdd-ts-hv"; 152451e5e018SMark Zhang regulator-enable-ramp-delay = <62>; 152551e5e018SMark Zhang regulator-min-microvolt = <3300000>; 152651e5e018SMark Zhang regulator-max-microvolt = <3300000>; 152751e5e018SMark Zhang regulator-ramp-delay = <100000>; 152851e5e018SMark Zhang 152951e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 153051e5e018SMark Zhang }; 153151e5e018SMark Zhang 153251e5e018SMark Zhang max77620_ldo6: ldo6 { 153351e5e018SMark Zhang regulator-name = "vdd-ts"; 153451e5e018SMark Zhang regulator-enable-ramp-delay = <36>; 153551e5e018SMark Zhang regulator-min-microvolt = <1800000>; 153651e5e018SMark Zhang regulator-max-microvolt = <1800000>; 153751e5e018SMark Zhang regulator-ramp-delay = <100000>; 153851e5e018SMark Zhang regulator-boot-on; 153951e5e018SMark Zhang 154051e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; 154151e5e018SMark Zhang }; 154251e5e018SMark Zhang 154351e5e018SMark Zhang max77620_ldo7: ldo7 { 154451e5e018SMark Zhang regulator-name = "vdd-gen-pll-edp"; 154551e5e018SMark Zhang regulator-enable-ramp-delay = <24>; 154651e5e018SMark Zhang regulator-min-microvolt = <1050000>; 154751e5e018SMark Zhang regulator-max-microvolt = <1050000>; 154851e5e018SMark Zhang regulator-ramp-delay = <100000>; 154951e5e018SMark Zhang regulator-always-on; 155051e5e018SMark Zhang regulator-boot-on; 155151e5e018SMark Zhang 155251e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 155351e5e018SMark Zhang maxim,suspend-fps-source = <MAX77620_FPS_SRC_NONE>; 155451e5e018SMark Zhang }; 155551e5e018SMark Zhang 155651e5e018SMark Zhang max77620_ldo8: ldo8 { 155751e5e018SMark Zhang regulator-name = "vdd-hdmi-dp"; 155851e5e018SMark Zhang regulator-enable-ramp-delay = <22>; 155951e5e018SMark Zhang regulator-min-microvolt = <1050000>; 156051e5e018SMark Zhang regulator-max-microvolt = <1050000>; 156151e5e018SMark Zhang regulator-ramp-delay = <100000>; 156251e5e018SMark Zhang regulator-always-on; 156351e5e018SMark Zhang regulator-boot-on; 156451e5e018SMark Zhang 156551e5e018SMark Zhang maxim,active-fps-source = <MAX77620_FPS_SRC_1>; 156651e5e018SMark Zhang }; 156751e5e018SMark Zhang }; 156851e5e018SMark Zhang }; 156951e5e018SMark Zhang }; 157051e5e018SMark Zhang 1571dd03aeefSMark Zhang pmc@7000e400 { 1572dd03aeefSMark Zhang nvidia,invert-interrupt; 1573dd03aeefSMark Zhang nvidia,suspend-mode = <0>; 1574dd03aeefSMark Zhang nvidia,cpu-pwr-good-time = <0>; 1575dd03aeefSMark Zhang nvidia,cpu-pwr-off-time = <0>; 1576dd03aeefSMark Zhang nvidia,core-pwr-good-time = <4587 3876>; 1577dd03aeefSMark Zhang nvidia,core-pwr-off-time = <39065>; 1578dd03aeefSMark Zhang nvidia,core-power-req-active-high; 1579dd03aeefSMark Zhang nvidia,sys-clock-req-active-high; 1580dd03aeefSMark Zhang status = "okay"; 1581dd03aeefSMark Zhang }; 1582dd03aeefSMark Zhang 158367bb17f6SThierry Reding mmc@700b0600 { 1584dd03aeefSMark Zhang bus-width = <8>; 1585dd03aeefSMark Zhang non-removable; 1586dd03aeefSMark Zhang status = "okay"; 1587dd03aeefSMark Zhang }; 1588dd03aeefSMark Zhang 1589*4cc3e3e1SThierry Reding clk32k_in: clock-32k { 1590dd03aeefSMark Zhang compatible = "fixed-clock"; 1591dd03aeefSMark Zhang clock-frequency = <32768>; 1592393a403eSThierry Reding #clock-cells = <0>; 1593dd03aeefSMark Zhang }; 1594dd03aeefSMark Zhang 15957152879dSMark Zhang gpio-keys { 15967152879dSMark Zhang compatible = "gpio-keys"; 15977152879dSMark Zhang status = "okay"; 15987152879dSMark Zhang 15997152879dSMark Zhang power { 16007152879dSMark Zhang debounce-interval = <30>; 16017152879dSMark Zhang gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 16027152879dSMark Zhang label = "Power"; 16037152879dSMark Zhang linux,code = <KEY_POWER>; 16047152879dSMark Zhang wakeup-event-action = <EV_ACT_ASSERTED>; 16057152879dSMark Zhang wakeup-source; 16067152879dSMark Zhang }; 16077152879dSMark Zhang }; 16087152879dSMark Zhang 1609dd03aeefSMark Zhang cpus { 1610dd03aeefSMark Zhang cpu@0 { 1611dd03aeefSMark Zhang enable-method = "psci"; 1612dd03aeefSMark Zhang }; 1613dd03aeefSMark Zhang 1614dd03aeefSMark Zhang cpu@1 { 1615dd03aeefSMark Zhang enable-method = "psci"; 1616dd03aeefSMark Zhang }; 1617dd03aeefSMark Zhang 1618dd03aeefSMark Zhang cpu@2 { 1619dd03aeefSMark Zhang enable-method = "psci"; 1620dd03aeefSMark Zhang }; 1621dd03aeefSMark Zhang 1622dd03aeefSMark Zhang cpu@3 { 1623dd03aeefSMark Zhang enable-method = "psci"; 1624dd03aeefSMark Zhang }; 16253056c1caSJoseph Lo 16263056c1caSJoseph Lo idle-states { 16273056c1caSJoseph Lo cpu-sleep { 16283056c1caSJoseph Lo status = "okay"; 16293056c1caSJoseph Lo }; 16303056c1caSJoseph Lo }; 1631dd03aeefSMark Zhang }; 1632dd03aeefSMark Zhang 1633dd03aeefSMark Zhang psci { 1634dd03aeefSMark Zhang compatible = "arm,psci-1.0"; 1635dd03aeefSMark Zhang method = "smc"; 1636dd03aeefSMark Zhang }; 163751e5e018SMark Zhang 163851e5e018SMark Zhang battery_reg: regulator@0 { 163951e5e018SMark Zhang compatible = "regulator-fixed"; 164051e5e018SMark Zhang regulator-name = "vdd-ac-bat"; 164151e5e018SMark Zhang regulator-min-microvolt = <5000000>; 164251e5e018SMark Zhang regulator-max-microvolt = <5000000>; 164351e5e018SMark Zhang regulator-always-on; 164451e5e018SMark Zhang }; 164551e5e018SMark Zhang 164651e5e018SMark Zhang vdd_3v3: regulator@1 { 164751e5e018SMark Zhang compatible = "regulator-fixed"; 164851e5e018SMark Zhang regulator-name = "vdd-3v3"; 164951e5e018SMark Zhang regulator-enable-ramp-delay = <160>; 165051e5e018SMark Zhang regulator-min-microvolt = <3300000>; 165151e5e018SMark Zhang regulator-max-microvolt = <3300000>; 165251e5e018SMark Zhang regulator-always-on; 165351e5e018SMark Zhang 1654bb678298SThierry Reding gpio = <&pmic 3 GPIO_ACTIVE_HIGH>; 165551e5e018SMark Zhang enable-active-high; 165651e5e018SMark Zhang }; 165751e5e018SMark Zhang 165851e5e018SMark Zhang max77620_gpio7: regulator@2 { 165951e5e018SMark Zhang compatible = "regulator-fixed"; 166051e5e018SMark Zhang regulator-name = "max77620-gpio7"; 166151e5e018SMark Zhang regulator-enable-ramp-delay = <240>; 166251e5e018SMark Zhang regulator-min-microvolt = <1200000>; 166351e5e018SMark Zhang regulator-max-microvolt = <1200000>; 166451e5e018SMark Zhang vin-supply = <&max77620_ldo0>; 166551e5e018SMark Zhang regulator-always-on; 166651e5e018SMark Zhang regulator-boot-on; 166751e5e018SMark Zhang 1668bb678298SThierry Reding gpio = <&pmic 7 GPIO_ACTIVE_HIGH>; 166951e5e018SMark Zhang enable-active-high; 167051e5e018SMark Zhang }; 167151e5e018SMark Zhang 167251e5e018SMark Zhang lcd_bl_en: regulator@3 { 167351e5e018SMark Zhang compatible = "regulator-fixed"; 167451e5e018SMark Zhang regulator-name = "lcd-bl-en"; 167551e5e018SMark Zhang regulator-min-microvolt = <1800000>; 167651e5e018SMark Zhang regulator-max-microvolt = <1800000>; 167751e5e018SMark Zhang regulator-boot-on; 167851e5e018SMark Zhang 167951e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; 168051e5e018SMark Zhang enable-active-high; 168151e5e018SMark Zhang }; 168251e5e018SMark Zhang 168351e5e018SMark Zhang en_vdd_sd: regulator@4 { 168451e5e018SMark Zhang compatible = "regulator-fixed"; 168551e5e018SMark Zhang regulator-name = "en-vdd-sd"; 168651e5e018SMark Zhang regulator-enable-ramp-delay = <472>; 168751e5e018SMark Zhang regulator-min-microvolt = <3300000>; 168851e5e018SMark Zhang regulator-max-microvolt = <3300000>; 168951e5e018SMark Zhang vin-supply = <&vdd_3v3>; 169051e5e018SMark Zhang 169151e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; 169251e5e018SMark Zhang enable-active-high; 169351e5e018SMark Zhang }; 169451e5e018SMark Zhang 169551e5e018SMark Zhang en_vdd_cam: regulator@5 { 169651e5e018SMark Zhang compatible = "regulator-fixed"; 169751e5e018SMark Zhang regulator-name = "en-vdd-cam"; 169851e5e018SMark Zhang regulator-min-microvolt = <1800000>; 169951e5e018SMark Zhang regulator-max-microvolt = <1800000>; 170051e5e018SMark Zhang 170151e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_HIGH>; 170251e5e018SMark Zhang enable-active-high; 170351e5e018SMark Zhang }; 170451e5e018SMark Zhang 170551e5e018SMark Zhang vdd_sys_boost: regulator@6 { 170651e5e018SMark Zhang compatible = "regulator-fixed"; 170751e5e018SMark Zhang regulator-name = "vdd-sys-boost"; 170851e5e018SMark Zhang regulator-enable-ramp-delay = <3090>; 170951e5e018SMark Zhang regulator-min-microvolt = <5000000>; 171051e5e018SMark Zhang regulator-max-microvolt = <5000000>; 171151e5e018SMark Zhang regulator-always-on; 171251e5e018SMark Zhang 1713bb678298SThierry Reding gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; 171451e5e018SMark Zhang enable-active-high; 171551e5e018SMark Zhang }; 171651e5e018SMark Zhang 171751e5e018SMark Zhang vdd_hdmi: regulator@7 { 171851e5e018SMark Zhang compatible = "regulator-fixed"; 171951e5e018SMark Zhang regulator-name = "vdd-hdmi"; 172051e5e018SMark Zhang regulator-enable-ramp-delay = <468>; 172151e5e018SMark Zhang regulator-min-microvolt = <5000000>; 172251e5e018SMark Zhang regulator-max-microvolt = <5000000>; 172351e5e018SMark Zhang vin-supply = <&vdd_sys_boost>; 172451e5e018SMark Zhang regulator-boot-on; 172551e5e018SMark Zhang 172651e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(CC, 7) GPIO_ACTIVE_HIGH>; 172751e5e018SMark Zhang enable-active-high; 172851e5e018SMark Zhang }; 172951e5e018SMark Zhang 173051e5e018SMark Zhang en_vdd_cpu_fixed: regulator@8 { 173151e5e018SMark Zhang compatible = "regulator-fixed"; 173251e5e018SMark Zhang regulator-name = "vdd-cpu-fixed"; 173351e5e018SMark Zhang regulator-min-microvolt = <1000000>; 173451e5e018SMark Zhang regulator-max-microvolt = <1000000>; 173551e5e018SMark Zhang }; 173651e5e018SMark Zhang 173751e5e018SMark Zhang vdd_aux_3v3: regulator@9 { 173851e5e018SMark Zhang compatible = "regulator-fixed"; 173951e5e018SMark Zhang regulator-name = "aux-3v3"; 174051e5e018SMark Zhang regulator-min-microvolt = <3300000>; 174151e5e018SMark Zhang regulator-max-microvolt = <3300000>; 174251e5e018SMark Zhang }; 174351e5e018SMark Zhang 174451e5e018SMark Zhang vdd_snsr_pm: regulator@10 { 174551e5e018SMark Zhang compatible = "regulator-fixed"; 174651e5e018SMark Zhang regulator-name = "snsr_pm"; 174751e5e018SMark Zhang regulator-min-microvolt = <3300000>; 174851e5e018SMark Zhang regulator-max-microvolt = <3300000>; 174951e5e018SMark Zhang 175051e5e018SMark Zhang enable-active-high; 175151e5e018SMark Zhang }; 175251e5e018SMark Zhang 175351e5e018SMark Zhang vdd_usb_5v0: regulator@11 { 175451e5e018SMark Zhang compatible = "regulator-fixed"; 175551e5e018SMark Zhang status = "disabled"; 175651e5e018SMark Zhang regulator-name = "vdd-usb-5v0"; 175751e5e018SMark Zhang regulator-min-microvolt = <5000000>; 175851e5e018SMark Zhang regulator-max-microvolt = <5000000>; 175951e5e018SMark Zhang vin-supply = <&vdd_3v3>; 176051e5e018SMark Zhang 176151e5e018SMark Zhang enable-active-high; 176251e5e018SMark Zhang }; 176351e5e018SMark Zhang 176451e5e018SMark Zhang vdd_cdc_1v2_aud: regulator@101 { 176551e5e018SMark Zhang compatible = "regulator-fixed"; 176651e5e018SMark Zhang status = "disabled"; 176751e5e018SMark Zhang regulator-name = "vdd_cdc_1v2_aud"; 176851e5e018SMark Zhang regulator-min-microvolt = <1200000>; 176951e5e018SMark Zhang regulator-max-microvolt = <1200000>; 177051e5e018SMark Zhang startup-delay-us = <250000>; 177151e5e018SMark Zhang 177251e5e018SMark Zhang enable-active-high; 177351e5e018SMark Zhang }; 177451e5e018SMark Zhang 177551e5e018SMark Zhang vdd_disp_3v0: regulator@12 { 177651e5e018SMark Zhang compatible = "regulator-fixed"; 177751e5e018SMark Zhang regulator-name = "vdd-disp-3v0"; 177851e5e018SMark Zhang regulator-enable-ramp-delay = <232>; 177951e5e018SMark Zhang regulator-min-microvolt = <3000000>; 178051e5e018SMark Zhang regulator-max-microvolt = <3000000>; 178151e5e018SMark Zhang regulator-always-on; 178251e5e018SMark Zhang 178351e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>; 178451e5e018SMark Zhang enable-active-high; 178551e5e018SMark Zhang }; 178651e5e018SMark Zhang 178751e5e018SMark Zhang vdd_fan: regulator@13 { 178851e5e018SMark Zhang compatible = "regulator-fixed"; 178951e5e018SMark Zhang regulator-name = "vdd-fan"; 179051e5e018SMark Zhang regulator-enable-ramp-delay = <284>; 179151e5e018SMark Zhang regulator-min-microvolt = <5000000>; 179251e5e018SMark Zhang regulator-max-microvolt = <5000000>; 179351e5e018SMark Zhang 179451e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(E, 4) GPIO_ACTIVE_HIGH>; 179551e5e018SMark Zhang enable-active-high; 179651e5e018SMark Zhang }; 179751e5e018SMark Zhang 179851e5e018SMark Zhang usb_vbus1: regulator@14 { 179951e5e018SMark Zhang compatible = "regulator-fixed"; 180051e5e018SMark Zhang regulator-name = "usb-vbus1"; 180151e5e018SMark Zhang regulator-min-microvolt = <5000000>; 180251e5e018SMark Zhang regulator-max-microvolt = <5000000>; 180351e5e018SMark Zhang 180451e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; 180551e5e018SMark Zhang enable-active-high; 180651e5e018SMark Zhang gpio-open-drain; 180751e5e018SMark Zhang }; 180851e5e018SMark Zhang 180951e5e018SMark Zhang usb_vbus2: regulator@15 { 181051e5e018SMark Zhang compatible = "regulator-fixed"; 181151e5e018SMark Zhang regulator-name = "usb-vbus2"; 181251e5e018SMark Zhang regulator-min-microvolt = <5000000>; 181351e5e018SMark Zhang regulator-max-microvolt = <5000000>; 181451e5e018SMark Zhang 181551e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>; 181651e5e018SMark Zhang enable-active-high; 181751e5e018SMark Zhang gpio-open-drain; 181851e5e018SMark Zhang }; 181951e5e018SMark Zhang 182051e5e018SMark Zhang vdd_3v3_eth: regulator@16 { 182151e5e018SMark Zhang compatible = "regulator-fixed"; 182251e5e018SMark Zhang regulator-name = "vdd-3v3-eth-a02"; 182351e5e018SMark Zhang regulator-min-microvolt = <3300000>; 182451e5e018SMark Zhang regulator-max-microvolt = <3300000>; 182551e5e018SMark Zhang regulator-always-on; 182651e5e018SMark Zhang regulator-boot-on; 182751e5e018SMark Zhang 182851e5e018SMark Zhang gpio = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 182951e5e018SMark Zhang enable-active-high; 183051e5e018SMark Zhang gpio-open-drain; 183151e5e018SMark Zhang }; 183251e5e018SMark Zhang}; 1833