15df50128SLars Povlsen// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 25df50128SLars Povlsen/* 35df50128SLars Povlsen * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 45df50128SLars Povlsen */ 55df50128SLars Povlsen 65df50128SLars Povlsen&gpio { 75df50128SLars Povlsen cs14_pins: cs14-pins { 85df50128SLars Povlsen pins = "GPIO_44"; 95df50128SLars Povlsen function = "si"; 105df50128SLars Povlsen }; 115df50128SLars Povlsen}; 125df50128SLars Povlsen 135df50128SLars Povlsen&spi0 { 145df50128SLars Povlsen pinctrl-0 = <&si2_pins>; 155df50128SLars Povlsen pinctrl-names = "default"; 165df50128SLars Povlsen spi@e { 175df50128SLars Povlsen compatible = "spi-mux"; 185df50128SLars Povlsen mux-controls = <&mux>; 195df50128SLars Povlsen #address-cells = <1>; 205df50128SLars Povlsen #size-cells = <0>; 215df50128SLars Povlsen reg = <14>; /* CS14 */ 22*402eb8ecSKrzysztof Kozlowski flash@6 { 235df50128SLars Povlsen compatible = "spi-nand"; 245df50128SLars Povlsen pinctrl-0 = <&cs14_pins>; 255df50128SLars Povlsen pinctrl-names = "default"; 265df50128SLars Povlsen reg = <0x6>; /* SPI2 */ 275df50128SLars Povlsen spi-max-frequency = <42000000>; 285df50128SLars Povlsen rx-sample-delay-ns = <7>; /* Tune for speed */ 295df50128SLars Povlsen }; 305df50128SLars Povlsen }; 315df50128SLars Povlsen}; 32