1*c4629c34SSean Wang/* 2*c4629c34SSean Wang * Copyright (c) 2017 MediaTek Inc. 3*c4629c34SSean Wang * Author: Ming Huang <ming.huang@mediatek.com> 4*c4629c34SSean Wang * Sean Wang <sean.wang@mediatek.com> 5*c4629c34SSean Wang * 6*c4629c34SSean Wang * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7*c4629c34SSean Wang */ 8*c4629c34SSean Wang 9*c4629c34SSean Wang#include <dt-bindings/interrupt-controller/irq.h> 10*c4629c34SSean Wang#include <dt-bindings/interrupt-controller/arm-gic.h> 11*c4629c34SSean Wang 12*c4629c34SSean Wang/ { 13*c4629c34SSean Wang compatible = "mediatek,mt7622"; 14*c4629c34SSean Wang interrupt-parent = <&sysirq>; 15*c4629c34SSean Wang #address-cells = <2>; 16*c4629c34SSean Wang #size-cells = <2>; 17*c4629c34SSean Wang 18*c4629c34SSean Wang cpus { 19*c4629c34SSean Wang #address-cells = <2>; 20*c4629c34SSean Wang #size-cells = <0>; 21*c4629c34SSean Wang 22*c4629c34SSean Wang cpu0: cpu@0 { 23*c4629c34SSean Wang device_type = "cpu"; 24*c4629c34SSean Wang compatible = "arm,cortex-a53", "arm,armv8"; 25*c4629c34SSean Wang reg = <0x0 0x0>; 26*c4629c34SSean Wang enable-method = "psci"; 27*c4629c34SSean Wang clock-frequency = <1300000000>; 28*c4629c34SSean Wang }; 29*c4629c34SSean Wang 30*c4629c34SSean Wang cpu1: cpu@1 { 31*c4629c34SSean Wang device_type = "cpu"; 32*c4629c34SSean Wang compatible = "arm,cortex-a53", "arm,armv8"; 33*c4629c34SSean Wang reg = <0x0 0x1>; 34*c4629c34SSean Wang enable-method = "psci"; 35*c4629c34SSean Wang clock-frequency = <1300000000>; 36*c4629c34SSean Wang }; 37*c4629c34SSean Wang }; 38*c4629c34SSean Wang 39*c4629c34SSean Wang uart_clk: dummy25m { 40*c4629c34SSean Wang compatible = "fixed-clock"; 41*c4629c34SSean Wang #clock-cells = <0>; 42*c4629c34SSean Wang clock-frequency = <25000000>; 43*c4629c34SSean Wang }; 44*c4629c34SSean Wang 45*c4629c34SSean Wang bus_clk: dummy280m { 46*c4629c34SSean Wang compatible = "fixed-clock"; 47*c4629c34SSean Wang #clock-cells = <0>; 48*c4629c34SSean Wang clock-frequency = <280000000>; 49*c4629c34SSean Wang }; 50*c4629c34SSean Wang 51*c4629c34SSean Wang psci { 52*c4629c34SSean Wang compatible = "arm,psci-0.2"; 53*c4629c34SSean Wang method = "smc"; 54*c4629c34SSean Wang }; 55*c4629c34SSean Wang 56*c4629c34SSean Wang reserved-memory { 57*c4629c34SSean Wang #address-cells = <2>; 58*c4629c34SSean Wang #size-cells = <2>; 59*c4629c34SSean Wang ranges; 60*c4629c34SSean Wang 61*c4629c34SSean Wang /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 62*c4629c34SSean Wang secmon_reserved: secmon@43000000 { 63*c4629c34SSean Wang reg = <0 0x43000000 0 0x30000>; 64*c4629c34SSean Wang no-map; 65*c4629c34SSean Wang }; 66*c4629c34SSean Wang }; 67*c4629c34SSean Wang 68*c4629c34SSean Wang timer { 69*c4629c34SSean Wang compatible = "arm,armv8-timer"; 70*c4629c34SSean Wang interrupt-parent = <&gic>; 71*c4629c34SSean Wang interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 72*c4629c34SSean Wang IRQ_TYPE_LEVEL_HIGH)>, 73*c4629c34SSean Wang <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 74*c4629c34SSean Wang IRQ_TYPE_LEVEL_HIGH)>, 75*c4629c34SSean Wang <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 76*c4629c34SSean Wang IRQ_TYPE_LEVEL_HIGH)>, 77*c4629c34SSean Wang <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 78*c4629c34SSean Wang IRQ_TYPE_LEVEL_HIGH)>; 79*c4629c34SSean Wang }; 80*c4629c34SSean Wang 81*c4629c34SSean Wang sysirq: interrupt-controller@10200620 { 82*c4629c34SSean Wang compatible = "mediatek,mt7622-sysirq", 83*c4629c34SSean Wang "mediatek,mt6577-sysirq"; 84*c4629c34SSean Wang interrupt-controller; 85*c4629c34SSean Wang #interrupt-cells = <3>; 86*c4629c34SSean Wang interrupt-parent = <&gic>; 87*c4629c34SSean Wang reg = <0 0x10200620 0 0x20>; 88*c4629c34SSean Wang }; 89*c4629c34SSean Wang 90*c4629c34SSean Wang gic: interrupt-controller@10300000 { 91*c4629c34SSean Wang compatible = "arm,gic-400"; 92*c4629c34SSean Wang interrupt-controller; 93*c4629c34SSean Wang #interrupt-cells = <3>; 94*c4629c34SSean Wang interrupt-parent = <&gic>; 95*c4629c34SSean Wang reg = <0 0x10310000 0 0x1000>, 96*c4629c34SSean Wang <0 0x10320000 0 0x1000>, 97*c4629c34SSean Wang <0 0x10340000 0 0x2000>, 98*c4629c34SSean Wang <0 0x10360000 0 0x2000>; 99*c4629c34SSean Wang }; 100*c4629c34SSean Wang 101*c4629c34SSean Wang uart0: serial@11002000 { 102*c4629c34SSean Wang compatible = "mediatek,mt7622-uart", 103*c4629c34SSean Wang "mediatek,mt6577-uart"; 104*c4629c34SSean Wang reg = <0 0x11002000 0 0x400>; 105*c4629c34SSean Wang interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 106*c4629c34SSean Wang clocks = <&uart_clk>, <&bus_clk>; 107*c4629c34SSean Wang clock-names = "baud", "bus"; 108*c4629c34SSean Wang status = "disabled"; 109*c4629c34SSean Wang }; 110*c4629c34SSean Wang}; 111