1*cbafcad0SMiquel Raynal// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*cbafcad0SMiquel Raynal/* 3*cbafcad0SMiquel Raynal * Device Tree file for Marvell Armada AP807 Quad 4*cbafcad0SMiquel Raynal * 5*cbafcad0SMiquel Raynal * Copyright (C) 2019 Marvell Technology Group Ltd. 6*cbafcad0SMiquel Raynal */ 7*cbafcad0SMiquel Raynal 8*cbafcad0SMiquel Raynal#include "armada-ap807.dtsi" 9*cbafcad0SMiquel Raynal 10*cbafcad0SMiquel Raynal/ { 11*cbafcad0SMiquel Raynal model = "Marvell Armada AP807 Quad"; 12*cbafcad0SMiquel Raynal compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; 13*cbafcad0SMiquel Raynal 14*cbafcad0SMiquel Raynal cpus { 15*cbafcad0SMiquel Raynal #address-cells = <1>; 16*cbafcad0SMiquel Raynal #size-cells = <0>; 17*cbafcad0SMiquel Raynal 18*cbafcad0SMiquel Raynal cpu0: cpu@0 { 19*cbafcad0SMiquel Raynal device_type = "cpu"; 20*cbafcad0SMiquel Raynal compatible = "arm,cortex-a72", "arm,armv8"; 21*cbafcad0SMiquel Raynal reg = <0x000>; 22*cbafcad0SMiquel Raynal enable-method = "psci"; 23*cbafcad0SMiquel Raynal #cooling-cells = <2>; 24*cbafcad0SMiquel Raynal clocks = <&cpu_clk 0>; 25*cbafcad0SMiquel Raynal }; 26*cbafcad0SMiquel Raynal cpu1: cpu@1 { 27*cbafcad0SMiquel Raynal device_type = "cpu"; 28*cbafcad0SMiquel Raynal compatible = "arm,cortex-a72", "arm,armv8"; 29*cbafcad0SMiquel Raynal reg = <0x001>; 30*cbafcad0SMiquel Raynal enable-method = "psci"; 31*cbafcad0SMiquel Raynal #cooling-cells = <2>; 32*cbafcad0SMiquel Raynal clocks = <&cpu_clk 0>; 33*cbafcad0SMiquel Raynal }; 34*cbafcad0SMiquel Raynal cpu2: cpu@100 { 35*cbafcad0SMiquel Raynal device_type = "cpu"; 36*cbafcad0SMiquel Raynal compatible = "arm,cortex-a72", "arm,armv8"; 37*cbafcad0SMiquel Raynal reg = <0x100>; 38*cbafcad0SMiquel Raynal enable-method = "psci"; 39*cbafcad0SMiquel Raynal #cooling-cells = <2>; 40*cbafcad0SMiquel Raynal clocks = <&cpu_clk 1>; 41*cbafcad0SMiquel Raynal }; 42*cbafcad0SMiquel Raynal cpu3: cpu@101 { 43*cbafcad0SMiquel Raynal device_type = "cpu"; 44*cbafcad0SMiquel Raynal compatible = "arm,cortex-a72", "arm,armv8"; 45*cbafcad0SMiquel Raynal reg = <0x101>; 46*cbafcad0SMiquel Raynal enable-method = "psci"; 47*cbafcad0SMiquel Raynal #cooling-cells = <2>; 48*cbafcad0SMiquel Raynal clocks = <&cpu_clk 1>; 49*cbafcad0SMiquel Raynal }; 50*cbafcad0SMiquel Raynal }; 51*cbafcad0SMiquel Raynal}; 52