1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ec7e5a56SThomas Petazzoni/* 3ec7e5a56SThomas Petazzoni * Copyright (C) 2016 Marvell Technology Group Ltd. 4ec7e5a56SThomas Petazzoni * 5ec7e5a56SThomas Petazzoni * Device Tree file for Marvell Armada AP806. 6ec7e5a56SThomas Petazzoni */ 7ec7e5a56SThomas Petazzoni 8ec7e5a56SThomas Petazzoni#include "armada-ap806.dtsi" 9ec7e5a56SThomas Petazzoni 10ec7e5a56SThomas Petazzoni/ { 11ec7e5a56SThomas Petazzoni model = "Marvell Armada AP806 Quad"; 12ec7e5a56SThomas Petazzoni compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; 13ec7e5a56SThomas Petazzoni 14ec7e5a56SThomas Petazzoni cpus { 15ec7e5a56SThomas Petazzoni #address-cells = <1>; 16ec7e5a56SThomas Petazzoni #size-cells = <0>; 17ec7e5a56SThomas Petazzoni 1892e5d4e9SGregory CLEMENT cpu0: cpu@0 { 19ec7e5a56SThomas Petazzoni device_type = "cpu"; 2031af04cdSRob Herring compatible = "arm,cortex-a72"; 21ec7e5a56SThomas Petazzoni reg = <0x000>; 22ec7e5a56SThomas Petazzoni enable-method = "psci"; 23fe7f7f22SMiquel Raynal #cooling-cells = <2>; 24c00bc383SGregory CLEMENT clocks = <&cpu_clk 0>; 25*760cabcdSGrzegorz Jaszczyk i-cache-size = <0xc000>; 26*760cabcdSGrzegorz Jaszczyk i-cache-line-size = <64>; 27*760cabcdSGrzegorz Jaszczyk i-cache-sets = <256>; 28*760cabcdSGrzegorz Jaszczyk d-cache-size = <0x8000>; 29*760cabcdSGrzegorz Jaszczyk d-cache-line-size = <64>; 30*760cabcdSGrzegorz Jaszczyk d-cache-sets = <256>; 31*760cabcdSGrzegorz Jaszczyk next-level-cache = <&l2_0>; 32ec7e5a56SThomas Petazzoni }; 3392e5d4e9SGregory CLEMENT cpu1: cpu@1 { 34ec7e5a56SThomas Petazzoni device_type = "cpu"; 3531af04cdSRob Herring compatible = "arm,cortex-a72"; 36ec7e5a56SThomas Petazzoni reg = <0x001>; 37ec7e5a56SThomas Petazzoni enable-method = "psci"; 38fe7f7f22SMiquel Raynal #cooling-cells = <2>; 39c00bc383SGregory CLEMENT clocks = <&cpu_clk 0>; 40*760cabcdSGrzegorz Jaszczyk i-cache-size = <0xc000>; 41*760cabcdSGrzegorz Jaszczyk i-cache-line-size = <64>; 42*760cabcdSGrzegorz Jaszczyk i-cache-sets = <256>; 43*760cabcdSGrzegorz Jaszczyk d-cache-size = <0x8000>; 44*760cabcdSGrzegorz Jaszczyk d-cache-line-size = <64>; 45*760cabcdSGrzegorz Jaszczyk d-cache-sets = <256>; 46*760cabcdSGrzegorz Jaszczyk next-level-cache = <&l2_0>; 47ec7e5a56SThomas Petazzoni }; 4892e5d4e9SGregory CLEMENT cpu2: cpu@100 { 49ec7e5a56SThomas Petazzoni device_type = "cpu"; 5031af04cdSRob Herring compatible = "arm,cortex-a72"; 51ec7e5a56SThomas Petazzoni reg = <0x100>; 52ec7e5a56SThomas Petazzoni enable-method = "psci"; 53fe7f7f22SMiquel Raynal #cooling-cells = <2>; 54c00bc383SGregory CLEMENT clocks = <&cpu_clk 1>; 55*760cabcdSGrzegorz Jaszczyk i-cache-size = <0xc000>; 56*760cabcdSGrzegorz Jaszczyk i-cache-line-size = <64>; 57*760cabcdSGrzegorz Jaszczyk i-cache-sets = <256>; 58*760cabcdSGrzegorz Jaszczyk d-cache-size = <0x8000>; 59*760cabcdSGrzegorz Jaszczyk d-cache-line-size = <64>; 60*760cabcdSGrzegorz Jaszczyk d-cache-sets = <256>; 61*760cabcdSGrzegorz Jaszczyk next-level-cache = <&l2_1>; 62ec7e5a56SThomas Petazzoni }; 6392e5d4e9SGregory CLEMENT cpu3: cpu@101 { 64ec7e5a56SThomas Petazzoni device_type = "cpu"; 6531af04cdSRob Herring compatible = "arm,cortex-a72"; 66ec7e5a56SThomas Petazzoni reg = <0x101>; 67ec7e5a56SThomas Petazzoni enable-method = "psci"; 68fe7f7f22SMiquel Raynal #cooling-cells = <2>; 69c00bc383SGregory CLEMENT clocks = <&cpu_clk 1>; 70*760cabcdSGrzegorz Jaszczyk i-cache-size = <0xc000>; 71*760cabcdSGrzegorz Jaszczyk i-cache-line-size = <64>; 72*760cabcdSGrzegorz Jaszczyk i-cache-sets = <256>; 73*760cabcdSGrzegorz Jaszczyk d-cache-size = <0x8000>; 74*760cabcdSGrzegorz Jaszczyk d-cache-line-size = <64>; 75*760cabcdSGrzegorz Jaszczyk d-cache-sets = <256>; 76*760cabcdSGrzegorz Jaszczyk next-level-cache = <&l2_1>; 77*760cabcdSGrzegorz Jaszczyk }; 78*760cabcdSGrzegorz Jaszczyk 79*760cabcdSGrzegorz Jaszczyk l2_0: l2-cache0 { 80*760cabcdSGrzegorz Jaszczyk compatible = "cache"; 81*760cabcdSGrzegorz Jaszczyk cache-size = <0x80000>; 82*760cabcdSGrzegorz Jaszczyk cache-line-size = <64>; 83*760cabcdSGrzegorz Jaszczyk cache-sets = <512>; 84*760cabcdSGrzegorz Jaszczyk }; 85*760cabcdSGrzegorz Jaszczyk 86*760cabcdSGrzegorz Jaszczyk l2_1: l2-cache1 { 87*760cabcdSGrzegorz Jaszczyk compatible = "cache"; 88*760cabcdSGrzegorz Jaszczyk cache-size = <0x80000>; 89*760cabcdSGrzegorz Jaszczyk cache-line-size = <64>; 90*760cabcdSGrzegorz Jaszczyk cache-sets = <512>; 91ec7e5a56SThomas Petazzoni }; 92ec7e5a56SThomas Petazzoni }; 93ec7e5a56SThomas Petazzoni}; 94