1*bb61c536SShawn Guo// SPDX-License-Identifier: GPL-2.0 2*bb61c536SShawn Guo/* 3*bb61c536SShawn Guo * Pinctrl dts file for HiSilicon Poplar board 4*bb61c536SShawn Guo * 5*bb61c536SShawn Guo * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. 6*bb61c536SShawn Guo */ 7*bb61c536SShawn Guo 8*bb61c536SShawn Guo#include <dt-bindings/pinctrl/hisi.h> 9*bb61c536SShawn Guo 10*bb61c536SShawn Guo/* value, enable bits, disable bits, mask */ 11*bb61c536SShawn Guo#define PINCTRL_PULLDOWN(value, enable, disable, mask) \ 12*bb61c536SShawn Guo (value << 13) (enable << 13) (disable << 13) (mask << 13) 13*bb61c536SShawn Guo#define PINCTRL_PULLUP(value, enable, disable, mask) \ 14*bb61c536SShawn Guo (value << 12) (enable << 12) (disable << 12) (mask << 12) 15*bb61c536SShawn Guo#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) 16*bb61c536SShawn Guo#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) 17*bb61c536SShawn Guo 18*bb61c536SShawn Guo&pmx0 { 19*bb61c536SShawn Guo emmc_pins_1: emmc-pins-1 { 20*bb61c536SShawn Guo pinctrl-single,pins = < 21*bb61c536SShawn Guo 0x000 MUX_M2 22*bb61c536SShawn Guo 0x004 MUX_M2 23*bb61c536SShawn Guo 0x008 MUX_M2 24*bb61c536SShawn Guo 0x00c MUX_M2 25*bb61c536SShawn Guo 0x010 MUX_M2 26*bb61c536SShawn Guo 0x014 MUX_M2 27*bb61c536SShawn Guo 0x018 MUX_M2 28*bb61c536SShawn Guo 0x01c MUX_M2 29*bb61c536SShawn Guo 0x024 MUX_M2 30*bb61c536SShawn Guo >; 31*bb61c536SShawn Guo pinctrl-single,bias-pulldown = < 32*bb61c536SShawn Guo PINCTRL_PULLDOWN(0, 1, 0, 1) 33*bb61c536SShawn Guo >; 34*bb61c536SShawn Guo pinctrl-single,bias-pullup = < 35*bb61c536SShawn Guo PINCTRL_PULLUP(0, 1, 0, 1) 36*bb61c536SShawn Guo >; 37*bb61c536SShawn Guo pinctrl-single,slew-rate = < 38*bb61c536SShawn Guo PINCTRL_SLEW_RATE(1, 1) 39*bb61c536SShawn Guo >; 40*bb61c536SShawn Guo pinctrl-single,drive-strength = < 41*bb61c536SShawn Guo PINCTRL_DRV_STRENGTH(0xb, 0xf) 42*bb61c536SShawn Guo >; 43*bb61c536SShawn Guo }; 44*bb61c536SShawn Guo 45*bb61c536SShawn Guo emmc_pins_2: emmc-pins-2 { 46*bb61c536SShawn Guo pinctrl-single,pins = < 47*bb61c536SShawn Guo 0x028 MUX_M2 48*bb61c536SShawn Guo >; 49*bb61c536SShawn Guo pinctrl-single,bias-pulldown = < 50*bb61c536SShawn Guo PINCTRL_PULLDOWN(0, 1, 0, 1) 51*bb61c536SShawn Guo >; 52*bb61c536SShawn Guo pinctrl-single,bias-pullup = < 53*bb61c536SShawn Guo PINCTRL_PULLUP(0, 1, 0, 1) 54*bb61c536SShawn Guo >; 55*bb61c536SShawn Guo pinctrl-single,slew-rate = < 56*bb61c536SShawn Guo PINCTRL_SLEW_RATE(1, 1) 57*bb61c536SShawn Guo >; 58*bb61c536SShawn Guo pinctrl-single,drive-strength = < 59*bb61c536SShawn Guo PINCTRL_DRV_STRENGTH(0x9, 0xf) 60*bb61c536SShawn Guo >; 61*bb61c536SShawn Guo }; 62*bb61c536SShawn Guo 63*bb61c536SShawn Guo emmc_pins_3: emmc-pins-3 { 64*bb61c536SShawn Guo pinctrl-single,pins = < 65*bb61c536SShawn Guo 0x02c MUX_M2 66*bb61c536SShawn Guo >; 67*bb61c536SShawn Guo pinctrl-single,bias-pulldown = < 68*bb61c536SShawn Guo PINCTRL_PULLDOWN(0, 1, 0, 1) 69*bb61c536SShawn Guo >; 70*bb61c536SShawn Guo pinctrl-single,bias-pullup = < 71*bb61c536SShawn Guo PINCTRL_PULLUP(0, 1, 0, 1) 72*bb61c536SShawn Guo >; 73*bb61c536SShawn Guo pinctrl-single,slew-rate = < 74*bb61c536SShawn Guo PINCTRL_SLEW_RATE(1, 1) 75*bb61c536SShawn Guo >; 76*bb61c536SShawn Guo pinctrl-single,drive-strength = < 77*bb61c536SShawn Guo PINCTRL_DRV_STRENGTH(3, 3) 78*bb61c536SShawn Guo >; 79*bb61c536SShawn Guo }; 80*bb61c536SShawn Guo 81*bb61c536SShawn Guo emmc_pins_4: emmc-pins-4 { 82*bb61c536SShawn Guo pinctrl-single,pins = < 83*bb61c536SShawn Guo 0x030 MUX_M2 84*bb61c536SShawn Guo >; 85*bb61c536SShawn Guo pinctrl-single,bias-pulldown = < 86*bb61c536SShawn Guo PINCTRL_PULLDOWN(1, 1, 0, 1) 87*bb61c536SShawn Guo >; 88*bb61c536SShawn Guo pinctrl-single,bias-pullup = < 89*bb61c536SShawn Guo PINCTRL_PULLUP(0, 1, 0, 1) 90*bb61c536SShawn Guo >; 91*bb61c536SShawn Guo pinctrl-single,slew-rate = < 92*bb61c536SShawn Guo PINCTRL_SLEW_RATE(1, 1) 93*bb61c536SShawn Guo >; 94*bb61c536SShawn Guo pinctrl-single,drive-strength = < 95*bb61c536SShawn Guo PINCTRL_DRV_STRENGTH(3, 3) 96*bb61c536SShawn Guo >; 97*bb61c536SShawn Guo }; 98*bb61c536SShawn Guo}; 99