1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8ulp.dtsi" 9 10/ { 11 model = "NXP i.MX8ULP EVK"; 12 compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; 13 14 chosen { 15 stdout-path = &lpuart5; 16 }; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x0 0x80000000 0 0x80000000>; 21 }; 22 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 linux,cma { 29 compatible = "shared-dma-pool"; 30 reusable; 31 size = <0 0x28000000>; 32 linux,cma-default; 33 }; 34 }; 35 36 clock_ext_rmii: clock-ext-rmii { 37 compatible = "fixed-clock"; 38 clock-frequency = <50000000>; 39 clock-output-names = "ext_rmii_clk"; 40 #clock-cells = <0>; 41 }; 42 43 clock_ext_ts: clock-ext-ts { 44 compatible = "fixed-clock"; 45 /* External ts clock is 50MHZ from PHY on EVK board. */ 46 clock-frequency = <50000000>; 47 clock-output-names = "ext_ts_clk"; 48 #clock-cells = <0>; 49 }; 50}; 51 52&lpuart5 { 53 /* console */ 54 pinctrl-names = "default", "sleep"; 55 pinctrl-0 = <&pinctrl_lpuart5>; 56 pinctrl-1 = <&pinctrl_lpuart5>; 57 status = "okay"; 58}; 59 60&usdhc0 { 61 pinctrl-names = "default", "sleep"; 62 pinctrl-0 = <&pinctrl_usdhc0>; 63 pinctrl-1 = <&pinctrl_usdhc0>; 64 non-removable; 65 bus-width = <8>; 66 status = "okay"; 67}; 68 69&fec { 70 pinctrl-names = "default", "sleep"; 71 pinctrl-0 = <&pinctrl_enet>; 72 pinctrl-1 = <&pinctrl_enet>; 73 clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>, 74 <&pcc4 IMX8ULP_CLK_ENET>, 75 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>, 76 <&clock_ext_rmii>; 77 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; 78 assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>; 79 assigned-clock-parents = <&clock_ext_ts>; 80 phy-mode = "rmii"; 81 phy-handle = <ðphy>; 82 status = "okay"; 83 84 mdio { 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 ethphy: ethernet-phy@1 { 89 reg = <1>; 90 micrel,led-mode = <1>; 91 }; 92 }; 93}; 94 95&iomuxc1 { 96 pinctrl_enet: enetgrp { 97 fsl,pins = < 98 MX8ULP_PAD_PTE15__ENET0_MDC 0x43 99 MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 100 MX8ULP_PAD_PTE17__ENET0_RXER 0x43 101 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 102 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 103 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 104 MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 105 MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 106 MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 107 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 108 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 109 >; 110 }; 111 112 pinctrl_lpuart5: lpuart5grp { 113 fsl,pins = < 114 MX8ULP_PAD_PTF14__LPUART5_TX 0x3 115 MX8ULP_PAD_PTF15__LPUART5_RX 0x3 116 >; 117 }; 118 119 pinctrl_usdhc0: usdhc0grp { 120 fsl,pins = < 121 MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 122 MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 123 MX8ULP_PAD_PTD10__SDHC0_D0 0x43 124 MX8ULP_PAD_PTD9__SDHC0_D1 0x43 125 MX8ULP_PAD_PTD8__SDHC0_D2 0x43 126 MX8ULP_PAD_PTD7__SDHC0_D3 0x43 127 MX8ULP_PAD_PTD6__SDHC0_D4 0x43 128 MX8ULP_PAD_PTD5__SDHC0_D5 0x43 129 MX8ULP_PAD_PTD4__SDHC0_D6 0x43 130 MX8ULP_PAD_PTD3__SDHC0_D7 0x43 131 MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 132 >; 133 }; 134}; 135