xref: /openbmc/linux/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1510c527bSMarek Vasut// SPDX-License-Identifier: GPL-2.0+ OR MIT
2510c527bSMarek Vasut/*
3510c527bSMarek Vasut * Copyright 2021-2022 Marek Vasut <marex@denx.de>
4510c527bSMarek Vasut */
5510c527bSMarek Vasut
6510c527bSMarek Vasut/dts-v1/;
7510c527bSMarek Vasut
8510c527bSMarek Vasut#include "imx8mm-verdin.dtsi"
9510c527bSMarek Vasut
10510c527bSMarek Vasut/ {
11510c527bSMarek Vasut	model = "MENLO MX8MM EMBEDDED DEVICE";
12510c527bSMarek Vasut	compatible = "menlo,mx8menlo",
13*2314515eSMarek Vasut		     "toradex,verdin-imx8mm-nonwifi",
14510c527bSMarek Vasut		     "toradex,verdin-imx8mm",
15510c527bSMarek Vasut		     "fsl,imx8mm";
16510c527bSMarek Vasut
17510c527bSMarek Vasut	/delete-node/ gpio-keys;
18510c527bSMarek Vasut
19510c527bSMarek Vasut	leds {
20510c527bSMarek Vasut		compatible = "gpio-leds";
21510c527bSMarek Vasut		pinctrl-names = "default";
22510c527bSMarek Vasut		pinctrl-0 = <&pinctrl_led>;
23510c527bSMarek Vasut
2482cb8506SKrzysztof Kozlowski		led-1 {
25510c527bSMarek Vasut			label = "TestLed601";
26510c527bSMarek Vasut			gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
27510c527bSMarek Vasut			linux,default-trigger = "mmc0";
28510c527bSMarek Vasut		};
29510c527bSMarek Vasut
3082cb8506SKrzysztof Kozlowski		led-2 {
31510c527bSMarek Vasut			label = "TestLed602";
32510c527bSMarek Vasut			gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
33510c527bSMarek Vasut			linux,default-trigger = "heartbeat";
34510c527bSMarek Vasut		};
35510c527bSMarek Vasut	};
36510c527bSMarek Vasut
37510c527bSMarek Vasut	beeper {
38510c527bSMarek Vasut		compatible = "gpio-beeper";
39510c527bSMarek Vasut		pinctrl-names = "default";
40510c527bSMarek Vasut		pinctrl-0 = <&pinctrl_beeper>;
41510c527bSMarek Vasut		gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
42510c527bSMarek Vasut	};
43510c527bSMarek Vasut
44510c527bSMarek Vasut	/* Fixed clock dedicated to SPI CAN on carrier board */
45510c527bSMarek Vasut	clk_xtal20: clk-xtal20 {
46510c527bSMarek Vasut		compatible = "fixed-clock";
47510c527bSMarek Vasut		#clock-cells = <0>;
48510c527bSMarek Vasut		clock-frequency = <20000000>;
49510c527bSMarek Vasut	};
50510c527bSMarek Vasut};
51510c527bSMarek Vasut
52510c527bSMarek Vasut&ecspi1 {
53510c527bSMarek Vasut	#address-cells = <1>;
54510c527bSMarek Vasut	#size-cells = <0>;
55510c527bSMarek Vasut	pinctrl-names = "default";
56510c527bSMarek Vasut	pinctrl-0 = <&pinctrl_ecspi1>;
57510c527bSMarek Vasut	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
58510c527bSMarek Vasut	status = "okay";
59510c527bSMarek Vasut
60510c527bSMarek Vasut	/* CAN controller on the baseboard */
61510c527bSMarek Vasut	canfd: can@0 {
62510c527bSMarek Vasut		compatible = "microchip,mcp2518fd";
63510c527bSMarek Vasut		clocks = <&clk_xtal20>;
64510c527bSMarek Vasut		interrupt-parent = <&gpio1>;
65510c527bSMarek Vasut		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
66510c527bSMarek Vasut		reg = <0>;
67510c527bSMarek Vasut		spi-max-frequency = <2000000>;
68510c527bSMarek Vasut	};
69510c527bSMarek Vasut
70510c527bSMarek Vasut};
71510c527bSMarek Vasut
72510c527bSMarek Vasut&ecspi2 {
73510c527bSMarek Vasut	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
74510c527bSMarek Vasut	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
7513e4e43aSMarek Vasut	status = "okay";
7613e4e43aSMarek Vasut
7713e4e43aSMarek Vasut	spidev@0 {
7813e4e43aSMarek Vasut		compatible = "menlo,m53cpld";
7913e4e43aSMarek Vasut		reg = <0>;
8013e4e43aSMarek Vasut		spi-max-frequency = <25000000>;
8113e4e43aSMarek Vasut	};
8213e4e43aSMarek Vasut
8313e4e43aSMarek Vasut	spidev@1 {
8413e4e43aSMarek Vasut		compatible = "menlo,m53cpld";
8513e4e43aSMarek Vasut		reg = <1>;
8613e4e43aSMarek Vasut		spi-max-frequency = <25000000>;
8713e4e43aSMarek Vasut	};
8813e4e43aSMarek Vasut
89510c527bSMarek Vasut};
90510c527bSMarek Vasut
91510c527bSMarek Vasut&ethphy0 {
92510c527bSMarek Vasut	max-speed = <100>;
93510c527bSMarek Vasut};
94510c527bSMarek Vasut
95510c527bSMarek Vasut&fec1 {
96510c527bSMarek Vasut	status = "okay";
97510c527bSMarek Vasut};
98510c527bSMarek Vasut
99510c527bSMarek Vasut&flexspi {
100510c527bSMarek Vasut	status = "okay";
101510c527bSMarek Vasut
102510c527bSMarek Vasut	flash@0 {
103510c527bSMarek Vasut		reg = <0>;
104510c527bSMarek Vasut		#address-cells = <1>;
105510c527bSMarek Vasut		#size-cells = <1>;
106510c527bSMarek Vasut		compatible = "jedec,spi-nor";
107510c527bSMarek Vasut		spi-max-frequency = <66000000>;
108510c527bSMarek Vasut		spi-rx-bus-width = <4>;
109510c527bSMarek Vasut		spi-tx-bus-width = <4>;
110510c527bSMarek Vasut	};
111510c527bSMarek Vasut};
112510c527bSMarek Vasut
113510c527bSMarek Vasut&gpio1 {
114510c527bSMarek Vasut	gpio-line-names =
115510c527bSMarek Vasut		"", "", "", "",
116510c527bSMarek Vasut		"", "", "", "",
117510c527bSMarek Vasut		"", "", "", "",
118510c527bSMarek Vasut		"", "", "", "",
119510c527bSMarek Vasut		"", "", "", "",
120510c527bSMarek Vasut		"", "", "", "",
121510c527bSMarek Vasut		"", "", "", "",
122510c527bSMarek Vasut		"", "", "", "";
123510c527bSMarek Vasut};
124510c527bSMarek Vasut
125510c527bSMarek Vasut&gpio2 {
126510c527bSMarek Vasut	gpio-line-names =
127510c527bSMarek Vasut		"", "", "", "",
128510c527bSMarek Vasut		"", "", "", "",
129510c527bSMarek Vasut		"", "", "", "",
130510c527bSMarek Vasut		"", "", "", "",
131510c527bSMarek Vasut		"", "", "", "",
132510c527bSMarek Vasut		"", "", "", "",
133510c527bSMarek Vasut		"", "", "", "",
134510c527bSMarek Vasut		"", "", "", "";
135510c527bSMarek Vasut};
136510c527bSMarek Vasut
137510c527bSMarek Vasut&gpio3 {
138510c527bSMarek Vasut	gpio-line-names =
139510c527bSMarek Vasut		"", "", "", "",
140510c527bSMarek Vasut		"", "", "", "",
141510c527bSMarek Vasut		"", "", "", "",
142510c527bSMarek Vasut		"", "", "", "",
143510c527bSMarek Vasut		"", "", "", "",
144510c527bSMarek Vasut		"", "", "DISP_reset", "KBD_intI",
145510c527bSMarek Vasut		"", "", "", "",
146510c527bSMarek Vasut		"", "", "", "";
147510c527bSMarek Vasut};
148510c527bSMarek Vasut
149510c527bSMarek Vasut&gpio4 {
150510c527bSMarek Vasut	/*
151510c527bSMarek Vasut	 * CPLD_D[n] is ARM_CPLD[n] in schematic
152510c527bSMarek Vasut	 * CPLD_int is SA_INTERRUPT in schematic
153510c527bSMarek Vasut	 * CPLD_reset is RESET_SOFT in schematic
154510c527bSMarek Vasut	 */
155510c527bSMarek Vasut	gpio-line-names =
1568194a356SMarek Vasut		"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
1578194a356SMarek Vasut		"", "CPLD_D[7]", "", "",
1588194a356SMarek Vasut		"", "", "", "CPLD_D[5]",
1598194a356SMarek Vasut		"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
1608194a356SMarek Vasut		"CPLD_D[0]", "", "", "",
161510c527bSMarek Vasut		"", "", "", "",
162510c527bSMarek Vasut		"", "", "", "KBD_intK",
163510c527bSMarek Vasut		"", "", "", "";
164510c527bSMarek Vasut};
165510c527bSMarek Vasut
166510c527bSMarek Vasut&gpio5 {
167510c527bSMarek Vasut	gpio-line-names =
168510c527bSMarek Vasut		"", "", "", "",
169510c527bSMarek Vasut		"", "", "", "",
170510c527bSMarek Vasut		"", "", "", "",
171510c527bSMarek Vasut		"", "", "", "",
172510c527bSMarek Vasut		"", "", "", "",
173510c527bSMarek Vasut		"", "", "", "",
174510c527bSMarek Vasut		"", "", "", "",
175510c527bSMarek Vasut		"", "", "", "";
176510c527bSMarek Vasut};
177510c527bSMarek Vasut
178510c527bSMarek Vasut&gpio_expander_21 {
179510c527bSMarek Vasut	status = "okay";
180510c527bSMarek Vasut};
181510c527bSMarek Vasut
182510c527bSMarek Vasut&hwmon {
183510c527bSMarek Vasut	status = "okay";
184510c527bSMarek Vasut};
185510c527bSMarek Vasut
186510c527bSMarek Vasut&i2c3 {
187510c527bSMarek Vasut	status = "okay";
188510c527bSMarek Vasut};
189510c527bSMarek Vasut
190510c527bSMarek Vasut&i2c4 {
191510c527bSMarek Vasut	/* None of this is present on the SoM. */
192510c527bSMarek Vasut	/delete-node/ bridge@2c;
193510c527bSMarek Vasut	/delete-node/ hdmi@48;
194510c527bSMarek Vasut	/delete-node/ touch@4a;
195510c527bSMarek Vasut	/delete-node/ sensor@4f;
196510c527bSMarek Vasut	/delete-node/ eeprom@50;
197510c527bSMarek Vasut	/delete-node/ eeprom@57;
198510c527bSMarek Vasut};
199510c527bSMarek Vasut
200510c527bSMarek Vasut&iomuxc {
201510c527bSMarek Vasut	pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
202510c527bSMarek Vasut		    <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
203510c527bSMarek Vasut
204510c527bSMarek Vasut	pinctrl_beeper: beepergrp {
205510c527bSMarek Vasut		fsl,pins = <
206510c527bSMarek Vasut			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x1c4
207510c527bSMarek Vasut		>;
208510c527bSMarek Vasut	};
209510c527bSMarek Vasut
210510c527bSMarek Vasut	pinctrl_ecspi1: ecspi1grp {
211510c527bSMarek Vasut		fsl,pins = <
212510c527bSMarek Vasut			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x4
213510c527bSMarek Vasut			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x4
214510c527bSMarek Vasut			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x1c4
215510c527bSMarek Vasut			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x1c4
216510c527bSMarek Vasut		>;
217510c527bSMarek Vasut	};
218510c527bSMarek Vasut
219510c527bSMarek Vasut	pinctrl_led: ledgrp {
220510c527bSMarek Vasut		fsl,pins = <
221510c527bSMarek Vasut			MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18		0x1c4
222510c527bSMarek Vasut			MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10		0x1c4
223510c527bSMarek Vasut		>;
224510c527bSMarek Vasut	};
225510c527bSMarek Vasut
226510c527bSMarek Vasut	pinctrl_uart4_rts: uart4rtsgrp {
227510c527bSMarek Vasut		fsl,pins = <
228510c527bSMarek Vasut			/* SODIMM 222 */
229510c527bSMarek Vasut			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x184
230510c527bSMarek Vasut		>;
231510c527bSMarek Vasut	};
232510c527bSMarek Vasut};
233510c527bSMarek Vasut
234510c527bSMarek Vasut&pinctrl_gpio1 {
235510c527bSMarek Vasut	fsl,pins = <
236510c527bSMarek Vasut		/* SODIMM 206 */
237510c527bSMarek Vasut		MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4			0x1c4
238510c527bSMarek Vasut	>;
239510c527bSMarek Vasut};
240510c527bSMarek Vasut
241510c527bSMarek Vasut&pinctrl_gpio_hog1 {
242510c527bSMarek Vasut	fsl,pins = <
243510c527bSMarek Vasut		/* SODIMM 88 */
244510c527bSMarek Vasut		MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20			0x1c4
245510c527bSMarek Vasut		/* CPLD_int */
246510c527bSMarek Vasut		MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1				0x1c4
247510c527bSMarek Vasut		/* CPLD_reset */
248510c527bSMarek Vasut		MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2			0x1c4
249510c527bSMarek Vasut		/* SODIMM 94 */
250510c527bSMarek Vasut		MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3			0x1c4
251510c527bSMarek Vasut		/* SODIMM 96 */
252510c527bSMarek Vasut		MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4			0x1c4
253510c527bSMarek Vasut		/* CPLD_D[7] */
254f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5			0x184
255510c527bSMarek Vasut		/* CPLD_D[6] */
256f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0			0x184
257510c527bSMarek Vasut		/* CPLD_D[5] */
258f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11			0x184
259510c527bSMarek Vasut		/* CPLD_D[4] */
260f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12			0x184
261510c527bSMarek Vasut		/* CPLD_D[3] */
262f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13			0x184
263510c527bSMarek Vasut		/* CPLD_D[2] */
264f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14			0x184
265510c527bSMarek Vasut		/* CPLD_D[1] */
266f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15			0x184
267510c527bSMarek Vasut		/* CPLD_D[0] */
268f23f1a1eSMarek Vasut		MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16			0x184
269510c527bSMarek Vasut		/* KBD_intK */
270510c527bSMarek Vasut		MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27			0x1c4
271510c527bSMarek Vasut		/* DISP_reset */
272510c527bSMarek Vasut		MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22			0x1c4
273510c527bSMarek Vasut		/* KBD_intI */
274510c527bSMarek Vasut		MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23			0x1c4
275510c527bSMarek Vasut		/* SODIMM 46 */
276510c527bSMarek Vasut		MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24			0x1c4
277510c527bSMarek Vasut	>;
278510c527bSMarek Vasut};
279510c527bSMarek Vasut
280510c527bSMarek Vasut&pinctrl_uart1 {
281510c527bSMarek Vasut	fsl,pins = <
282510c527bSMarek Vasut		/* SODIMM 149 */
283510c527bSMarek Vasut		MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX			0x1c4
284510c527bSMarek Vasut		/* SODIMM 147 */
285510c527bSMarek Vasut		MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX			0x1c4
286510c527bSMarek Vasut		/* SODIMM 210 */
287510c527bSMarek Vasut		MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B			0x1c4
288510c527bSMarek Vasut		/* SODIMM 212 */
289510c527bSMarek Vasut		MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B			0x1c4
290510c527bSMarek Vasut	>;
291510c527bSMarek Vasut};
292510c527bSMarek Vasut
293510c527bSMarek Vasut&reg_usb_otg1_vbus {
294510c527bSMarek Vasut	/delete-property/ enable-active-high;
295510c527bSMarek Vasut	gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
296510c527bSMarek Vasut};
297510c527bSMarek Vasut
298510c527bSMarek Vasut&reg_usb_otg2_vbus {
299510c527bSMarek Vasut	/delete-property/ enable-active-high;
300510c527bSMarek Vasut	gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
301510c527bSMarek Vasut};
302510c527bSMarek Vasut
303510c527bSMarek Vasut&sai2 {
304510c527bSMarek Vasut	status = "disabled";
305510c527bSMarek Vasut};
306510c527bSMarek Vasut
307510c527bSMarek Vasut&uart1 {
308510c527bSMarek Vasut	uart-has-rtscts;
309510c527bSMarek Vasut	status = "okay";
310510c527bSMarek Vasut};
311510c527bSMarek Vasut
312510c527bSMarek Vasut&uart2 {
313510c527bSMarek Vasut	status = "okay";
314510c527bSMarek Vasut};
315510c527bSMarek Vasut
316510c527bSMarek Vasut&uart4 {
317510c527bSMarek Vasut	pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
318510c527bSMarek Vasut	linux,rs485-enabled-at-boot-time;
319510c527bSMarek Vasut	rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
320510c527bSMarek Vasut	status = "okay";
321510c527bSMarek Vasut};
322510c527bSMarek Vasut
323510c527bSMarek Vasut&usbotg1 {
324510c527bSMarek Vasut	dr_mode = "peripheral";
325510c527bSMarek Vasut	status = "okay";
326510c527bSMarek Vasut};
327510c527bSMarek Vasut
328510c527bSMarek Vasut&usbotg2 {
329510c527bSMarek Vasut	dr_mode = "host";
330510c527bSMarek Vasut	status = "okay";
331510c527bSMarek Vasut};
332510c527bSMarek Vasut
333510c527bSMarek Vasut&usdhc2 {
334510c527bSMarek Vasut	status = "okay";
335510c527bSMarek Vasut};
336