1*cbd3ef64SHimanshu Bhavani// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*cbd3ef64SHimanshu Bhavani/* 3*cbd3ef64SHimanshu Bhavani * Copyright 2023 Emtop Embedded Solutions 4*cbd3ef64SHimanshu Bhavani */ 5*cbd3ef64SHimanshu Bhavani 6*cbd3ef64SHimanshu Bhavani/dts-v1/; 7*cbd3ef64SHimanshu Bhavani 8*cbd3ef64SHimanshu Bhavani#include <dt-bindings/gpio/gpio.h> 9*cbd3ef64SHimanshu Bhavani#include <dt-bindings/leds/common.h> 10*cbd3ef64SHimanshu Bhavani#include <dt-bindings/usb/pd.h> 11*cbd3ef64SHimanshu Bhavani 12*cbd3ef64SHimanshu Bhavani#include "imx8mm.dtsi" 13*cbd3ef64SHimanshu Bhavani 14*cbd3ef64SHimanshu Bhavani/ { 15*cbd3ef64SHimanshu Bhavani model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM"; 16*cbd3ef64SHimanshu Bhavani compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm"; 17*cbd3ef64SHimanshu Bhavani 18*cbd3ef64SHimanshu Bhavani chosen { 19*cbd3ef64SHimanshu Bhavani stdout-path = &uart2; 20*cbd3ef64SHimanshu Bhavani }; 21*cbd3ef64SHimanshu Bhavani 22*cbd3ef64SHimanshu Bhavani leds { 23*cbd3ef64SHimanshu Bhavani compatible = "gpio-leds"; 24*cbd3ef64SHimanshu Bhavani pinctrl-names = "default"; 25*cbd3ef64SHimanshu Bhavani pinctrl-0 = <&pinctrl_gpio_led>; 26*cbd3ef64SHimanshu Bhavani 27*cbd3ef64SHimanshu Bhavani led-0 { 28*cbd3ef64SHimanshu Bhavani function = LED_FUNCTION_POWER; 29*cbd3ef64SHimanshu Bhavani gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 30*cbd3ef64SHimanshu Bhavani linux,default-trigger = "heartbeat"; 31*cbd3ef64SHimanshu Bhavani }; 32*cbd3ef64SHimanshu Bhavani }; 33*cbd3ef64SHimanshu Bhavani}; 34*cbd3ef64SHimanshu Bhavani 35*cbd3ef64SHimanshu Bhavani&A53_0 { 36*cbd3ef64SHimanshu Bhavani cpu-supply = <&buck2>; 37*cbd3ef64SHimanshu Bhavani}; 38*cbd3ef64SHimanshu Bhavani 39*cbd3ef64SHimanshu Bhavani&A53_1 { 40*cbd3ef64SHimanshu Bhavani cpu-supply = <&buck2>; 41*cbd3ef64SHimanshu Bhavani}; 42*cbd3ef64SHimanshu Bhavani 43*cbd3ef64SHimanshu Bhavani&A53_2 { 44*cbd3ef64SHimanshu Bhavani cpu-supply = <&buck2>; 45*cbd3ef64SHimanshu Bhavani}; 46*cbd3ef64SHimanshu Bhavani 47*cbd3ef64SHimanshu Bhavani&A53_3 { 48*cbd3ef64SHimanshu Bhavani cpu-supply = <&buck2>; 49*cbd3ef64SHimanshu Bhavani}; 50*cbd3ef64SHimanshu Bhavani 51*cbd3ef64SHimanshu Bhavani&i2c1 { 52*cbd3ef64SHimanshu Bhavani clock-frequency = <400000>; 53*cbd3ef64SHimanshu Bhavani pinctrl-names = "default"; 54*cbd3ef64SHimanshu Bhavani pinctrl-0 = <&pinctrl_i2c1>; 55*cbd3ef64SHimanshu Bhavani status = "okay"; 56*cbd3ef64SHimanshu Bhavani 57*cbd3ef64SHimanshu Bhavani pmic@25 { 58*cbd3ef64SHimanshu Bhavani compatible = "nxp,pca9450c"; 59*cbd3ef64SHimanshu Bhavani reg = <0x25>; 60*cbd3ef64SHimanshu Bhavani pinctrl-names = "default"; 61*cbd3ef64SHimanshu Bhavani pinctrl-0 = <&pinctrl_pmic>; 62*cbd3ef64SHimanshu Bhavani interrupt-parent = <&gpio1>; 63*cbd3ef64SHimanshu Bhavani interrupts = <3 IRQ_TYPE_EDGE_RISING>; 64*cbd3ef64SHimanshu Bhavani 65*cbd3ef64SHimanshu Bhavani regulators { 66*cbd3ef64SHimanshu Bhavani buck1: BUCK1 { 67*cbd3ef64SHimanshu Bhavani regulator-name = "BUCK1"; 68*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <800000>; 69*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <1000000>; 70*cbd3ef64SHimanshu Bhavani regulator-boot-on; 71*cbd3ef64SHimanshu Bhavani regulator-always-on; 72*cbd3ef64SHimanshu Bhavani regulator-ramp-delay = <3125>; 73*cbd3ef64SHimanshu Bhavani }; 74*cbd3ef64SHimanshu Bhavani 75*cbd3ef64SHimanshu Bhavani buck2: BUCK2 { 76*cbd3ef64SHimanshu Bhavani regulator-name = "BUCK2"; 77*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <800000>; 78*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <900000>; 79*cbd3ef64SHimanshu Bhavani regulator-boot-on; 80*cbd3ef64SHimanshu Bhavani regulator-always-on; 81*cbd3ef64SHimanshu Bhavani regulator-ramp-delay = <3125>; 82*cbd3ef64SHimanshu Bhavani }; 83*cbd3ef64SHimanshu Bhavani 84*cbd3ef64SHimanshu Bhavani buck3: BUCK3 { 85*cbd3ef64SHimanshu Bhavani regulator-name = "BUCK3"; 86*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <800000>; 87*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <1000000>; 88*cbd3ef64SHimanshu Bhavani regulator-boot-on; 89*cbd3ef64SHimanshu Bhavani regulator-always-on; 90*cbd3ef64SHimanshu Bhavani }; 91*cbd3ef64SHimanshu Bhavani 92*cbd3ef64SHimanshu Bhavani buck4: BUCK4 { 93*cbd3ef64SHimanshu Bhavani regulator-name = "BUCK4"; 94*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <3000000>; 95*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <3600000>; 96*cbd3ef64SHimanshu Bhavani regulator-boot-on; 97*cbd3ef64SHimanshu Bhavani regulator-always-on; 98*cbd3ef64SHimanshu Bhavani }; 99*cbd3ef64SHimanshu Bhavani 100*cbd3ef64SHimanshu Bhavani buck5: BUCK5 { 101*cbd3ef64SHimanshu Bhavani regulator-name = "BUCK5"; 102*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <1650000>; 103*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <1950000>; 104*cbd3ef64SHimanshu Bhavani regulator-boot-on; 105*cbd3ef64SHimanshu Bhavani regulator-always-on; 106*cbd3ef64SHimanshu Bhavani }; 107*cbd3ef64SHimanshu Bhavani 108*cbd3ef64SHimanshu Bhavani buck6: BUCK6 { 109*cbd3ef64SHimanshu Bhavani regulator-name = "BUCK6"; 110*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <1100000>; 111*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <1200000>; 112*cbd3ef64SHimanshu Bhavani regulator-boot-on; 113*cbd3ef64SHimanshu Bhavani regulator-always-on; 114*cbd3ef64SHimanshu Bhavani }; 115*cbd3ef64SHimanshu Bhavani 116*cbd3ef64SHimanshu Bhavani ldo1: LDO1 { 117*cbd3ef64SHimanshu Bhavani regulator-name = "LDO1"; 118*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <1650000>; 119*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <1950000>; 120*cbd3ef64SHimanshu Bhavani regulator-boot-on; 121*cbd3ef64SHimanshu Bhavani regulator-always-on; 122*cbd3ef64SHimanshu Bhavani }; 123*cbd3ef64SHimanshu Bhavani 124*cbd3ef64SHimanshu Bhavani ldo2: LDO2 { 125*cbd3ef64SHimanshu Bhavani regulator-name = "LDO2"; 126*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <800000>; 127*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <945000>; 128*cbd3ef64SHimanshu Bhavani regulator-boot-on; 129*cbd3ef64SHimanshu Bhavani regulator-always-on; 130*cbd3ef64SHimanshu Bhavani }; 131*cbd3ef64SHimanshu Bhavani 132*cbd3ef64SHimanshu Bhavani ldo3: LDO3 { 133*cbd3ef64SHimanshu Bhavani regulator-name = "LDO3"; 134*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <1710000>; 135*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <1890000>; 136*cbd3ef64SHimanshu Bhavani regulator-boot-on; 137*cbd3ef64SHimanshu Bhavani regulator-always-on; 138*cbd3ef64SHimanshu Bhavani }; 139*cbd3ef64SHimanshu Bhavani 140*cbd3ef64SHimanshu Bhavani ldo4: LDO4 { 141*cbd3ef64SHimanshu Bhavani regulator-name = "LDO4"; 142*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <810000>; 143*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <945000>; 144*cbd3ef64SHimanshu Bhavani regulator-boot-on; 145*cbd3ef64SHimanshu Bhavani regulator-always-on; 146*cbd3ef64SHimanshu Bhavani }; 147*cbd3ef64SHimanshu Bhavani 148*cbd3ef64SHimanshu Bhavani ldo5: LDO5 { 149*cbd3ef64SHimanshu Bhavani regulator-name = "LDO5"; 150*cbd3ef64SHimanshu Bhavani regulator-min-microvolt = <1650000>; 151*cbd3ef64SHimanshu Bhavani regulator-max-microvolt = <3600000>; 152*cbd3ef64SHimanshu Bhavani }; 153*cbd3ef64SHimanshu Bhavani }; 154*cbd3ef64SHimanshu Bhavani }; 155*cbd3ef64SHimanshu Bhavani}; 156*cbd3ef64SHimanshu Bhavani 157*cbd3ef64SHimanshu Bhavani&uart2 { 158*cbd3ef64SHimanshu Bhavani pinctrl-names = "default"; 159*cbd3ef64SHimanshu Bhavani pinctrl-0 = <&pinctrl_uart2>; 160*cbd3ef64SHimanshu Bhavani status = "okay"; 161*cbd3ef64SHimanshu Bhavani}; 162*cbd3ef64SHimanshu Bhavani 163*cbd3ef64SHimanshu Bhavani&usdhc3 { 164*cbd3ef64SHimanshu Bhavani pinctrl-names = "default", "state_100mhz", "state_200mhz"; 165*cbd3ef64SHimanshu Bhavani pinctrl-0 = <&pinctrl_usdhc3>; 166*cbd3ef64SHimanshu Bhavani pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 167*cbd3ef64SHimanshu Bhavani pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 168*cbd3ef64SHimanshu Bhavani bus-width = <8>; 169*cbd3ef64SHimanshu Bhavani non-removable; 170*cbd3ef64SHimanshu Bhavani status = "okay"; 171*cbd3ef64SHimanshu Bhavani}; 172*cbd3ef64SHimanshu Bhavani 173*cbd3ef64SHimanshu Bhavani&wdog1 { 174*cbd3ef64SHimanshu Bhavani pinctrl-names = "default"; 175*cbd3ef64SHimanshu Bhavani pinctrl-0 = <&pinctrl_wdog>; 176*cbd3ef64SHimanshu Bhavani fsl,ext-reset-output; 177*cbd3ef64SHimanshu Bhavani status = "okay"; 178*cbd3ef64SHimanshu Bhavani}; 179*cbd3ef64SHimanshu Bhavani 180*cbd3ef64SHimanshu Bhavani&iomuxc { 181*cbd3ef64SHimanshu Bhavani pinctrl_gpio_led: emtop-gpio-led-grp { 182*cbd3ef64SHimanshu Bhavani fsl,pins = < 183*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 184*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 185*cbd3ef64SHimanshu Bhavani >; 186*cbd3ef64SHimanshu Bhavani }; 187*cbd3ef64SHimanshu Bhavani 188*cbd3ef64SHimanshu Bhavani pinctrl_i2c1: emtop-i2c1-grp { 189*cbd3ef64SHimanshu Bhavani fsl,pins = < 190*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 191*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 192*cbd3ef64SHimanshu Bhavani >; 193*cbd3ef64SHimanshu Bhavani }; 194*cbd3ef64SHimanshu Bhavani 195*cbd3ef64SHimanshu Bhavani pinctrl_pmic: emtop-pmic-grp { 196*cbd3ef64SHimanshu Bhavani fsl,pins = < 197*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 198*cbd3ef64SHimanshu Bhavani >; 199*cbd3ef64SHimanshu Bhavani }; 200*cbd3ef64SHimanshu Bhavani 201*cbd3ef64SHimanshu Bhavani pinctrl_uart2: emtop-uart2-grp { 202*cbd3ef64SHimanshu Bhavani fsl,pins = < 203*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 204*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 205*cbd3ef64SHimanshu Bhavani >; 206*cbd3ef64SHimanshu Bhavani }; 207*cbd3ef64SHimanshu Bhavani 208*cbd3ef64SHimanshu Bhavani pinctrl_usdhc3: emtop-usdhc3-grp { 209*cbd3ef64SHimanshu Bhavani fsl,pins = < 210*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 211*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 212*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 213*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 214*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 215*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 216*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 217*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 218*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 219*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 220*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 221*cbd3ef64SHimanshu Bhavani >; 222*cbd3ef64SHimanshu Bhavani }; 223*cbd3ef64SHimanshu Bhavani 224*cbd3ef64SHimanshu Bhavani pinctrl_usdhc3_100mhz: emtop-usdhc3-100mhz-grp { 225*cbd3ef64SHimanshu Bhavani fsl,pins = < 226*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 227*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 228*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 229*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 230*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 231*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 232*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 233*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 234*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 235*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 236*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 237*cbd3ef64SHimanshu Bhavani >; 238*cbd3ef64SHimanshu Bhavani }; 239*cbd3ef64SHimanshu Bhavani 240*cbd3ef64SHimanshu Bhavani pinctrl_usdhc3_200mhz: emtop-usdhc3-200mhz-grp { 241*cbd3ef64SHimanshu Bhavani fsl,pins = < 242*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 243*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 244*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 245*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 246*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 247*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 248*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 249*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 250*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 251*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 252*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 253*cbd3ef64SHimanshu Bhavani >; 254*cbd3ef64SHimanshu Bhavani }; 255*cbd3ef64SHimanshu Bhavani 256*cbd3ef64SHimanshu Bhavani pinctrl_wdog: emtop-wdog-grp { 257*cbd3ef64SHimanshu Bhavani fsl,pins = < 258*cbd3ef64SHimanshu Bhavani MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 259*cbd3ef64SHimanshu Bhavani >; 260*cbd3ef64SHimanshu Bhavani }; 261*cbd3ef64SHimanshu Bhavani}; 262