1*35f4e9d7SDong Aisheng// SPDX-License-Identifier: GPL-2.0+ 2*35f4e9d7SDong Aisheng/* 3*35f4e9d7SDong Aisheng * Copyright 2018-2019 NXP 4*35f4e9d7SDong Aisheng * Dong Aisheng <aisheng.dong@nxp.com> 5*35f4e9d7SDong Aisheng */ 6*35f4e9d7SDong Aisheng 7*35f4e9d7SDong Aisheng#include <dt-bindings/clock/imx8-lpcg.h> 8*35f4e9d7SDong Aisheng#include <dt-bindings/firmware/imx/rsrc.h> 9*35f4e9d7SDong Aisheng 10*35f4e9d7SDong Aishengaudio_subsys: bus@59000000 { 11*35f4e9d7SDong Aisheng compatible = "simple-bus"; 12*35f4e9d7SDong Aisheng #address-cells = <1>; 13*35f4e9d7SDong Aisheng #size-cells = <1>; 14*35f4e9d7SDong Aisheng ranges = <0x59000000 0x0 0x59000000 0x1000000>; 15*35f4e9d7SDong Aisheng 16*35f4e9d7SDong Aisheng audio_ipg_clk: clock-audio-ipg { 17*35f4e9d7SDong Aisheng compatible = "fixed-clock"; 18*35f4e9d7SDong Aisheng #clock-cells = <0>; 19*35f4e9d7SDong Aisheng clock-frequency = <120000000>; 20*35f4e9d7SDong Aisheng clock-output-names = "audio_ipg_clk"; 21*35f4e9d7SDong Aisheng }; 22*35f4e9d7SDong Aisheng 23*35f4e9d7SDong Aisheng dsp_lpcg: clock-controller@59580000 { 24*35f4e9d7SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 25*35f4e9d7SDong Aisheng reg = <0x59580000 0x10000>; 26*35f4e9d7SDong Aisheng #clock-cells = <1>; 27*35f4e9d7SDong Aisheng clocks = <&audio_ipg_clk>, 28*35f4e9d7SDong Aisheng <&audio_ipg_clk>, 29*35f4e9d7SDong Aisheng <&audio_ipg_clk>; 30*35f4e9d7SDong Aisheng clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 31*35f4e9d7SDong Aisheng <IMX_LPCG_CLK_7>; 32*35f4e9d7SDong Aisheng clock-output-names = "dsp_lpcg_adb_clk", 33*35f4e9d7SDong Aisheng "dsp_lpcg_ipg_clk", 34*35f4e9d7SDong Aisheng "dsp_lpcg_core_clk"; 35*35f4e9d7SDong Aisheng power-domains = <&pd IMX_SC_R_DSP>; 36*35f4e9d7SDong Aisheng }; 37*35f4e9d7SDong Aisheng 38*35f4e9d7SDong Aisheng dsp_ram_lpcg: clock-controller@59590000 { 39*35f4e9d7SDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 40*35f4e9d7SDong Aisheng reg = <0x59590000 0x10000>; 41*35f4e9d7SDong Aisheng #clock-cells = <1>; 42*35f4e9d7SDong Aisheng clocks = <&audio_ipg_clk>; 43*35f4e9d7SDong Aisheng clock-indices = <IMX_LPCG_CLK_4>; 44*35f4e9d7SDong Aisheng clock-output-names = "dsp_ram_lpcg_ipg_clk"; 45*35f4e9d7SDong Aisheng power-domains = <&pd IMX_SC_R_DSP_RAM>; 46*35f4e9d7SDong Aisheng }; 47*35f4e9d7SDong Aisheng 48*35f4e9d7SDong Aisheng dsp: dsp@596e8000 { 49*35f4e9d7SDong Aisheng compatible = "fsl,imx8qxp-dsp"; 50*35f4e9d7SDong Aisheng reg = <0x596e8000 0x88000>; 51*35f4e9d7SDong Aisheng clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, 52*35f4e9d7SDong Aisheng <&dsp_ram_lpcg IMX_LPCG_CLK_4>, 53*35f4e9d7SDong Aisheng <&dsp_lpcg IMX_LPCG_CLK_7>; 54*35f4e9d7SDong Aisheng clock-names = "ipg", "ocram", "core"; 55*35f4e9d7SDong Aisheng power-domains = <&pd IMX_SC_R_MU_13A>, 56*35f4e9d7SDong Aisheng <&pd IMX_SC_R_MU_13B>, 57*35f4e9d7SDong Aisheng <&pd IMX_SC_R_DSP>, 58*35f4e9d7SDong Aisheng <&pd IMX_SC_R_DSP_RAM>; 59*35f4e9d7SDong Aisheng mbox-names = "txdb0", "txdb1", 60*35f4e9d7SDong Aisheng "rxdb0", "rxdb1"; 61*35f4e9d7SDong Aisheng mboxes = <&lsio_mu13 2 0>, 62*35f4e9d7SDong Aisheng <&lsio_mu13 2 1>, 63*35f4e9d7SDong Aisheng <&lsio_mu13 3 0>, 64*35f4e9d7SDong Aisheng <&lsio_mu13 3 1>; 65*35f4e9d7SDong Aisheng memory-region = <&dsp_reserved>; 66*35f4e9d7SDong Aisheng status = "disabled"; 67*35f4e9d7SDong Aisheng }; 68*35f4e9d7SDong Aisheng}; 69