1*c083131cSMarcel Ziswiler// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*c083131cSMarcel Ziswiler/* 3*c083131cSMarcel Ziswiler * Copyright 2022 Toradex 4*c083131cSMarcel Ziswiler */ 5*c083131cSMarcel Ziswiler 6*c083131cSMarcel Ziswiler/ { 7*c083131cSMarcel Ziswiler aliases { 8*c083131cSMarcel Ziswiler rtc0 = &rtc_i2c; 9*c083131cSMarcel Ziswiler rtc1 = &rtc; 10*c083131cSMarcel Ziswiler }; 11*c083131cSMarcel Ziswiler 12*c083131cSMarcel Ziswiler reg_usb_host_vbus: regulator-usb-host-vbus { 13*c083131cSMarcel Ziswiler regulator-name = "VCC USBH2(ABCD) / USBH(3|4)"; 14*c083131cSMarcel Ziswiler }; 15*c083131cSMarcel Ziswiler}; 16*c083131cSMarcel Ziswiler 17*c083131cSMarcel Ziswiler&adc0 { 18*c083131cSMarcel Ziswiler status = "okay"; 19*c083131cSMarcel Ziswiler}; 20*c083131cSMarcel Ziswiler 21*c083131cSMarcel Ziswiler&adc1 { 22*c083131cSMarcel Ziswiler status = "okay"; 23*c083131cSMarcel Ziswiler}; 24*c083131cSMarcel Ziswiler 25*c083131cSMarcel Ziswiler/* TODO: Audio Mixer */ 26*c083131cSMarcel Ziswiler 27*c083131cSMarcel Ziswiler/* TODO: Asynchronous Sample Rate Converter (ASRC) */ 28*c083131cSMarcel Ziswiler 29*c083131cSMarcel Ziswiler/* TODO: Display Controller */ 30*c083131cSMarcel Ziswiler 31*c083131cSMarcel Ziswiler/* TODO: DPU */ 32*c083131cSMarcel Ziswiler 33*c083131cSMarcel Ziswiler/* Apalis ETH1 */ 34*c083131cSMarcel Ziswiler&fec1 { 35*c083131cSMarcel Ziswiler status = "okay"; 36*c083131cSMarcel Ziswiler}; 37*c083131cSMarcel Ziswiler 38*c083131cSMarcel Ziswiler/* Apalis CAN1 */ 39*c083131cSMarcel Ziswiler&flexcan1 { 40*c083131cSMarcel Ziswiler status = "okay"; 41*c083131cSMarcel Ziswiler}; 42*c083131cSMarcel Ziswiler 43*c083131cSMarcel Ziswiler/* Apalis CAN2 */ 44*c083131cSMarcel Ziswiler&flexcan2 { 45*c083131cSMarcel Ziswiler status = "okay"; 46*c083131cSMarcel Ziswiler}; 47*c083131cSMarcel Ziswiler 48*c083131cSMarcel Ziswiler/* TODO: GPU */ 49*c083131cSMarcel Ziswiler 50*c083131cSMarcel Ziswiler/* Apalis I2C1 */ 51*c083131cSMarcel Ziswiler&i2c2 { 52*c083131cSMarcel Ziswiler status = "okay"; 53*c083131cSMarcel Ziswiler 54*c083131cSMarcel Ziswiler /* M41T0M6 real time clock on carrier board */ 55*c083131cSMarcel Ziswiler rtc_i2c: rtc@68 { 56*c083131cSMarcel Ziswiler status = "okay"; 57*c083131cSMarcel Ziswiler }; 58*c083131cSMarcel Ziswiler}; 59*c083131cSMarcel Ziswiler 60*c083131cSMarcel Ziswiler/* Apalis I2C3 (CAM) */ 61*c083131cSMarcel Ziswiler&i2c3 { 62*c083131cSMarcel Ziswiler status = "okay"; 63*c083131cSMarcel Ziswiler}; 64*c083131cSMarcel Ziswiler 65*c083131cSMarcel Ziswiler/* Apalis SPI1 */ 66*c083131cSMarcel Ziswiler&lpspi0 { 67*c083131cSMarcel Ziswiler status = "okay"; 68*c083131cSMarcel Ziswiler}; 69*c083131cSMarcel Ziswiler 70*c083131cSMarcel Ziswiler/* Apalis SPI2 */ 71*c083131cSMarcel Ziswiler&lpspi2 { 72*c083131cSMarcel Ziswiler status = "okay"; 73*c083131cSMarcel Ziswiler}; 74*c083131cSMarcel Ziswiler 75*c083131cSMarcel Ziswiler/* Apalis UART3 */ 76*c083131cSMarcel Ziswiler&lpuart0 { 77*c083131cSMarcel Ziswiler status = "okay"; 78*c083131cSMarcel Ziswiler}; 79*c083131cSMarcel Ziswiler 80*c083131cSMarcel Ziswiler/* Apalis UART1 */ 81*c083131cSMarcel Ziswiler&lpuart1 { 82*c083131cSMarcel Ziswiler status = "okay"; 83*c083131cSMarcel Ziswiler}; 84*c083131cSMarcel Ziswiler 85*c083131cSMarcel Ziswiler/* Apalis UART4 */ 86*c083131cSMarcel Ziswiler&lpuart2 { 87*c083131cSMarcel Ziswiler status = "okay"; 88*c083131cSMarcel Ziswiler}; 89*c083131cSMarcel Ziswiler 90*c083131cSMarcel Ziswiler/* Apalis UART2 */ 91*c083131cSMarcel Ziswiler&lpuart3 { 92*c083131cSMarcel Ziswiler status = "okay"; 93*c083131cSMarcel Ziswiler}; 94*c083131cSMarcel Ziswiler 95*c083131cSMarcel Ziswiler/* Apalis PWM3, MXM3 pin 6 */ 96*c083131cSMarcel Ziswiler&lsio_pwm0 { 97*c083131cSMarcel Ziswiler status = "okay"; 98*c083131cSMarcel Ziswiler}; 99*c083131cSMarcel Ziswiler 100*c083131cSMarcel Ziswiler/* Apalis PWM4, MXM3 pin 8 */ 101*c083131cSMarcel Ziswiler&lsio_pwm1 { 102*c083131cSMarcel Ziswiler status = "okay"; 103*c083131cSMarcel Ziswiler}; 104*c083131cSMarcel Ziswiler 105*c083131cSMarcel Ziswiler/* Apalis PWM1, MXM3 pin 2 */ 106*c083131cSMarcel Ziswiler&lsio_pwm2 { 107*c083131cSMarcel Ziswiler status = "okay"; 108*c083131cSMarcel Ziswiler}; 109*c083131cSMarcel Ziswiler 110*c083131cSMarcel Ziswiler/* Apalis PWM2, MXM3 pin 4 */ 111*c083131cSMarcel Ziswiler&lsio_pwm3 { 112*c083131cSMarcel Ziswiler status = "okay"; 113*c083131cSMarcel Ziswiler}; 114*c083131cSMarcel Ziswiler 115*c083131cSMarcel Ziswiler/* TODO: Apalis PCIE1 */ 116*c083131cSMarcel Ziswiler 117*c083131cSMarcel Ziswiler/* TODO: Apalis BKL1_PWM */ 118*c083131cSMarcel Ziswiler 119*c083131cSMarcel Ziswiler/* TODO: Apalis DAP1 */ 120*c083131cSMarcel Ziswiler 121*c083131cSMarcel Ziswiler/* TODO: Apalis Analogue Audio */ 122*c083131cSMarcel Ziswiler 123*c083131cSMarcel Ziswiler/* TODO: Apalis SATA1 */ 124*c083131cSMarcel Ziswiler 125*c083131cSMarcel Ziswiler/* TODO: Apalis SPDIF1 */ 126*c083131cSMarcel Ziswiler 127*c083131cSMarcel Ziswiler/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ 128*c083131cSMarcel Ziswiler 129*c083131cSMarcel Ziswiler/* Apalis USBO1 */ 130*c083131cSMarcel Ziswiler&usbotg1 { 131*c083131cSMarcel Ziswiler status = "okay"; 132*c083131cSMarcel Ziswiler}; 133*c083131cSMarcel Ziswiler 134*c083131cSMarcel Ziswiler/* TODO: Apalis USBH4 SuperSpeed */ 135*c083131cSMarcel Ziswiler 136*c083131cSMarcel Ziswiler/* Apalis MMC1 */ 137*c083131cSMarcel Ziswiler&usdhc2 { 138*c083131cSMarcel Ziswiler status = "okay"; 139*c083131cSMarcel Ziswiler}; 140*c083131cSMarcel Ziswiler 141*c083131cSMarcel Ziswiler/* Apalis SD1 */ 142*c083131cSMarcel Ziswiler&usdhc3 { 143*c083131cSMarcel Ziswiler status = "okay"; 144*c083131cSMarcel Ziswiler}; 145