xref: /openbmc/linux/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi (revision c900529f3d9161bfde5cca0754f83b4d3c3e0220)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree file for Freescale LS2080A QDS Board.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 */

/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
&dpmac9 {
	phy-handle = <&mdio0_phy12>;
	phy-connection-type = "sgmii";
};

&dpmac10 {
	phy-handle = <&mdio0_phy13>;
	phy-connection-type = "sgmii";
};

&dpmac11 {
	phy-handle = <&mdio0_phy14>;
	phy-connection-type = "sgmii";
};

&dpmac12 {
	phy-handle = <&mdio0_phy15>;
	phy-connection-type = "sgmii";
};

&esdhc {
	mmc-hs200-1_8v;
	status = "okay";
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	ranges = <0x0 0x0 0x5 0x80000000 0x08000000
		  0x2 0x0 0x5 0x30000000 0x00010000
		  0x3 0x0 0x5 0x20000000 0x00010000>;

	nor@0,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@2,0 {
	     compatible = "fsl,ifc-nand";
	     reg = <0x2 0x0 0x10000>;
	};

	boardctrl: board-control@3,0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,ls208xaqds-fpga", "fsl,fpga-qixis", "simple-mfd";
		reg = <3 0 0x1000>;
		ranges = <0 3 0 0x1000>;

		mdio-mux-emi1@54 {
			compatible = "mdio-mux-mmioreg", "mdio-mux";
			mdio-parent-bus = <&emdio1>;
			reg = <0x54 1>;		/* BRDCFG4 */
			mux-mask = <0xe0>;	/* EMI1_MDIO */
			#address-cells = <1>;
			#size-cells = <0>;

			/* Child MDIO buses, one for each riser card:
			 * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
			 * VSC8234 PHYs on the riser cards.
			 */
			mdio_mux3: mdio@60 {
				reg = <0x60>;
				#address-cells = <1>;
				#size-cells = <0>;

				mdio0_phy12: mdio-phy0@1c {
					reg = <0x1c>;
				};

				mdio0_phy13: mdio-phy1@1d {
					reg = <0x1d>;
				};

				mdio0_phy14: mdio-phy2@1e {
					reg = <0x1e>;
				};

				mdio0_phy15: mdio-phy3@1f {
					reg = <0x1f>;
				};
			};
		};
	};
};

&i2c0 {
	status = "okay";
	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;
		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x00>;
			rtc@68 {
				compatible = "dallas,ds3232";
				reg = <0x68>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x02>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <500>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			adt7481@4c {
				compatible = "adi,adt7461";
				reg = <0x4c>;
			};
		};
	};
};

&i2c1 {
	status = "disabled";
};

&i2c2 {
	status = "disabled";
};

&i2c3 {
	status = "disabled";
};

&dspi {
	status = "okay";
	dflash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <3000000>;
		reg = <0>;
	};
	dflash1: flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <3000000>;
		reg = <1>;
	};
	dflash2: flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <3000000>;
		reg = <2>;
	};
};

&qspi {
	status = "okay";
	flash0: flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <0>;
	};
	flash2: flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p80";
		spi-max-frequency = <20000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <2>;
	};
};

&sata0 {
	status = "okay";
};

&sata1 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};