1*3d501682SKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0 */ 2*3d501682SKrzysztof Kozlowski /* 3*3d501682SKrzysztof Kozlowski * Samsung Exynos DTS pinctrl constants 4*3d501682SKrzysztof Kozlowski * 5*3d501682SKrzysztof Kozlowski * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6*3d501682SKrzysztof Kozlowski * http://www.samsung.com 7*3d501682SKrzysztof Kozlowski * Copyright (c) 2022 Linaro Ltd 8*3d501682SKrzysztof Kozlowski * Author: Krzysztof Kozlowski <krzk@kernel.org> 9*3d501682SKrzysztof Kozlowski */ 10*3d501682SKrzysztof Kozlowski 11*3d501682SKrzysztof Kozlowski #ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ 12*3d501682SKrzysztof Kozlowski #define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ 13*3d501682SKrzysztof Kozlowski 14*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_PULL_NONE 0 15*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_PULL_DOWN 1 16*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_PULL_UP 3 17*3d501682SKrzysztof Kozlowski 18*3d501682SKrzysztof Kozlowski /* Pin function in power down mode */ 19*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_PDN_OUT0 0 20*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_PDN_OUT1 1 21*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_PDN_INPUT 2 22*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_PDN_PREV 3 23*3d501682SKrzysztof Kozlowski 24*3d501682SKrzysztof Kozlowski /* 25*3d501682SKrzysztof Kozlowski * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850 26*3d501682SKrzysztof Kozlowski * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1) 27*3d501682SKrzysztof Kozlowski */ 28*3d501682SKrzysztof Kozlowski #define EXYNOS5420_PIN_DRV_LV1 0 29*3d501682SKrzysztof Kozlowski #define EXYNOS5420_PIN_DRV_LV2 1 30*3d501682SKrzysztof Kozlowski #define EXYNOS5420_PIN_DRV_LV3 2 31*3d501682SKrzysztof Kozlowski #define EXYNOS5420_PIN_DRV_LV4 3 32*3d501682SKrzysztof Kozlowski 33*3d501682SKrzysztof Kozlowski /* Drive strengths for Exynos5433 */ 34*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_FAST_SR1 0 35*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_FAST_SR2 1 36*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_FAST_SR3 2 37*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_FAST_SR4 3 38*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_FAST_SR5 4 39*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_FAST_SR6 5 40*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_SLOW_SR1 8 41*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_SLOW_SR2 9 42*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa 43*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb 44*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc 45*3d501682SKrzysztof Kozlowski #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf 46*3d501682SKrzysztof Kozlowski 47*3d501682SKrzysztof Kozlowski /* Drive strengths for Exynos7 (except FSYS1) */ 48*3d501682SKrzysztof Kozlowski #define EXYNOS7_PIN_DRV_LV1 0 49*3d501682SKrzysztof Kozlowski #define EXYNOS7_PIN_DRV_LV2 2 50*3d501682SKrzysztof Kozlowski #define EXYNOS7_PIN_DRV_LV3 1 51*3d501682SKrzysztof Kozlowski #define EXYNOS7_PIN_DRV_LV4 3 52*3d501682SKrzysztof Kozlowski 53*3d501682SKrzysztof Kozlowski /* Drive strengths for Exynos7 FSYS1 block */ 54*3d501682SKrzysztof Kozlowski #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 55*3d501682SKrzysztof Kozlowski #define EXYNOS7_FSYS1_PIN_DRV_LV2 4 56*3d501682SKrzysztof Kozlowski #define EXYNOS7_FSYS1_PIN_DRV_LV3 2 57*3d501682SKrzysztof Kozlowski #define EXYNOS7_FSYS1_PIN_DRV_LV4 6 58*3d501682SKrzysztof Kozlowski #define EXYNOS7_FSYS1_PIN_DRV_LV5 1 59*3d501682SKrzysztof Kozlowski #define EXYNOS7_FSYS1_PIN_DRV_LV6 5 60*3d501682SKrzysztof Kozlowski 61*3d501682SKrzysztof Kozlowski /* Drive strengths for Exynos850 GPIO_HSI block */ 62*3d501682SKrzysztof Kozlowski #define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ 63*3d501682SKrzysztof Kozlowski #define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ 64*3d501682SKrzysztof Kozlowski #define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ 65*3d501682SKrzysztof Kozlowski #define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ 66*3d501682SKrzysztof Kozlowski #define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ 67*3d501682SKrzysztof Kozlowski #define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ 68*3d501682SKrzysztof Kozlowski 69*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_INPUT 0 70*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_OUTPUT 1 71*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_2 2 72*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_3 3 73*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_4 4 74*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_5 5 75*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_6 6 76*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_EINT 0xf 77*3d501682SKrzysztof Kozlowski #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT 78*3d501682SKrzysztof Kozlowski 79*3d501682SKrzysztof Kozlowski #endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */ 80