1*b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 241904360SSuravee Suthikulpanit/* 341904360SSuravee Suthikulpanit * DTS file for AMD Seattle Clocks 441904360SSuravee Suthikulpanit * 541904360SSuravee Suthikulpanit * Copyright (C) 2014 Advanced Micro Devices, Inc. 641904360SSuravee Suthikulpanit */ 741904360SSuravee Suthikulpanit 841904360SSuravee Suthikulpanit adl3clk_100mhz: clk100mhz_0 { 941904360SSuravee Suthikulpanit compatible = "fixed-clock"; 1041904360SSuravee Suthikulpanit #clock-cells = <0>; 1141904360SSuravee Suthikulpanit clock-frequency = <100000000>; 1241904360SSuravee Suthikulpanit clock-output-names = "adl3clk_100mhz"; 1341904360SSuravee Suthikulpanit }; 1441904360SSuravee Suthikulpanit 1541904360SSuravee Suthikulpanit ccpclk_375mhz: clk375mhz { 1641904360SSuravee Suthikulpanit compatible = "fixed-clock"; 1741904360SSuravee Suthikulpanit #clock-cells = <0>; 1841904360SSuravee Suthikulpanit clock-frequency = <375000000>; 1941904360SSuravee Suthikulpanit clock-output-names = "ccpclk_375mhz"; 2041904360SSuravee Suthikulpanit }; 2141904360SSuravee Suthikulpanit 2241904360SSuravee Suthikulpanit sataclk_333mhz: clk333mhz { 2341904360SSuravee Suthikulpanit compatible = "fixed-clock"; 2441904360SSuravee Suthikulpanit #clock-cells = <0>; 2541904360SSuravee Suthikulpanit clock-frequency = <333000000>; 2641904360SSuravee Suthikulpanit clock-output-names = "sataclk_333mhz"; 2741904360SSuravee Suthikulpanit }; 2841904360SSuravee Suthikulpanit 2941904360SSuravee Suthikulpanit pcieclk_500mhz: clk500mhz_0 { 3041904360SSuravee Suthikulpanit compatible = "fixed-clock"; 3141904360SSuravee Suthikulpanit #clock-cells = <0>; 3241904360SSuravee Suthikulpanit clock-frequency = <500000000>; 3341904360SSuravee Suthikulpanit clock-output-names = "pcieclk_500mhz"; 3441904360SSuravee Suthikulpanit }; 3541904360SSuravee Suthikulpanit 3641904360SSuravee Suthikulpanit dmaclk_500mhz: clk500mhz_1 { 3741904360SSuravee Suthikulpanit compatible = "fixed-clock"; 3841904360SSuravee Suthikulpanit #clock-cells = <0>; 3941904360SSuravee Suthikulpanit clock-frequency = <500000000>; 4041904360SSuravee Suthikulpanit clock-output-names = "dmaclk_500mhz"; 4141904360SSuravee Suthikulpanit }; 4241904360SSuravee Suthikulpanit 4341904360SSuravee Suthikulpanit miscclk_250mhz: clk250mhz_4 { 4441904360SSuravee Suthikulpanit compatible = "fixed-clock"; 4541904360SSuravee Suthikulpanit #clock-cells = <0>; 4641904360SSuravee Suthikulpanit clock-frequency = <250000000>; 4741904360SSuravee Suthikulpanit clock-output-names = "miscclk_250mhz"; 4841904360SSuravee Suthikulpanit }; 4941904360SSuravee Suthikulpanit 5041904360SSuravee Suthikulpanit uartspiclk_100mhz: clk100mhz_1 { 5141904360SSuravee Suthikulpanit compatible = "fixed-clock"; 5241904360SSuravee Suthikulpanit #clock-cells = <0>; 5341904360SSuravee Suthikulpanit clock-frequency = <100000000>; 5441904360SSuravee Suthikulpanit clock-output-names = "uartspiclk_100mhz"; 5541904360SSuravee Suthikulpanit }; 56