xref: /openbmc/linux/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts (revision f4e4453aa9f474bb86f656a1cd56367444767f56)
1b8bcf0e1SAndre Przywara/*
2b8bcf0e1SAndre Przywara * Copyright (c) 2016 ARM Ltd.
3b8bcf0e1SAndre Przywara *
4b8bcf0e1SAndre Przywara * This file is dual-licensed: you can use it either under the terms
5b8bcf0e1SAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual
6b8bcf0e1SAndre Przywara * licensing only applies to this file, and not this project as a
7b8bcf0e1SAndre Przywara * whole.
8b8bcf0e1SAndre Przywara *
9b8bcf0e1SAndre Przywara *  a) This library is free software; you can redistribute it and/or
10b8bcf0e1SAndre Przywara *     modify it under the terms of the GNU General Public License as
11b8bcf0e1SAndre Przywara *     published by the Free Software Foundation; either version 2 of the
12b8bcf0e1SAndre Przywara *     License, or (at your option) any later version.
13b8bcf0e1SAndre Przywara *
14b8bcf0e1SAndre Przywara *     This library is distributed in the hope that it will be useful,
15b8bcf0e1SAndre Przywara *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16b8bcf0e1SAndre Przywara *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17b8bcf0e1SAndre Przywara *     GNU General Public License for more details.
18b8bcf0e1SAndre Przywara *
19b8bcf0e1SAndre Przywara * Or, alternatively,
20b8bcf0e1SAndre Przywara *
21b8bcf0e1SAndre Przywara *  b) Permission is hereby granted, free of charge, to any person
22b8bcf0e1SAndre Przywara *     obtaining a copy of this software and associated documentation
23b8bcf0e1SAndre Przywara *     files (the "Software"), to deal in the Software without
24b8bcf0e1SAndre Przywara *     restriction, including without limitation the rights to use,
25b8bcf0e1SAndre Przywara *     copy, modify, merge, publish, distribute, sublicense, and/or
26b8bcf0e1SAndre Przywara *     sell copies of the Software, and to permit persons to whom the
27b8bcf0e1SAndre Przywara *     Software is furnished to do so, subject to the following
28b8bcf0e1SAndre Przywara *     conditions:
29b8bcf0e1SAndre Przywara *
30b8bcf0e1SAndre Przywara *     The above copyright notice and this permission notice shall be
31b8bcf0e1SAndre Przywara *     included in all copies or substantial portions of the Software.
32b8bcf0e1SAndre Przywara *
33b8bcf0e1SAndre Przywara *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34b8bcf0e1SAndre Przywara *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35b8bcf0e1SAndre Przywara *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36b8bcf0e1SAndre Przywara *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37b8bcf0e1SAndre Przywara *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38b8bcf0e1SAndre Przywara *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39b8bcf0e1SAndre Przywara *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40b8bcf0e1SAndre Przywara *     OTHER DEALINGS IN THE SOFTWARE.
41b8bcf0e1SAndre Przywara */
42b8bcf0e1SAndre Przywara
43b8bcf0e1SAndre Przywara/dts-v1/;
44b8bcf0e1SAndre Przywara
45b8bcf0e1SAndre Przywara#include "sun50i-a64.dtsi"
46b8bcf0e1SAndre Przywara
47b8bcf0e1SAndre Przywara#include <dt-bindings/gpio/gpio.h>
48b8bcf0e1SAndre Przywara
49b8bcf0e1SAndre Przywara/ {
50b8bcf0e1SAndre Przywara	model = "BananaPi-M64";
51b8bcf0e1SAndre Przywara	compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
52b8bcf0e1SAndre Przywara
53b8bcf0e1SAndre Przywara	aliases {
5494f44288SCorentin Labbe		ethernet0 = &emac;
55b8bcf0e1SAndre Przywara		serial0 = &uart0;
56b8bcf0e1SAndre Przywara		serial1 = &uart1;
57b8bcf0e1SAndre Przywara	};
58b8bcf0e1SAndre Przywara
59b8bcf0e1SAndre Przywara	chosen {
60b8bcf0e1SAndre Przywara		stdout-path = "serial0:115200n8";
61b8bcf0e1SAndre Przywara	};
623bc1de8cSIcenowy Zheng
63*f4e4453aSJagan Teki	hdmi-connector {
64*f4e4453aSJagan Teki		compatible = "hdmi-connector";
65*f4e4453aSJagan Teki		type = "a";
66*f4e4453aSJagan Teki
67*f4e4453aSJagan Teki		port {
68*f4e4453aSJagan Teki			hdmi_con_in: endpoint {
69*f4e4453aSJagan Teki				remote-endpoint = <&hdmi_out_con>;
70*f4e4453aSJagan Teki			};
71*f4e4453aSJagan Teki		};
72*f4e4453aSJagan Teki	};
73*f4e4453aSJagan Teki
7436252668SChen-Yu Tsai	leds {
7536252668SChen-Yu Tsai		compatible = "gpio-leds";
7636252668SChen-Yu Tsai
7736252668SChen-Yu Tsai		pwr-led {
7836252668SChen-Yu Tsai			label = "bananapi-m64:red:pwr";
7936252668SChen-Yu Tsai			gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
8036252668SChen-Yu Tsai			default-state = "on";
8136252668SChen-Yu Tsai		};
8236252668SChen-Yu Tsai
8336252668SChen-Yu Tsai		green {
8436252668SChen-Yu Tsai			label = "bananapi-m64:green:user";
8536252668SChen-Yu Tsai			gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */
8636252668SChen-Yu Tsai		};
8736252668SChen-Yu Tsai
8836252668SChen-Yu Tsai		blue {
8936252668SChen-Yu Tsai			label = "bananapi-m64:blue:user";
9036252668SChen-Yu Tsai			gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
9136252668SChen-Yu Tsai		};
9236252668SChen-Yu Tsai	};
9336252668SChen-Yu Tsai
943bc1de8cSIcenowy Zheng	wifi_pwrseq: wifi_pwrseq {
953bc1de8cSIcenowy Zheng		compatible = "mmc-pwrseq-simple";
963bc1de8cSIcenowy Zheng		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
973bc1de8cSIcenowy Zheng	};
98b8bcf0e1SAndre Przywara};
99b8bcf0e1SAndre Przywara
100*f4e4453aSJagan Teki&de {
101*f4e4453aSJagan Teki	status = "okay";
102*f4e4453aSJagan Teki};
103*f4e4453aSJagan Teki
10481866805SJagan Teki&ehci0 {
10581866805SJagan Teki	status = "okay";
10681866805SJagan Teki};
10781866805SJagan Teki
10815ec9598SIcenowy Zheng&ehci1 {
10915ec9598SIcenowy Zheng	status = "okay";
11015ec9598SIcenowy Zheng};
11115ec9598SIcenowy Zheng
11294f44288SCorentin Labbe&emac {
11394f44288SCorentin Labbe	pinctrl-names = "default";
11494f44288SCorentin Labbe	pinctrl-0 = <&rgmii_pins>;
11594f44288SCorentin Labbe	phy-mode = "rgmii";
11694f44288SCorentin Labbe	phy-handle = <&ext_rgmii_phy>;
117bdfe4cebSIcenowy Zheng	phy-supply = <&reg_dc1sw>;
11894f44288SCorentin Labbe	status = "okay";
11994f44288SCorentin Labbe};
12094f44288SCorentin Labbe
121*f4e4453aSJagan Teki&hdmi {
122*f4e4453aSJagan Teki	hvcc-supply = <&reg_dldo1>;
123*f4e4453aSJagan Teki	status = "okay";
124*f4e4453aSJagan Teki};
125*f4e4453aSJagan Teki
126*f4e4453aSJagan Teki&hdmi_out {
127*f4e4453aSJagan Teki	hdmi_out_con: endpoint {
128*f4e4453aSJagan Teki		remote-endpoint = <&hdmi_con_in>;
129*f4e4453aSJagan Teki	};
130*f4e4453aSJagan Teki};
131*f4e4453aSJagan Teki
132b8bcf0e1SAndre Przywara&i2c1 {
133b8bcf0e1SAndre Przywara	pinctrl-names = "default";
134b8bcf0e1SAndre Przywara	pinctrl-0 = <&i2c1_pins>;
135b8bcf0e1SAndre Przywara	status = "okay";
136b8bcf0e1SAndre Przywara};
137b8bcf0e1SAndre Przywara
138b8bcf0e1SAndre Przywara&i2c1_pins {
139b8bcf0e1SAndre Przywara	bias-pull-up;
140b8bcf0e1SAndre Przywara};
141b8bcf0e1SAndre Przywara
14294f44288SCorentin Labbe&mdio {
14394f44288SCorentin Labbe	ext_rgmii_phy: ethernet-phy@1 {
14494f44288SCorentin Labbe		compatible = "ethernet-phy-ieee802.3-c22";
14594f44288SCorentin Labbe		reg = <1>;
14694f44288SCorentin Labbe	};
14794f44288SCorentin Labbe};
14894f44288SCorentin Labbe
149b8bcf0e1SAndre Przywara&mmc0 {
150b8bcf0e1SAndre Przywara	pinctrl-names = "default";
151b8bcf0e1SAndre Przywara	pinctrl-0 = <&mmc0_pins>;
1520ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dcdc1>;
153b75cb68dSTuomas Tynkkynen	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
154b8bcf0e1SAndre Przywara	disable-wp;
155b8bcf0e1SAndre Przywara	bus-width = <4>;
156b8bcf0e1SAndre Przywara	status = "okay";
157b8bcf0e1SAndre Przywara};
158b8bcf0e1SAndre Przywara
159b8bcf0e1SAndre Przywara&mmc1 {
160b8bcf0e1SAndre Przywara	pinctrl-names = "default";
161b8bcf0e1SAndre Przywara	pinctrl-0 = <&mmc1_pins>;
1620ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dldo2>;
1630ff75efbSIcenowy Zheng	vqmmc-supply = <&reg_dldo4>;
1643bc1de8cSIcenowy Zheng	mmc-pwrseq = <&wifi_pwrseq>;
165b8bcf0e1SAndre Przywara	bus-width = <4>;
166b8bcf0e1SAndre Przywara	non-removable;
167b8bcf0e1SAndre Przywara	status = "okay";
1683bc1de8cSIcenowy Zheng
1693bc1de8cSIcenowy Zheng	brcmf: wifi@1 {
1703bc1de8cSIcenowy Zheng		reg = <1>;
1713bc1de8cSIcenowy Zheng		compatible = "brcm,bcm4329-fmac";
1723bc1de8cSIcenowy Zheng		interrupt-parent = <&r_pio>;
1733bc1de8cSIcenowy Zheng		interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
1743bc1de8cSIcenowy Zheng		interrupt-names = "host-wake";
1753bc1de8cSIcenowy Zheng	};
176b8bcf0e1SAndre Przywara};
177b8bcf0e1SAndre Przywara
178b8bcf0e1SAndre Przywara&mmc2 {
179b8bcf0e1SAndre Przywara	pinctrl-names = "default";
180fa59dd2eSChen-Yu Tsai	pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
1810ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dcdc1>;
182b8bcf0e1SAndre Przywara	bus-width = <8>;
183b8bcf0e1SAndre Przywara	non-removable;
184b8bcf0e1SAndre Przywara	cap-mmc-hw-reset;
185b8bcf0e1SAndre Przywara	status = "okay";
186b8bcf0e1SAndre Przywara};
187b8bcf0e1SAndre Przywara
18881866805SJagan Teki&ohci0 {
18981866805SJagan Teki	status = "okay";
19081866805SJagan Teki};
19181866805SJagan Teki
19215ec9598SIcenowy Zheng&ohci1 {
19315ec9598SIcenowy Zheng	status = "okay";
19415ec9598SIcenowy Zheng};
19515ec9598SIcenowy Zheng
1960ff75efbSIcenowy Zheng&r_rsb {
1970ff75efbSIcenowy Zheng	status = "okay";
1980ff75efbSIcenowy Zheng
1990ff75efbSIcenowy Zheng	axp803: pmic@3a3 {
2000ff75efbSIcenowy Zheng		compatible = "x-powers,axp803";
2010ff75efbSIcenowy Zheng		reg = <0x3a3>;
2020ff75efbSIcenowy Zheng		interrupt-parent = <&r_intc>;
2030ff75efbSIcenowy Zheng		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
20481866805SJagan Teki		x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
2050ff75efbSIcenowy Zheng	};
2060ff75efbSIcenowy Zheng};
2070ff75efbSIcenowy Zheng
2080ff75efbSIcenowy Zheng#include "axp803.dtsi"
2090ff75efbSIcenowy Zheng
21036252668SChen-Yu Tsai&reg_aldo1 {
21136252668SChen-Yu Tsai	/*
21236252668SChen-Yu Tsai	 * This regulator also drives the PE pingroup GPIOs,
21336252668SChen-Yu Tsai	 * which also controls two LEDs.
21436252668SChen-Yu Tsai	 */
21536252668SChen-Yu Tsai	regulator-always-on;
21636252668SChen-Yu Tsai	regulator-min-microvolt = <2800000>;
21736252668SChen-Yu Tsai	regulator-max-microvolt = <2800000>;
21836252668SChen-Yu Tsai	regulator-name = "afvcc-csi";
21936252668SChen-Yu Tsai};
22036252668SChen-Yu Tsai
2210ff75efbSIcenowy Zheng&reg_aldo2 {
2220ff75efbSIcenowy Zheng	regulator-always-on;
2230ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
2240ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2250ff75efbSIcenowy Zheng	regulator-name = "vcc-pl";
2260ff75efbSIcenowy Zheng};
2270ff75efbSIcenowy Zheng
2280ff75efbSIcenowy Zheng&reg_aldo3 {
2290ff75efbSIcenowy Zheng	regulator-always-on;
2300ff75efbSIcenowy Zheng	regulator-min-microvolt = <3000000>;
2310ff75efbSIcenowy Zheng	regulator-max-microvolt = <3000000>;
2320ff75efbSIcenowy Zheng	regulator-name = "vcc-pll-avcc";
2330ff75efbSIcenowy Zheng};
2340ff75efbSIcenowy Zheng
2350ff75efbSIcenowy Zheng&reg_dc1sw {
23636252668SChen-Yu Tsai	/*
23736252668SChen-Yu Tsai	 * This regulator also indirectly drives the PD pingroup GPIOs,
23836252668SChen-Yu Tsai	 * which also controls the power LED.
23936252668SChen-Yu Tsai	 */
24036252668SChen-Yu Tsai	regulator-always-on;
2410ff75efbSIcenowy Zheng	regulator-name = "vcc-phy";
2420ff75efbSIcenowy Zheng};
2430ff75efbSIcenowy Zheng
2440ff75efbSIcenowy Zheng&reg_dcdc1 {
2450ff75efbSIcenowy Zheng	regulator-always-on;
2460ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
2470ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2480ff75efbSIcenowy Zheng	regulator-name = "vcc-3v3";
2490ff75efbSIcenowy Zheng};
2500ff75efbSIcenowy Zheng
2510ff75efbSIcenowy Zheng&reg_dcdc2 {
2520ff75efbSIcenowy Zheng	regulator-always-on;
2530ff75efbSIcenowy Zheng	regulator-min-microvolt = <1040000>;
2540ff75efbSIcenowy Zheng	regulator-max-microvolt = <1300000>;
2550ff75efbSIcenowy Zheng	regulator-name = "vdd-cpux";
2560ff75efbSIcenowy Zheng};
2570ff75efbSIcenowy Zheng
2580ff75efbSIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */
2590ff75efbSIcenowy Zheng
2600ff75efbSIcenowy Zheng&reg_dcdc5 {
2610ff75efbSIcenowy Zheng	regulator-always-on;
2620ff75efbSIcenowy Zheng	regulator-min-microvolt = <1500000>;
2630ff75efbSIcenowy Zheng	regulator-max-microvolt = <1500000>;
2640ff75efbSIcenowy Zheng	regulator-name = "vcc-dram";
2650ff75efbSIcenowy Zheng};
2660ff75efbSIcenowy Zheng
2670ff75efbSIcenowy Zheng&reg_dcdc6 {
2680ff75efbSIcenowy Zheng	regulator-always-on;
2690ff75efbSIcenowy Zheng	regulator-min-microvolt = <1100000>;
2700ff75efbSIcenowy Zheng	regulator-max-microvolt = <1100000>;
2710ff75efbSIcenowy Zheng	regulator-name = "vdd-sys";
2720ff75efbSIcenowy Zheng};
2730ff75efbSIcenowy Zheng
2740ff75efbSIcenowy Zheng&reg_dldo1 {
2750ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
2760ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2770ff75efbSIcenowy Zheng	regulator-name = "vcc-hdmi-dsi";
2780ff75efbSIcenowy Zheng};
2790ff75efbSIcenowy Zheng
2800ff75efbSIcenowy Zheng&reg_dldo2 {
2810ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
2820ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2830ff75efbSIcenowy Zheng	regulator-name = "vcc-wifi";
2840ff75efbSIcenowy Zheng};
2850ff75efbSIcenowy Zheng
2860ff75efbSIcenowy Zheng&reg_dldo4 {
2870ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
2880ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2890ff75efbSIcenowy Zheng	regulator-name = "vcc-wifi-io";
2900ff75efbSIcenowy Zheng};
2910ff75efbSIcenowy Zheng
29281866805SJagan Teki&reg_drivevbus {
29381866805SJagan Teki	regulator-name = "usb0-vbus";
29481866805SJagan Teki	status = "okay";
29581866805SJagan Teki};
29681866805SJagan Teki
2970ff75efbSIcenowy Zheng&reg_eldo1 {
2980ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
2990ff75efbSIcenowy Zheng	regulator-max-microvolt = <1800000>;
3000ff75efbSIcenowy Zheng	regulator-name = "cpvdd";
3010ff75efbSIcenowy Zheng};
3020ff75efbSIcenowy Zheng
3030ff75efbSIcenowy Zheng&reg_fldo1 {
3040ff75efbSIcenowy Zheng	regulator-min-microvolt = <1200000>;
3050ff75efbSIcenowy Zheng	regulator-max-microvolt = <1200000>;
3060ff75efbSIcenowy Zheng	regulator-name = "vcc-1v2-hsic";
3070ff75efbSIcenowy Zheng};
3080ff75efbSIcenowy Zheng
3090ff75efbSIcenowy Zheng/*
3100ff75efbSIcenowy Zheng * The A64 chip cannot work without this regulator off, although
3110ff75efbSIcenowy Zheng * it seems to be only driving the AR100 core.
3120ff75efbSIcenowy Zheng * Maybe we don't still know well about CPUs domain.
3130ff75efbSIcenowy Zheng */
3140ff75efbSIcenowy Zheng&reg_fldo2 {
3150ff75efbSIcenowy Zheng	regulator-always-on;
3160ff75efbSIcenowy Zheng	regulator-min-microvolt = <1100000>;
3170ff75efbSIcenowy Zheng	regulator-max-microvolt = <1100000>;
3180ff75efbSIcenowy Zheng	regulator-name = "vdd-cpus";
3190ff75efbSIcenowy Zheng};
3200ff75efbSIcenowy Zheng
3210ff75efbSIcenowy Zheng&reg_rtc_ldo {
3220ff75efbSIcenowy Zheng	regulator-name = "vcc-rtc";
3230ff75efbSIcenowy Zheng};
3240ff75efbSIcenowy Zheng
3255cbef9f9SIcenowy Zheng&simplefb_hdmi {
3265cbef9f9SIcenowy Zheng	vcc-hdmi-supply = <&reg_dldo1>;
3275cbef9f9SIcenowy Zheng};
3285cbef9f9SIcenowy Zheng
329b8bcf0e1SAndre Przywara&uart0 {
330b8bcf0e1SAndre Przywara	pinctrl-names = "default";
331d91ebb95SChen-Yu Tsai	pinctrl-0 = <&uart0_pb_pins>;
332b8bcf0e1SAndre Przywara	status = "okay";
333b8bcf0e1SAndre Przywara};
334b8bcf0e1SAndre Przywara
335b8bcf0e1SAndre Przywara&uart1 {
336b8bcf0e1SAndre Przywara	pinctrl-names = "default";
337b8bcf0e1SAndre Przywara	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
338b8bcf0e1SAndre Przywara	status = "okay";
339b8bcf0e1SAndre Przywara};
34015ec9598SIcenowy Zheng
34181866805SJagan Teki&usb_otg {
34281866805SJagan Teki	dr_mode = "otg";
34381866805SJagan Teki	status = "okay";
34481866805SJagan Teki};
34581866805SJagan Teki
34615ec9598SIcenowy Zheng&usbphy {
34781866805SJagan Teki	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
34881866805SJagan Teki	usb0_vbus-supply = <&reg_drivevbus>;
34915ec9598SIcenowy Zheng	status = "okay";
35015ec9598SIcenowy Zheng};
351