1b8bcf0e1SAndre Przywara/* 2b8bcf0e1SAndre Przywara * Copyright (c) 2016 ARM Ltd. 3b8bcf0e1SAndre Przywara * 4b8bcf0e1SAndre Przywara * This file is dual-licensed: you can use it either under the terms 5b8bcf0e1SAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 6b8bcf0e1SAndre Przywara * licensing only applies to this file, and not this project as a 7b8bcf0e1SAndre Przywara * whole. 8b8bcf0e1SAndre Przywara * 9b8bcf0e1SAndre Przywara * a) This library is free software; you can redistribute it and/or 10b8bcf0e1SAndre Przywara * modify it under the terms of the GNU General Public License as 11b8bcf0e1SAndre Przywara * published by the Free Software Foundation; either version 2 of the 12b8bcf0e1SAndre Przywara * License, or (at your option) any later version. 13b8bcf0e1SAndre Przywara * 14b8bcf0e1SAndre Przywara * This library is distributed in the hope that it will be useful, 15b8bcf0e1SAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 16b8bcf0e1SAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17b8bcf0e1SAndre Przywara * GNU General Public License for more details. 18b8bcf0e1SAndre Przywara * 19b8bcf0e1SAndre Przywara * Or, alternatively, 20b8bcf0e1SAndre Przywara * 21b8bcf0e1SAndre Przywara * b) Permission is hereby granted, free of charge, to any person 22b8bcf0e1SAndre Przywara * obtaining a copy of this software and associated documentation 23b8bcf0e1SAndre Przywara * files (the "Software"), to deal in the Software without 24b8bcf0e1SAndre Przywara * restriction, including without limitation the rights to use, 25b8bcf0e1SAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 26b8bcf0e1SAndre Przywara * sell copies of the Software, and to permit persons to whom the 27b8bcf0e1SAndre Przywara * Software is furnished to do so, subject to the following 28b8bcf0e1SAndre Przywara * conditions: 29b8bcf0e1SAndre Przywara * 30b8bcf0e1SAndre Przywara * The above copyright notice and this permission notice shall be 31b8bcf0e1SAndre Przywara * included in all copies or substantial portions of the Software. 32b8bcf0e1SAndre Przywara * 33b8bcf0e1SAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34b8bcf0e1SAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35b8bcf0e1SAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36b8bcf0e1SAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37b8bcf0e1SAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38b8bcf0e1SAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39b8bcf0e1SAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40b8bcf0e1SAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 41b8bcf0e1SAndre Przywara */ 42b8bcf0e1SAndre Przywara 43b8bcf0e1SAndre Przywara/dts-v1/; 44b8bcf0e1SAndre Przywara 45b8bcf0e1SAndre Przywara#include "sun50i-a64.dtsi" 46b8bcf0e1SAndre Przywara 47b8bcf0e1SAndre Przywara#include <dt-bindings/gpio/gpio.h> 48b8bcf0e1SAndre Przywara 49b8bcf0e1SAndre Przywara/ { 50b8bcf0e1SAndre Przywara model = "BananaPi-M64"; 51b8bcf0e1SAndre Przywara compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; 52b8bcf0e1SAndre Przywara 53b8bcf0e1SAndre Przywara aliases { 5494f44288SCorentin Labbe ethernet0 = &emac; 55b8bcf0e1SAndre Przywara serial0 = &uart0; 56b8bcf0e1SAndre Przywara serial1 = &uart1; 57b8bcf0e1SAndre Przywara }; 58b8bcf0e1SAndre Przywara 59b8bcf0e1SAndre Przywara chosen { 60b8bcf0e1SAndre Przywara stdout-path = "serial0:115200n8"; 61b8bcf0e1SAndre Przywara }; 623bc1de8cSIcenowy Zheng 633bc1de8cSIcenowy Zheng wifi_pwrseq: wifi_pwrseq { 643bc1de8cSIcenowy Zheng compatible = "mmc-pwrseq-simple"; 653bc1de8cSIcenowy Zheng reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ 663bc1de8cSIcenowy Zheng }; 67b8bcf0e1SAndre Przywara}; 68b8bcf0e1SAndre Przywara 6915ec9598SIcenowy Zheng&ehci1 { 7015ec9598SIcenowy Zheng status = "okay"; 7115ec9598SIcenowy Zheng}; 7215ec9598SIcenowy Zheng 7394f44288SCorentin Labbe&emac { 7494f44288SCorentin Labbe pinctrl-names = "default"; 7594f44288SCorentin Labbe pinctrl-0 = <&rgmii_pins>; 7694f44288SCorentin Labbe phy-mode = "rgmii"; 7794f44288SCorentin Labbe phy-handle = <&ext_rgmii_phy>; 78*bdfe4cebSIcenowy Zheng phy-supply = <®_dc1sw>; 7994f44288SCorentin Labbe status = "okay"; 8094f44288SCorentin Labbe}; 8194f44288SCorentin Labbe 82b8bcf0e1SAndre Przywara&i2c1 { 83b8bcf0e1SAndre Przywara pinctrl-names = "default"; 84b8bcf0e1SAndre Przywara pinctrl-0 = <&i2c1_pins>; 85b8bcf0e1SAndre Przywara status = "okay"; 86b8bcf0e1SAndre Przywara}; 87b8bcf0e1SAndre Przywara 88b8bcf0e1SAndre Przywara&i2c1_pins { 89b8bcf0e1SAndre Przywara bias-pull-up; 90b8bcf0e1SAndre Przywara}; 91b8bcf0e1SAndre Przywara 9294f44288SCorentin Labbe&mdio { 9394f44288SCorentin Labbe ext_rgmii_phy: ethernet-phy@1 { 9494f44288SCorentin Labbe compatible = "ethernet-phy-ieee802.3-c22"; 9594f44288SCorentin Labbe reg = <1>; 9694f44288SCorentin Labbe }; 9794f44288SCorentin Labbe}; 9894f44288SCorentin Labbe 99b8bcf0e1SAndre Przywara&mmc0 { 100b8bcf0e1SAndre Przywara pinctrl-names = "default"; 101b8bcf0e1SAndre Przywara pinctrl-0 = <&mmc0_pins>; 1020ff75efbSIcenowy Zheng vmmc-supply = <®_dcdc1>; 103b8bcf0e1SAndre Przywara cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 104b8bcf0e1SAndre Przywara cd-inverted; 105b8bcf0e1SAndre Przywara disable-wp; 106b8bcf0e1SAndre Przywara bus-width = <4>; 107b8bcf0e1SAndre Przywara status = "okay"; 108b8bcf0e1SAndre Przywara}; 109b8bcf0e1SAndre Przywara 110b8bcf0e1SAndre Przywara&mmc1 { 111b8bcf0e1SAndre Przywara pinctrl-names = "default"; 112b8bcf0e1SAndre Przywara pinctrl-0 = <&mmc1_pins>; 1130ff75efbSIcenowy Zheng vmmc-supply = <®_dldo2>; 1140ff75efbSIcenowy Zheng vqmmc-supply = <®_dldo4>; 1153bc1de8cSIcenowy Zheng mmc-pwrseq = <&wifi_pwrseq>; 116b8bcf0e1SAndre Przywara bus-width = <4>; 117b8bcf0e1SAndre Przywara non-removable; 118b8bcf0e1SAndre Przywara status = "okay"; 1193bc1de8cSIcenowy Zheng 1203bc1de8cSIcenowy Zheng brcmf: wifi@1 { 1213bc1de8cSIcenowy Zheng reg = <1>; 1223bc1de8cSIcenowy Zheng compatible = "brcm,bcm4329-fmac"; 1233bc1de8cSIcenowy Zheng interrupt-parent = <&r_pio>; 1243bc1de8cSIcenowy Zheng interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ 1253bc1de8cSIcenowy Zheng interrupt-names = "host-wake"; 1263bc1de8cSIcenowy Zheng }; 127b8bcf0e1SAndre Przywara}; 128b8bcf0e1SAndre Przywara 129b8bcf0e1SAndre Przywara&mmc2 { 130b8bcf0e1SAndre Przywara pinctrl-names = "default"; 131b8bcf0e1SAndre Przywara pinctrl-0 = <&mmc2_pins>; 1320ff75efbSIcenowy Zheng vmmc-supply = <®_dcdc1>; 133b8bcf0e1SAndre Przywara bus-width = <8>; 134b8bcf0e1SAndre Przywara non-removable; 135b8bcf0e1SAndre Przywara cap-mmc-hw-reset; 136b8bcf0e1SAndre Przywara status = "okay"; 137b8bcf0e1SAndre Przywara}; 138b8bcf0e1SAndre Przywara 13915ec9598SIcenowy Zheng&ohci1 { 14015ec9598SIcenowy Zheng status = "okay"; 14115ec9598SIcenowy Zheng}; 14215ec9598SIcenowy Zheng 1430ff75efbSIcenowy Zheng&r_rsb { 1440ff75efbSIcenowy Zheng status = "okay"; 1450ff75efbSIcenowy Zheng 1460ff75efbSIcenowy Zheng axp803: pmic@3a3 { 1470ff75efbSIcenowy Zheng compatible = "x-powers,axp803"; 1480ff75efbSIcenowy Zheng reg = <0x3a3>; 1490ff75efbSIcenowy Zheng interrupt-parent = <&r_intc>; 1500ff75efbSIcenowy Zheng interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 1510ff75efbSIcenowy Zheng }; 1520ff75efbSIcenowy Zheng}; 1530ff75efbSIcenowy Zheng 1540ff75efbSIcenowy Zheng#include "axp803.dtsi" 1550ff75efbSIcenowy Zheng 1560ff75efbSIcenowy Zheng®_aldo2 { 1570ff75efbSIcenowy Zheng regulator-always-on; 1580ff75efbSIcenowy Zheng regulator-min-microvolt = <1800000>; 1590ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 1600ff75efbSIcenowy Zheng regulator-name = "vcc-pl"; 1610ff75efbSIcenowy Zheng}; 1620ff75efbSIcenowy Zheng 1630ff75efbSIcenowy Zheng®_aldo3 { 1640ff75efbSIcenowy Zheng regulator-always-on; 1650ff75efbSIcenowy Zheng regulator-min-microvolt = <3000000>; 1660ff75efbSIcenowy Zheng regulator-max-microvolt = <3000000>; 1670ff75efbSIcenowy Zheng regulator-name = "vcc-pll-avcc"; 1680ff75efbSIcenowy Zheng}; 1690ff75efbSIcenowy Zheng 1700ff75efbSIcenowy Zheng®_dc1sw { 1710ff75efbSIcenowy Zheng regulator-name = "vcc-phy"; 1720ff75efbSIcenowy Zheng}; 1730ff75efbSIcenowy Zheng 1740ff75efbSIcenowy Zheng®_dcdc1 { 1750ff75efbSIcenowy Zheng regulator-always-on; 1760ff75efbSIcenowy Zheng regulator-min-microvolt = <3300000>; 1770ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 1780ff75efbSIcenowy Zheng regulator-name = "vcc-3v3"; 1790ff75efbSIcenowy Zheng}; 1800ff75efbSIcenowy Zheng 1810ff75efbSIcenowy Zheng®_dcdc2 { 1820ff75efbSIcenowy Zheng regulator-always-on; 1830ff75efbSIcenowy Zheng regulator-min-microvolt = <1040000>; 1840ff75efbSIcenowy Zheng regulator-max-microvolt = <1300000>; 1850ff75efbSIcenowy Zheng regulator-name = "vdd-cpux"; 1860ff75efbSIcenowy Zheng}; 1870ff75efbSIcenowy Zheng 1880ff75efbSIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */ 1890ff75efbSIcenowy Zheng 1900ff75efbSIcenowy Zheng®_dcdc5 { 1910ff75efbSIcenowy Zheng regulator-always-on; 1920ff75efbSIcenowy Zheng regulator-min-microvolt = <1500000>; 1930ff75efbSIcenowy Zheng regulator-max-microvolt = <1500000>; 1940ff75efbSIcenowy Zheng regulator-name = "vcc-dram"; 1950ff75efbSIcenowy Zheng}; 1960ff75efbSIcenowy Zheng 1970ff75efbSIcenowy Zheng®_dcdc6 { 1980ff75efbSIcenowy Zheng regulator-always-on; 1990ff75efbSIcenowy Zheng regulator-min-microvolt = <1100000>; 2000ff75efbSIcenowy Zheng regulator-max-microvolt = <1100000>; 2010ff75efbSIcenowy Zheng regulator-name = "vdd-sys"; 2020ff75efbSIcenowy Zheng}; 2030ff75efbSIcenowy Zheng 2040ff75efbSIcenowy Zheng®_dldo1 { 2050ff75efbSIcenowy Zheng regulator-min-microvolt = <3300000>; 2060ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 2070ff75efbSIcenowy Zheng regulator-name = "vcc-hdmi-dsi"; 2080ff75efbSIcenowy Zheng}; 2090ff75efbSIcenowy Zheng 2100ff75efbSIcenowy Zheng®_dldo2 { 2110ff75efbSIcenowy Zheng regulator-min-microvolt = <3300000>; 2120ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 2130ff75efbSIcenowy Zheng regulator-name = "vcc-wifi"; 2140ff75efbSIcenowy Zheng}; 2150ff75efbSIcenowy Zheng 2160ff75efbSIcenowy Zheng®_dldo4 { 2170ff75efbSIcenowy Zheng regulator-min-microvolt = <1800000>; 2180ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 2190ff75efbSIcenowy Zheng regulator-name = "vcc-wifi-io"; 2200ff75efbSIcenowy Zheng}; 2210ff75efbSIcenowy Zheng 2220ff75efbSIcenowy Zheng®_eldo1 { 2230ff75efbSIcenowy Zheng regulator-min-microvolt = <1800000>; 2240ff75efbSIcenowy Zheng regulator-max-microvolt = <1800000>; 2250ff75efbSIcenowy Zheng regulator-name = "cpvdd"; 2260ff75efbSIcenowy Zheng}; 2270ff75efbSIcenowy Zheng 2280ff75efbSIcenowy Zheng®_fldo1 { 2290ff75efbSIcenowy Zheng regulator-min-microvolt = <1200000>; 2300ff75efbSIcenowy Zheng regulator-max-microvolt = <1200000>; 2310ff75efbSIcenowy Zheng regulator-name = "vcc-1v2-hsic"; 2320ff75efbSIcenowy Zheng}; 2330ff75efbSIcenowy Zheng 2340ff75efbSIcenowy Zheng/* 2350ff75efbSIcenowy Zheng * The A64 chip cannot work without this regulator off, although 2360ff75efbSIcenowy Zheng * it seems to be only driving the AR100 core. 2370ff75efbSIcenowy Zheng * Maybe we don't still know well about CPUs domain. 2380ff75efbSIcenowy Zheng */ 2390ff75efbSIcenowy Zheng®_fldo2 { 2400ff75efbSIcenowy Zheng regulator-always-on; 2410ff75efbSIcenowy Zheng regulator-min-microvolt = <1100000>; 2420ff75efbSIcenowy Zheng regulator-max-microvolt = <1100000>; 2430ff75efbSIcenowy Zheng regulator-name = "vdd-cpus"; 2440ff75efbSIcenowy Zheng}; 2450ff75efbSIcenowy Zheng 2460ff75efbSIcenowy Zheng®_rtc_ldo { 2470ff75efbSIcenowy Zheng regulator-name = "vcc-rtc"; 2480ff75efbSIcenowy Zheng}; 2490ff75efbSIcenowy Zheng 250b8bcf0e1SAndre Przywara&uart0 { 251b8bcf0e1SAndre Przywara pinctrl-names = "default"; 252b8bcf0e1SAndre Przywara pinctrl-0 = <&uart0_pins_a>; 253b8bcf0e1SAndre Przywara status = "okay"; 254b8bcf0e1SAndre Przywara}; 255b8bcf0e1SAndre Przywara 256b8bcf0e1SAndre Przywara&uart1 { 257b8bcf0e1SAndre Przywara pinctrl-names = "default"; 258b8bcf0e1SAndre Przywara pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; 259b8bcf0e1SAndre Przywara status = "okay"; 260b8bcf0e1SAndre Przywara}; 26115ec9598SIcenowy Zheng 26215ec9598SIcenowy Zheng&usbphy { 26315ec9598SIcenowy Zheng status = "okay"; 26415ec9598SIcenowy Zheng}; 265