1b8bcf0e1SAndre Przywara/* 2b8bcf0e1SAndre Przywara * Copyright (c) 2016 ARM Ltd. 3b8bcf0e1SAndre Przywara * 4b8bcf0e1SAndre Przywara * This file is dual-licensed: you can use it either under the terms 5b8bcf0e1SAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual 6b8bcf0e1SAndre Przywara * licensing only applies to this file, and not this project as a 7b8bcf0e1SAndre Przywara * whole. 8b8bcf0e1SAndre Przywara * 9b8bcf0e1SAndre Przywara * a) This library is free software; you can redistribute it and/or 10b8bcf0e1SAndre Przywara * modify it under the terms of the GNU General Public License as 11b8bcf0e1SAndre Przywara * published by the Free Software Foundation; either version 2 of the 12b8bcf0e1SAndre Przywara * License, or (at your option) any later version. 13b8bcf0e1SAndre Przywara * 14b8bcf0e1SAndre Przywara * This library is distributed in the hope that it will be useful, 15b8bcf0e1SAndre Przywara * but WITHOUT ANY WARRANTY; without even the implied warranty of 16b8bcf0e1SAndre Przywara * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17b8bcf0e1SAndre Przywara * GNU General Public License for more details. 18b8bcf0e1SAndre Przywara * 19b8bcf0e1SAndre Przywara * Or, alternatively, 20b8bcf0e1SAndre Przywara * 21b8bcf0e1SAndre Przywara * b) Permission is hereby granted, free of charge, to any person 22b8bcf0e1SAndre Przywara * obtaining a copy of this software and associated documentation 23b8bcf0e1SAndre Przywara * files (the "Software"), to deal in the Software without 24b8bcf0e1SAndre Przywara * restriction, including without limitation the rights to use, 25b8bcf0e1SAndre Przywara * copy, modify, merge, publish, distribute, sublicense, and/or 26b8bcf0e1SAndre Przywara * sell copies of the Software, and to permit persons to whom the 27b8bcf0e1SAndre Przywara * Software is furnished to do so, subject to the following 28b8bcf0e1SAndre Przywara * conditions: 29b8bcf0e1SAndre Przywara * 30b8bcf0e1SAndre Przywara * The above copyright notice and this permission notice shall be 31b8bcf0e1SAndre Przywara * included in all copies or substantial portions of the Software. 32b8bcf0e1SAndre Przywara * 33b8bcf0e1SAndre Przywara * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34b8bcf0e1SAndre Przywara * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35b8bcf0e1SAndre Przywara * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36b8bcf0e1SAndre Przywara * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37b8bcf0e1SAndre Przywara * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38b8bcf0e1SAndre Przywara * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39b8bcf0e1SAndre Przywara * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40b8bcf0e1SAndre Przywara * OTHER DEALINGS IN THE SOFTWARE. 41b8bcf0e1SAndre Przywara */ 42b8bcf0e1SAndre Przywara 43b8bcf0e1SAndre Przywara/dts-v1/; 44b8bcf0e1SAndre Przywara 45b8bcf0e1SAndre Przywara#include "sun50i-a64.dtsi" 46b8bcf0e1SAndre Przywara 47b8bcf0e1SAndre Przywara#include <dt-bindings/gpio/gpio.h> 48b8bcf0e1SAndre Przywara 49b8bcf0e1SAndre Przywara/ { 50b8bcf0e1SAndre Przywara model = "BananaPi-M64"; 51b8bcf0e1SAndre Przywara compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64"; 52b8bcf0e1SAndre Przywara 53b8bcf0e1SAndre Przywara aliases { 5494f44288SCorentin Labbe ethernet0 = &emac; 55b8bcf0e1SAndre Przywara serial0 = &uart0; 56b8bcf0e1SAndre Przywara serial1 = &uart1; 57b8bcf0e1SAndre Przywara }; 58b8bcf0e1SAndre Przywara 59b8bcf0e1SAndre Przywara chosen { 60b8bcf0e1SAndre Przywara stdout-path = "serial0:115200n8"; 61b8bcf0e1SAndre Przywara }; 623bc1de8cSIcenowy Zheng 63*36252668SChen-Yu Tsai leds { 64*36252668SChen-Yu Tsai compatible = "gpio-leds"; 65*36252668SChen-Yu Tsai 66*36252668SChen-Yu Tsai pwr-led { 67*36252668SChen-Yu Tsai label = "bananapi-m64:red:pwr"; 68*36252668SChen-Yu Tsai gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ 69*36252668SChen-Yu Tsai default-state = "on"; 70*36252668SChen-Yu Tsai }; 71*36252668SChen-Yu Tsai 72*36252668SChen-Yu Tsai green { 73*36252668SChen-Yu Tsai label = "bananapi-m64:green:user"; 74*36252668SChen-Yu Tsai gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */ 75*36252668SChen-Yu Tsai }; 76*36252668SChen-Yu Tsai 77*36252668SChen-Yu Tsai blue { 78*36252668SChen-Yu Tsai label = "bananapi-m64:blue:user"; 79*36252668SChen-Yu Tsai gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */ 80*36252668SChen-Yu Tsai }; 81*36252668SChen-Yu Tsai }; 82*36252668SChen-Yu Tsai 833bc1de8cSIcenowy Zheng wifi_pwrseq: wifi_pwrseq { 843bc1de8cSIcenowy Zheng compatible = "mmc-pwrseq-simple"; 853bc1de8cSIcenowy Zheng reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ 863bc1de8cSIcenowy Zheng }; 87b8bcf0e1SAndre Przywara}; 88b8bcf0e1SAndre Przywara 8915ec9598SIcenowy Zheng&ehci1 { 9015ec9598SIcenowy Zheng status = "okay"; 9115ec9598SIcenowy Zheng}; 9215ec9598SIcenowy Zheng 9394f44288SCorentin Labbe&emac { 9494f44288SCorentin Labbe pinctrl-names = "default"; 9594f44288SCorentin Labbe pinctrl-0 = <&rgmii_pins>; 9694f44288SCorentin Labbe phy-mode = "rgmii"; 9794f44288SCorentin Labbe phy-handle = <&ext_rgmii_phy>; 9894f44288SCorentin Labbe status = "okay"; 9994f44288SCorentin Labbe}; 10094f44288SCorentin Labbe 101b8bcf0e1SAndre Przywara&i2c1 { 102b8bcf0e1SAndre Przywara pinctrl-names = "default"; 103b8bcf0e1SAndre Przywara pinctrl-0 = <&i2c1_pins>; 104b8bcf0e1SAndre Przywara status = "okay"; 105b8bcf0e1SAndre Przywara}; 106b8bcf0e1SAndre Przywara 107b8bcf0e1SAndre Przywara&i2c1_pins { 108b8bcf0e1SAndre Przywara bias-pull-up; 109b8bcf0e1SAndre Przywara}; 110b8bcf0e1SAndre Przywara 11194f44288SCorentin Labbe&mdio { 11294f44288SCorentin Labbe ext_rgmii_phy: ethernet-phy@1 { 11394f44288SCorentin Labbe compatible = "ethernet-phy-ieee802.3-c22"; 11494f44288SCorentin Labbe reg = <1>; 11594f44288SCorentin Labbe }; 11694f44288SCorentin Labbe}; 11794f44288SCorentin Labbe 118b8bcf0e1SAndre Przywara&mmc0 { 119b8bcf0e1SAndre Przywara pinctrl-names = "default"; 120b8bcf0e1SAndre Przywara pinctrl-0 = <&mmc0_pins>; 1210ff75efbSIcenowy Zheng vmmc-supply = <®_dcdc1>; 122b8bcf0e1SAndre Przywara cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 123b8bcf0e1SAndre Przywara cd-inverted; 124b8bcf0e1SAndre Przywara disable-wp; 125b8bcf0e1SAndre Przywara bus-width = <4>; 126b8bcf0e1SAndre Przywara status = "okay"; 127b8bcf0e1SAndre Przywara}; 128b8bcf0e1SAndre Przywara 129b8bcf0e1SAndre Przywara&mmc1 { 130b8bcf0e1SAndre Przywara pinctrl-names = "default"; 131b8bcf0e1SAndre Przywara pinctrl-0 = <&mmc1_pins>; 1320ff75efbSIcenowy Zheng vmmc-supply = <®_dldo2>; 1330ff75efbSIcenowy Zheng vqmmc-supply = <®_dldo4>; 1343bc1de8cSIcenowy Zheng mmc-pwrseq = <&wifi_pwrseq>; 135b8bcf0e1SAndre Przywara bus-width = <4>; 136b8bcf0e1SAndre Przywara non-removable; 137b8bcf0e1SAndre Przywara status = "okay"; 1383bc1de8cSIcenowy Zheng 1393bc1de8cSIcenowy Zheng brcmf: wifi@1 { 1403bc1de8cSIcenowy Zheng reg = <1>; 1413bc1de8cSIcenowy Zheng compatible = "brcm,bcm4329-fmac"; 1423bc1de8cSIcenowy Zheng interrupt-parent = <&r_pio>; 1433bc1de8cSIcenowy Zheng interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */ 1443bc1de8cSIcenowy Zheng interrupt-names = "host-wake"; 1453bc1de8cSIcenowy Zheng }; 146b8bcf0e1SAndre Przywara}; 147b8bcf0e1SAndre Przywara 148b8bcf0e1SAndre Przywara&mmc2 { 149b8bcf0e1SAndre Przywara pinctrl-names = "default"; 150b8bcf0e1SAndre Przywara pinctrl-0 = <&mmc2_pins>; 1510ff75efbSIcenowy Zheng vmmc-supply = <®_dcdc1>; 152b8bcf0e1SAndre Przywara bus-width = <8>; 153b8bcf0e1SAndre Przywara non-removable; 154b8bcf0e1SAndre Przywara cap-mmc-hw-reset; 155b8bcf0e1SAndre Przywara status = "okay"; 156b8bcf0e1SAndre Przywara}; 157b8bcf0e1SAndre Przywara 15815ec9598SIcenowy Zheng&ohci1 { 15915ec9598SIcenowy Zheng status = "okay"; 16015ec9598SIcenowy Zheng}; 16115ec9598SIcenowy Zheng 1620ff75efbSIcenowy Zheng&r_rsb { 1630ff75efbSIcenowy Zheng status = "okay"; 1640ff75efbSIcenowy Zheng 1650ff75efbSIcenowy Zheng axp803: pmic@3a3 { 1660ff75efbSIcenowy Zheng compatible = "x-powers,axp803"; 1670ff75efbSIcenowy Zheng reg = <0x3a3>; 1680ff75efbSIcenowy Zheng interrupt-parent = <&r_intc>; 1690ff75efbSIcenowy Zheng interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 1700ff75efbSIcenowy Zheng }; 1710ff75efbSIcenowy Zheng}; 1720ff75efbSIcenowy Zheng 1730ff75efbSIcenowy Zheng#include "axp803.dtsi" 1740ff75efbSIcenowy Zheng 175*36252668SChen-Yu Tsai®_aldo1 { 176*36252668SChen-Yu Tsai /* 177*36252668SChen-Yu Tsai * This regulator also drives the PE pingroup GPIOs, 178*36252668SChen-Yu Tsai * which also controls two LEDs. 179*36252668SChen-Yu Tsai */ 180*36252668SChen-Yu Tsai regulator-always-on; 181*36252668SChen-Yu Tsai regulator-min-microvolt = <2800000>; 182*36252668SChen-Yu Tsai regulator-max-microvolt = <2800000>; 183*36252668SChen-Yu Tsai regulator-name = "afvcc-csi"; 184*36252668SChen-Yu Tsai}; 185*36252668SChen-Yu Tsai 1860ff75efbSIcenowy Zheng®_aldo2 { 1870ff75efbSIcenowy Zheng regulator-always-on; 1880ff75efbSIcenowy Zheng regulator-min-microvolt = <1800000>; 1890ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 1900ff75efbSIcenowy Zheng regulator-name = "vcc-pl"; 1910ff75efbSIcenowy Zheng}; 1920ff75efbSIcenowy Zheng 1930ff75efbSIcenowy Zheng®_aldo3 { 1940ff75efbSIcenowy Zheng regulator-always-on; 1950ff75efbSIcenowy Zheng regulator-min-microvolt = <3000000>; 1960ff75efbSIcenowy Zheng regulator-max-microvolt = <3000000>; 1970ff75efbSIcenowy Zheng regulator-name = "vcc-pll-avcc"; 1980ff75efbSIcenowy Zheng}; 1990ff75efbSIcenowy Zheng 2000ff75efbSIcenowy Zheng®_dc1sw { 201*36252668SChen-Yu Tsai /* 202*36252668SChen-Yu Tsai * This regulator also indirectly drives the PD pingroup GPIOs, 203*36252668SChen-Yu Tsai * which also controls the power LED. 204*36252668SChen-Yu Tsai */ 205*36252668SChen-Yu Tsai regulator-always-on; 2060ff75efbSIcenowy Zheng regulator-name = "vcc-phy"; 2070ff75efbSIcenowy Zheng}; 2080ff75efbSIcenowy Zheng 2090ff75efbSIcenowy Zheng®_dcdc1 { 2100ff75efbSIcenowy Zheng regulator-always-on; 2110ff75efbSIcenowy Zheng regulator-min-microvolt = <3300000>; 2120ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 2130ff75efbSIcenowy Zheng regulator-name = "vcc-3v3"; 2140ff75efbSIcenowy Zheng}; 2150ff75efbSIcenowy Zheng 2160ff75efbSIcenowy Zheng®_dcdc2 { 2170ff75efbSIcenowy Zheng regulator-always-on; 2180ff75efbSIcenowy Zheng regulator-min-microvolt = <1040000>; 2190ff75efbSIcenowy Zheng regulator-max-microvolt = <1300000>; 2200ff75efbSIcenowy Zheng regulator-name = "vdd-cpux"; 2210ff75efbSIcenowy Zheng}; 2220ff75efbSIcenowy Zheng 2230ff75efbSIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */ 2240ff75efbSIcenowy Zheng 2250ff75efbSIcenowy Zheng®_dcdc5 { 2260ff75efbSIcenowy Zheng regulator-always-on; 2270ff75efbSIcenowy Zheng regulator-min-microvolt = <1500000>; 2280ff75efbSIcenowy Zheng regulator-max-microvolt = <1500000>; 2290ff75efbSIcenowy Zheng regulator-name = "vcc-dram"; 2300ff75efbSIcenowy Zheng}; 2310ff75efbSIcenowy Zheng 2320ff75efbSIcenowy Zheng®_dcdc6 { 2330ff75efbSIcenowy Zheng regulator-always-on; 2340ff75efbSIcenowy Zheng regulator-min-microvolt = <1100000>; 2350ff75efbSIcenowy Zheng regulator-max-microvolt = <1100000>; 2360ff75efbSIcenowy Zheng regulator-name = "vdd-sys"; 2370ff75efbSIcenowy Zheng}; 2380ff75efbSIcenowy Zheng 2390ff75efbSIcenowy Zheng®_dldo1 { 2400ff75efbSIcenowy Zheng regulator-min-microvolt = <3300000>; 2410ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 2420ff75efbSIcenowy Zheng regulator-name = "vcc-hdmi-dsi"; 2430ff75efbSIcenowy Zheng}; 2440ff75efbSIcenowy Zheng 2450ff75efbSIcenowy Zheng®_dldo2 { 2460ff75efbSIcenowy Zheng regulator-min-microvolt = <3300000>; 2470ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 2480ff75efbSIcenowy Zheng regulator-name = "vcc-wifi"; 2490ff75efbSIcenowy Zheng}; 2500ff75efbSIcenowy Zheng 2510ff75efbSIcenowy Zheng®_dldo4 { 2520ff75efbSIcenowy Zheng regulator-min-microvolt = <1800000>; 2530ff75efbSIcenowy Zheng regulator-max-microvolt = <3300000>; 2540ff75efbSIcenowy Zheng regulator-name = "vcc-wifi-io"; 2550ff75efbSIcenowy Zheng}; 2560ff75efbSIcenowy Zheng 2570ff75efbSIcenowy Zheng®_eldo1 { 2580ff75efbSIcenowy Zheng regulator-min-microvolt = <1800000>; 2590ff75efbSIcenowy Zheng regulator-max-microvolt = <1800000>; 2600ff75efbSIcenowy Zheng regulator-name = "cpvdd"; 2610ff75efbSIcenowy Zheng}; 2620ff75efbSIcenowy Zheng 2630ff75efbSIcenowy Zheng®_fldo1 { 2640ff75efbSIcenowy Zheng regulator-min-microvolt = <1200000>; 2650ff75efbSIcenowy Zheng regulator-max-microvolt = <1200000>; 2660ff75efbSIcenowy Zheng regulator-name = "vcc-1v2-hsic"; 2670ff75efbSIcenowy Zheng}; 2680ff75efbSIcenowy Zheng 2690ff75efbSIcenowy Zheng/* 2700ff75efbSIcenowy Zheng * The A64 chip cannot work without this regulator off, although 2710ff75efbSIcenowy Zheng * it seems to be only driving the AR100 core. 2720ff75efbSIcenowy Zheng * Maybe we don't still know well about CPUs domain. 2730ff75efbSIcenowy Zheng */ 2740ff75efbSIcenowy Zheng®_fldo2 { 2750ff75efbSIcenowy Zheng regulator-always-on; 2760ff75efbSIcenowy Zheng regulator-min-microvolt = <1100000>; 2770ff75efbSIcenowy Zheng regulator-max-microvolt = <1100000>; 2780ff75efbSIcenowy Zheng regulator-name = "vdd-cpus"; 2790ff75efbSIcenowy Zheng}; 2800ff75efbSIcenowy Zheng 2810ff75efbSIcenowy Zheng®_rtc_ldo { 2820ff75efbSIcenowy Zheng regulator-name = "vcc-rtc"; 2830ff75efbSIcenowy Zheng}; 2840ff75efbSIcenowy Zheng 285b8bcf0e1SAndre Przywara&uart0 { 286b8bcf0e1SAndre Przywara pinctrl-names = "default"; 287b8bcf0e1SAndre Przywara pinctrl-0 = <&uart0_pins_a>; 288b8bcf0e1SAndre Przywara status = "okay"; 289b8bcf0e1SAndre Przywara}; 290b8bcf0e1SAndre Przywara 291b8bcf0e1SAndre Przywara&uart1 { 292b8bcf0e1SAndre Przywara pinctrl-names = "default"; 293b8bcf0e1SAndre Przywara pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; 294b8bcf0e1SAndre Przywara status = "okay"; 295b8bcf0e1SAndre Przywara}; 29615ec9598SIcenowy Zheng 29715ec9598SIcenowy Zheng&usbphy { 29815ec9598SIcenowy Zheng status = "okay"; 29915ec9598SIcenowy Zheng}; 300