xref: /openbmc/linux/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts (revision 0ff75efbc9144820c39b9ec38286b909154770e1)
1b8bcf0e1SAndre Przywara/*
2b8bcf0e1SAndre Przywara * Copyright (c) 2016 ARM Ltd.
3b8bcf0e1SAndre Przywara *
4b8bcf0e1SAndre Przywara * This file is dual-licensed: you can use it either under the terms
5b8bcf0e1SAndre Przywara * of the GPL or the X11 license, at your option. Note that this dual
6b8bcf0e1SAndre Przywara * licensing only applies to this file, and not this project as a
7b8bcf0e1SAndre Przywara * whole.
8b8bcf0e1SAndre Przywara *
9b8bcf0e1SAndre Przywara *  a) This library is free software; you can redistribute it and/or
10b8bcf0e1SAndre Przywara *     modify it under the terms of the GNU General Public License as
11b8bcf0e1SAndre Przywara *     published by the Free Software Foundation; either version 2 of the
12b8bcf0e1SAndre Przywara *     License, or (at your option) any later version.
13b8bcf0e1SAndre Przywara *
14b8bcf0e1SAndre Przywara *     This library is distributed in the hope that it will be useful,
15b8bcf0e1SAndre Przywara *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16b8bcf0e1SAndre Przywara *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17b8bcf0e1SAndre Przywara *     GNU General Public License for more details.
18b8bcf0e1SAndre Przywara *
19b8bcf0e1SAndre Przywara * Or, alternatively,
20b8bcf0e1SAndre Przywara *
21b8bcf0e1SAndre Przywara *  b) Permission is hereby granted, free of charge, to any person
22b8bcf0e1SAndre Przywara *     obtaining a copy of this software and associated documentation
23b8bcf0e1SAndre Przywara *     files (the "Software"), to deal in the Software without
24b8bcf0e1SAndre Przywara *     restriction, including without limitation the rights to use,
25b8bcf0e1SAndre Przywara *     copy, modify, merge, publish, distribute, sublicense, and/or
26b8bcf0e1SAndre Przywara *     sell copies of the Software, and to permit persons to whom the
27b8bcf0e1SAndre Przywara *     Software is furnished to do so, subject to the following
28b8bcf0e1SAndre Przywara *     conditions:
29b8bcf0e1SAndre Przywara *
30b8bcf0e1SAndre Przywara *     The above copyright notice and this permission notice shall be
31b8bcf0e1SAndre Przywara *     included in all copies or substantial portions of the Software.
32b8bcf0e1SAndre Przywara *
33b8bcf0e1SAndre Przywara *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34b8bcf0e1SAndre Przywara *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35b8bcf0e1SAndre Przywara *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36b8bcf0e1SAndre Przywara *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37b8bcf0e1SAndre Przywara *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38b8bcf0e1SAndre Przywara *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39b8bcf0e1SAndre Przywara *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40b8bcf0e1SAndre Przywara *     OTHER DEALINGS IN THE SOFTWARE.
41b8bcf0e1SAndre Przywara */
42b8bcf0e1SAndre Przywara
43b8bcf0e1SAndre Przywara/dts-v1/;
44b8bcf0e1SAndre Przywara
45b8bcf0e1SAndre Przywara#include "sun50i-a64.dtsi"
46b8bcf0e1SAndre Przywara
47b8bcf0e1SAndre Przywara#include <dt-bindings/gpio/gpio.h>
48b8bcf0e1SAndre Przywara
49b8bcf0e1SAndre Przywara/ {
50b8bcf0e1SAndre Przywara	model = "BananaPi-M64";
51b8bcf0e1SAndre Przywara	compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
52b8bcf0e1SAndre Przywara
53b8bcf0e1SAndre Przywara	aliases {
54b8bcf0e1SAndre Przywara		serial0 = &uart0;
55b8bcf0e1SAndre Przywara		serial1 = &uart1;
56b8bcf0e1SAndre Przywara	};
57b8bcf0e1SAndre Przywara
58b8bcf0e1SAndre Przywara	chosen {
59b8bcf0e1SAndre Przywara		stdout-path = "serial0:115200n8";
60b8bcf0e1SAndre Przywara	};
61b8bcf0e1SAndre Przywara};
62b8bcf0e1SAndre Przywara
6315ec9598SIcenowy Zheng&ehci1 {
6415ec9598SIcenowy Zheng	status = "okay";
6515ec9598SIcenowy Zheng};
6615ec9598SIcenowy Zheng
67e7295499SCorentin Labbe&emac {
68e7295499SCorentin Labbe	pinctrl-names = "default";
69e7295499SCorentin Labbe	pinctrl-0 = <&rgmii_pins>;
70e7295499SCorentin Labbe	phy-mode = "rgmii";
71e7295499SCorentin Labbe	phy-handle = <&ext_rgmii_phy>;
72*0ff75efbSIcenowy Zheng	phy-supply = <&reg_dc1sw>;
73e7295499SCorentin Labbe	status = "okay";
74e7295499SCorentin Labbe};
75e7295499SCorentin Labbe
76b8bcf0e1SAndre Przywara&i2c1 {
77b8bcf0e1SAndre Przywara	pinctrl-names = "default";
78b8bcf0e1SAndre Przywara	pinctrl-0 = <&i2c1_pins>;
79b8bcf0e1SAndre Przywara	status = "okay";
80b8bcf0e1SAndre Przywara};
81b8bcf0e1SAndre Przywara
82b8bcf0e1SAndre Przywara&i2c1_pins {
83b8bcf0e1SAndre Przywara	bias-pull-up;
84b8bcf0e1SAndre Przywara};
85b8bcf0e1SAndre Przywara
86e7295499SCorentin Labbe&mdio {
87e7295499SCorentin Labbe	ext_rgmii_phy: ethernet-phy@1 {
88e7295499SCorentin Labbe		compatible = "ethernet-phy-ieee802.3-c22";
89e7295499SCorentin Labbe		reg = <1>;
90e7295499SCorentin Labbe	};
91e7295499SCorentin Labbe};
92e7295499SCorentin Labbe
93b8bcf0e1SAndre Przywara&mmc0 {
94b8bcf0e1SAndre Przywara	pinctrl-names = "default";
95b8bcf0e1SAndre Przywara	pinctrl-0 = <&mmc0_pins>;
96*0ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dcdc1>;
97b8bcf0e1SAndre Przywara	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
98b8bcf0e1SAndre Przywara	cd-inverted;
99b8bcf0e1SAndre Przywara	disable-wp;
100b8bcf0e1SAndre Przywara	bus-width = <4>;
101b8bcf0e1SAndre Przywara	status = "okay";
102b8bcf0e1SAndre Przywara};
103b8bcf0e1SAndre Przywara
104b8bcf0e1SAndre Przywara&mmc1 {
105b8bcf0e1SAndre Przywara	pinctrl-names = "default";
106b8bcf0e1SAndre Przywara	pinctrl-0 = <&mmc1_pins>;
107*0ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dldo2>;
108*0ff75efbSIcenowy Zheng	vqmmc-supply = <&reg_dldo4>;
109b8bcf0e1SAndre Przywara	bus-width = <4>;
110b8bcf0e1SAndre Przywara	non-removable;
111b8bcf0e1SAndre Przywara	status = "okay";
112b8bcf0e1SAndre Przywara};
113b8bcf0e1SAndre Przywara
114b8bcf0e1SAndre Przywara&mmc2 {
115b8bcf0e1SAndre Przywara	pinctrl-names = "default";
116b8bcf0e1SAndre Przywara	pinctrl-0 = <&mmc2_pins>;
117*0ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dcdc1>;
118b8bcf0e1SAndre Przywara	bus-width = <8>;
119b8bcf0e1SAndre Przywara	non-removable;
120b8bcf0e1SAndre Przywara	cap-mmc-hw-reset;
121b8bcf0e1SAndre Przywara	status = "okay";
122b8bcf0e1SAndre Przywara};
123b8bcf0e1SAndre Przywara
12415ec9598SIcenowy Zheng&ohci1 {
12515ec9598SIcenowy Zheng	status = "okay";
12615ec9598SIcenowy Zheng};
12715ec9598SIcenowy Zheng
128*0ff75efbSIcenowy Zheng&r_rsb {
129*0ff75efbSIcenowy Zheng	status = "okay";
130*0ff75efbSIcenowy Zheng
131*0ff75efbSIcenowy Zheng	axp803: pmic@3a3 {
132*0ff75efbSIcenowy Zheng		compatible = "x-powers,axp803";
133*0ff75efbSIcenowy Zheng		reg = <0x3a3>;
134*0ff75efbSIcenowy Zheng		interrupt-parent = <&r_intc>;
135*0ff75efbSIcenowy Zheng		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
136*0ff75efbSIcenowy Zheng	};
137*0ff75efbSIcenowy Zheng};
138*0ff75efbSIcenowy Zheng
139*0ff75efbSIcenowy Zheng#include "axp803.dtsi"
140*0ff75efbSIcenowy Zheng
141*0ff75efbSIcenowy Zheng&reg_aldo2 {
142*0ff75efbSIcenowy Zheng	regulator-always-on;
143*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
144*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
145*0ff75efbSIcenowy Zheng	regulator-name = "vcc-pl";
146*0ff75efbSIcenowy Zheng};
147*0ff75efbSIcenowy Zheng
148*0ff75efbSIcenowy Zheng&reg_aldo3 {
149*0ff75efbSIcenowy Zheng	regulator-always-on;
150*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <3000000>;
151*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <3000000>;
152*0ff75efbSIcenowy Zheng	regulator-name = "vcc-pll-avcc";
153*0ff75efbSIcenowy Zheng};
154*0ff75efbSIcenowy Zheng
155*0ff75efbSIcenowy Zheng&reg_dc1sw {
156*0ff75efbSIcenowy Zheng	regulator-name = "vcc-phy";
157*0ff75efbSIcenowy Zheng};
158*0ff75efbSIcenowy Zheng
159*0ff75efbSIcenowy Zheng&reg_dcdc1 {
160*0ff75efbSIcenowy Zheng	regulator-always-on;
161*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
162*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
163*0ff75efbSIcenowy Zheng	regulator-name = "vcc-3v3";
164*0ff75efbSIcenowy Zheng};
165*0ff75efbSIcenowy Zheng
166*0ff75efbSIcenowy Zheng&reg_dcdc2 {
167*0ff75efbSIcenowy Zheng	regulator-always-on;
168*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1040000>;
169*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <1300000>;
170*0ff75efbSIcenowy Zheng	regulator-name = "vdd-cpux";
171*0ff75efbSIcenowy Zheng};
172*0ff75efbSIcenowy Zheng
173*0ff75efbSIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */
174*0ff75efbSIcenowy Zheng
175*0ff75efbSIcenowy Zheng&reg_dcdc5 {
176*0ff75efbSIcenowy Zheng	regulator-always-on;
177*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1500000>;
178*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <1500000>;
179*0ff75efbSIcenowy Zheng	regulator-name = "vcc-dram";
180*0ff75efbSIcenowy Zheng};
181*0ff75efbSIcenowy Zheng
182*0ff75efbSIcenowy Zheng&reg_dcdc6 {
183*0ff75efbSIcenowy Zheng	regulator-always-on;
184*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1100000>;
185*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <1100000>;
186*0ff75efbSIcenowy Zheng	regulator-name = "vdd-sys";
187*0ff75efbSIcenowy Zheng};
188*0ff75efbSIcenowy Zheng
189*0ff75efbSIcenowy Zheng&reg_dldo1 {
190*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
191*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
192*0ff75efbSIcenowy Zheng	regulator-name = "vcc-hdmi-dsi";
193*0ff75efbSIcenowy Zheng};
194*0ff75efbSIcenowy Zheng
195*0ff75efbSIcenowy Zheng&reg_dldo2 {
196*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
197*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
198*0ff75efbSIcenowy Zheng	regulator-name = "vcc-wifi";
199*0ff75efbSIcenowy Zheng};
200*0ff75efbSIcenowy Zheng
201*0ff75efbSIcenowy Zheng&reg_dldo4 {
202*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
203*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
204*0ff75efbSIcenowy Zheng	regulator-name = "vcc-wifi-io";
205*0ff75efbSIcenowy Zheng};
206*0ff75efbSIcenowy Zheng
207*0ff75efbSIcenowy Zheng&reg_eldo1 {
208*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
209*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <1800000>;
210*0ff75efbSIcenowy Zheng	regulator-name = "cpvdd";
211*0ff75efbSIcenowy Zheng};
212*0ff75efbSIcenowy Zheng
213*0ff75efbSIcenowy Zheng&reg_fldo1 {
214*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1200000>;
215*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <1200000>;
216*0ff75efbSIcenowy Zheng	regulator-name = "vcc-1v2-hsic";
217*0ff75efbSIcenowy Zheng};
218*0ff75efbSIcenowy Zheng
219*0ff75efbSIcenowy Zheng/*
220*0ff75efbSIcenowy Zheng * The A64 chip cannot work without this regulator off, although
221*0ff75efbSIcenowy Zheng * it seems to be only driving the AR100 core.
222*0ff75efbSIcenowy Zheng * Maybe we don't still know well about CPUs domain.
223*0ff75efbSIcenowy Zheng */
224*0ff75efbSIcenowy Zheng&reg_fldo2 {
225*0ff75efbSIcenowy Zheng	regulator-always-on;
226*0ff75efbSIcenowy Zheng	regulator-min-microvolt = <1100000>;
227*0ff75efbSIcenowy Zheng	regulator-max-microvolt = <1100000>;
228*0ff75efbSIcenowy Zheng	regulator-name = "vdd-cpus";
229*0ff75efbSIcenowy Zheng};
230*0ff75efbSIcenowy Zheng
231*0ff75efbSIcenowy Zheng&reg_rtc_ldo {
232*0ff75efbSIcenowy Zheng	regulator-name = "vcc-rtc";
233*0ff75efbSIcenowy Zheng};
234*0ff75efbSIcenowy Zheng
235b8bcf0e1SAndre Przywara&uart0 {
236b8bcf0e1SAndre Przywara	pinctrl-names = "default";
237b8bcf0e1SAndre Przywara	pinctrl-0 = <&uart0_pins_a>;
238b8bcf0e1SAndre Przywara	status = "okay";
239b8bcf0e1SAndre Przywara};
240b8bcf0e1SAndre Przywara
241b8bcf0e1SAndre Przywara&uart1 {
242b8bcf0e1SAndre Przywara	pinctrl-names = "default";
243b8bcf0e1SAndre Przywara	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
244b8bcf0e1SAndre Przywara	status = "okay";
245b8bcf0e1SAndre Przywara};
24615ec9598SIcenowy Zheng
24715ec9598SIcenowy Zheng&usbphy {
24815ec9598SIcenowy Zheng	status = "okay";
24915ec9598SIcenowy Zheng};
250