1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_GTDT if ACPI 6 select ACPI_IORT if ACPI 7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 8 select ACPI_MCFG if (ACPI && PCI) 9 select ACPI_SPCR_TABLE if ACPI 10 select ACPI_PPTT if ACPI 11 select ARCH_CLOCKSOURCE_DATA 12 select ARCH_HAS_DEBUG_VIRTUAL 13 select ARCH_HAS_DEVMEM_IS_ALLOWED 14 select ARCH_HAS_DMA_COHERENT_TO_PFN 15 select ARCH_HAS_DMA_MMAP_PGPROT 16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 17 select ARCH_HAS_ELF_RANDOMIZE 18 select ARCH_HAS_FAST_MULTIPLIER 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA 22 select ARCH_HAS_KCOV 23 select ARCH_HAS_MEMBARRIER_SYNC_CORE 24 select ARCH_HAS_PTE_SPECIAL 25 select ARCH_HAS_SET_MEMORY 26 select ARCH_HAS_SG_CHAIN 27 select ARCH_HAS_STRICT_KERNEL_RWX 28 select ARCH_HAS_STRICT_MODULE_RWX 29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 30 select ARCH_HAS_SYNC_DMA_FOR_CPU 31 select ARCH_HAS_SYSCALL_WRAPPER 32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 33 select ARCH_HAVE_NMI_SAFE_CMPXCHG 34 select ARCH_INLINE_READ_LOCK if !PREEMPT 35 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT 36 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT 37 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT 38 select ARCH_INLINE_READ_UNLOCK if !PREEMPT 39 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT 40 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT 41 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT 42 select ARCH_INLINE_WRITE_LOCK if !PREEMPT 43 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT 44 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT 45 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT 46 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT 47 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT 48 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT 49 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT 50 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT 51 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT 52 select ARCH_INLINE_SPIN_LOCK if !PREEMPT 53 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT 54 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT 55 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT 56 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT 57 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT 58 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT 59 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT 60 select ARCH_USE_CMPXCHG_LOCKREF 61 select ARCH_USE_QUEUED_RWLOCKS 62 select ARCH_USE_QUEUED_SPINLOCKS 63 select ARCH_SUPPORTS_MEMORY_FAILURE 64 select ARCH_SUPPORTS_ATOMIC_RMW 65 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG 66 select ARCH_SUPPORTS_NUMA_BALANCING 67 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 68 select ARCH_WANT_FRAME_POINTERS 69 select ARCH_HAS_UBSAN_SANITIZE_ALL 70 select ARM_AMBA 71 select ARM_ARCH_TIMER 72 select ARM_GIC 73 select AUDIT_ARCH_COMPAT_GENERIC 74 select ARM_GIC_V2M if PCI 75 select ARM_GIC_V3 76 select ARM_GIC_V3_ITS if PCI 77 select ARM_PSCI_FW 78 select BUILDTIME_EXTABLE_SORT 79 select CLONE_BACKWARDS 80 select COMMON_CLK 81 select CPU_PM if (SUSPEND || CPU_IDLE) 82 select CRC32 83 select DCACHE_WORD_ACCESS 84 select DMA_DIRECT_OPS 85 select EDAC_SUPPORT 86 select FRAME_POINTER 87 select GENERIC_ALLOCATOR 88 select GENERIC_ARCH_TOPOLOGY 89 select GENERIC_CLOCKEVENTS 90 select GENERIC_CLOCKEVENTS_BROADCAST 91 select GENERIC_CPU_AUTOPROBE 92 select GENERIC_EARLY_IOREMAP 93 select GENERIC_IDLE_POLL_SETUP 94 select GENERIC_IRQ_MULTI_HANDLER 95 select GENERIC_IRQ_PROBE 96 select GENERIC_IRQ_SHOW 97 select GENERIC_IRQ_SHOW_LEVEL 98 select GENERIC_PCI_IOMAP 99 select GENERIC_SCHED_CLOCK 100 select GENERIC_SMP_IDLE_THREAD 101 select GENERIC_STRNCPY_FROM_USER 102 select GENERIC_STRNLEN_USER 103 select GENERIC_TIME_VSYSCALL 104 select HANDLE_DOMAIN_IRQ 105 select HARDIRQS_SW_RESEND 106 select HAVE_ACPI_APEI if (ACPI && EFI) 107 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 108 select HAVE_ARCH_AUDITSYSCALL 109 select HAVE_ARCH_BITREVERSE 110 select HAVE_ARCH_HUGE_VMAP 111 select HAVE_ARCH_JUMP_LABEL 112 select HAVE_ARCH_JUMP_LABEL_RELATIVE 113 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 114 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 115 select HAVE_ARCH_KGDB 116 select HAVE_ARCH_MMAP_RND_BITS 117 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 118 select HAVE_ARCH_PREL32_RELOCATIONS 119 select HAVE_ARCH_SECCOMP_FILTER 120 select HAVE_ARCH_STACKLEAK 121 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 122 select HAVE_ARCH_TRACEHOOK 123 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 124 select HAVE_ARCH_VMAP_STACK 125 select HAVE_ARM_SMCCC 126 select HAVE_EBPF_JIT 127 select HAVE_C_RECORDMCOUNT 128 select HAVE_CMPXCHG_DOUBLE 129 select HAVE_CMPXCHG_LOCAL 130 select HAVE_CONTEXT_TRACKING 131 select HAVE_DEBUG_BUGVERBOSE 132 select HAVE_DEBUG_KMEMLEAK 133 select HAVE_DMA_CONTIGUOUS 134 select HAVE_DYNAMIC_FTRACE 135 select HAVE_EFFICIENT_UNALIGNED_ACCESS 136 select HAVE_FTRACE_MCOUNT_RECORD 137 select HAVE_FUNCTION_TRACER 138 select HAVE_FUNCTION_GRAPH_TRACER 139 select HAVE_GCC_PLUGINS 140 select HAVE_GENERIC_DMA_COHERENT 141 select HAVE_HW_BREAKPOINT if PERF_EVENTS 142 select HAVE_IRQ_TIME_ACCOUNTING 143 select HAVE_MEMBLOCK_NODE_MAP if NUMA 144 select HAVE_NMI 145 select HAVE_PATA_PLATFORM 146 select HAVE_PERF_EVENTS 147 select HAVE_PERF_REGS 148 select HAVE_PERF_USER_STACK_DUMP 149 select HAVE_REGS_AND_STACK_ACCESS_API 150 select HAVE_RCU_TABLE_FREE 151 select HAVE_RCU_TABLE_INVALIDATE 152 select HAVE_RSEQ 153 select HAVE_STACKPROTECTOR 154 select HAVE_SYSCALL_TRACEPOINTS 155 select HAVE_KPROBES 156 select HAVE_KRETPROBES 157 select IOMMU_DMA if IOMMU_SUPPORT 158 select IRQ_DOMAIN 159 select IRQ_FORCED_THREADING 160 select MODULES_USE_ELF_RELA 161 select MULTI_IRQ_HANDLER 162 select NEED_DMA_MAP_STATE 163 select NEED_SG_DMA_LENGTH 164 select OF 165 select OF_EARLY_FLATTREE 166 select OF_RESERVED_MEM 167 select PCI_ECAM if (ACPI && PCI) 168 select POWER_RESET 169 select POWER_SUPPLY 170 select REFCOUNT_FULL 171 select SPARSE_IRQ 172 select SWIOTLB 173 select SYSCTL_EXCEPTION_TRACE 174 select THREAD_INFO_IN_TASK 175 help 176 ARM 64-bit (AArch64) Linux support. 177 178config 64BIT 179 def_bool y 180 181config MMU 182 def_bool y 183 184config ARM64_PAGE_SHIFT 185 int 186 default 16 if ARM64_64K_PAGES 187 default 14 if ARM64_16K_PAGES 188 default 12 189 190config ARM64_CONT_SHIFT 191 int 192 default 5 if ARM64_64K_PAGES 193 default 7 if ARM64_16K_PAGES 194 default 4 195 196config ARCH_MMAP_RND_BITS_MIN 197 default 14 if ARM64_64K_PAGES 198 default 16 if ARM64_16K_PAGES 199 default 18 200 201# max bits determined by the following formula: 202# VA_BITS - PAGE_SHIFT - 3 203config ARCH_MMAP_RND_BITS_MAX 204 default 19 if ARM64_VA_BITS=36 205 default 24 if ARM64_VA_BITS=39 206 default 27 if ARM64_VA_BITS=42 207 default 30 if ARM64_VA_BITS=47 208 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 209 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 210 default 33 if ARM64_VA_BITS=48 211 default 14 if ARM64_64K_PAGES 212 default 16 if ARM64_16K_PAGES 213 default 18 214 215config ARCH_MMAP_RND_COMPAT_BITS_MIN 216 default 7 if ARM64_64K_PAGES 217 default 9 if ARM64_16K_PAGES 218 default 11 219 220config ARCH_MMAP_RND_COMPAT_BITS_MAX 221 default 16 222 223config NO_IOPORT_MAP 224 def_bool y if !PCI 225 226config STACKTRACE_SUPPORT 227 def_bool y 228 229config ILLEGAL_POINTER_VALUE 230 hex 231 default 0xdead000000000000 232 233config LOCKDEP_SUPPORT 234 def_bool y 235 236config TRACE_IRQFLAGS_SUPPORT 237 def_bool y 238 239config RWSEM_XCHGADD_ALGORITHM 240 def_bool y 241 242config GENERIC_BUG 243 def_bool y 244 depends on BUG 245 246config GENERIC_BUG_RELATIVE_POINTERS 247 def_bool y 248 depends on GENERIC_BUG 249 250config GENERIC_HWEIGHT 251 def_bool y 252 253config GENERIC_CSUM 254 def_bool y 255 256config GENERIC_CALIBRATE_DELAY 257 def_bool y 258 259config ZONE_DMA32 260 def_bool y 261 262config HAVE_GENERIC_GUP 263 def_bool y 264 265config ARCH_ENABLE_MEMORY_HOTPLUG 266 def_bool y 267 268config SMP 269 def_bool y 270 271config KERNEL_MODE_NEON 272 def_bool y 273 274config FIX_EARLYCON_MEM 275 def_bool y 276 277config PGTABLE_LEVELS 278 int 279 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 280 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 281 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52) 282 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 283 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 284 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 285 286config ARCH_SUPPORTS_UPROBES 287 def_bool y 288 289config ARCH_PROC_KCORE_TEXT 290 def_bool y 291 292source "arch/arm64/Kconfig.platforms" 293 294menu "Bus support" 295 296config PCI 297 bool "PCI support" 298 help 299 This feature enables support for PCI bus system. If you say Y 300 here, the kernel will include drivers and infrastructure code 301 to support PCI bus devices. 302 303config PCI_DOMAINS 304 def_bool PCI 305 306config PCI_DOMAINS_GENERIC 307 def_bool PCI 308 309config PCI_SYSCALL 310 def_bool PCI 311 312source "drivers/pci/Kconfig" 313 314endmenu 315 316menu "Kernel Features" 317 318menu "ARM errata workarounds via the alternatives framework" 319 320config ARM64_WORKAROUND_CLEAN_CACHE 321 def_bool n 322 323config ARM64_ERRATUM_826319 324 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 325 default y 326 select ARM64_WORKAROUND_CLEAN_CACHE 327 help 328 This option adds an alternative code sequence to work around ARM 329 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 330 AXI master interface and an L2 cache. 331 332 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 333 and is unable to accept a certain write via this interface, it will 334 not progress on read data presented on the read data channel and the 335 system can deadlock. 336 337 The workaround promotes data cache clean instructions to 338 data cache clean-and-invalidate. 339 Please note that this does not necessarily enable the workaround, 340 as it depends on the alternative framework, which will only patch 341 the kernel if an affected CPU is detected. 342 343 If unsure, say Y. 344 345config ARM64_ERRATUM_827319 346 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 347 default y 348 select ARM64_WORKAROUND_CLEAN_CACHE 349 help 350 This option adds an alternative code sequence to work around ARM 351 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 352 master interface and an L2 cache. 353 354 Under certain conditions this erratum can cause a clean line eviction 355 to occur at the same time as another transaction to the same address 356 on the AMBA 5 CHI interface, which can cause data corruption if the 357 interconnect reorders the two transactions. 358 359 The workaround promotes data cache clean instructions to 360 data cache clean-and-invalidate. 361 Please note that this does not necessarily enable the workaround, 362 as it depends on the alternative framework, which will only patch 363 the kernel if an affected CPU is detected. 364 365 If unsure, say Y. 366 367config ARM64_ERRATUM_824069 368 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 369 default y 370 select ARM64_WORKAROUND_CLEAN_CACHE 371 help 372 This option adds an alternative code sequence to work around ARM 373 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 374 to a coherent interconnect. 375 376 If a Cortex-A53 processor is executing a store or prefetch for 377 write instruction at the same time as a processor in another 378 cluster is executing a cache maintenance operation to the same 379 address, then this erratum might cause a clean cache line to be 380 incorrectly marked as dirty. 381 382 The workaround promotes data cache clean instructions to 383 data cache clean-and-invalidate. 384 Please note that this option does not necessarily enable the 385 workaround, as it depends on the alternative framework, which will 386 only patch the kernel if an affected CPU is detected. 387 388 If unsure, say Y. 389 390config ARM64_ERRATUM_819472 391 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 392 default y 393 select ARM64_WORKAROUND_CLEAN_CACHE 394 help 395 This option adds an alternative code sequence to work around ARM 396 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 397 present when it is connected to a coherent interconnect. 398 399 If the processor is executing a load and store exclusive sequence at 400 the same time as a processor in another cluster is executing a cache 401 maintenance operation to the same address, then this erratum might 402 cause data corruption. 403 404 The workaround promotes data cache clean instructions to 405 data cache clean-and-invalidate. 406 Please note that this does not necessarily enable the workaround, 407 as it depends on the alternative framework, which will only patch 408 the kernel if an affected CPU is detected. 409 410 If unsure, say Y. 411 412config ARM64_ERRATUM_832075 413 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 414 default y 415 help 416 This option adds an alternative code sequence to work around ARM 417 erratum 832075 on Cortex-A57 parts up to r1p2. 418 419 Affected Cortex-A57 parts might deadlock when exclusive load/store 420 instructions to Write-Back memory are mixed with Device loads. 421 422 The workaround is to promote device loads to use Load-Acquire 423 semantics. 424 Please note that this does not necessarily enable the workaround, 425 as it depends on the alternative framework, which will only patch 426 the kernel if an affected CPU is detected. 427 428 If unsure, say Y. 429 430config ARM64_ERRATUM_834220 431 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 432 depends on KVM 433 default y 434 help 435 This option adds an alternative code sequence to work around ARM 436 erratum 834220 on Cortex-A57 parts up to r1p2. 437 438 Affected Cortex-A57 parts might report a Stage 2 translation 439 fault as the result of a Stage 1 fault for load crossing a 440 page boundary when there is a permission or device memory 441 alignment fault at Stage 1 and a translation fault at Stage 2. 442 443 The workaround is to verify that the Stage 1 translation 444 doesn't generate a fault before handling the Stage 2 fault. 445 Please note that this does not necessarily enable the workaround, 446 as it depends on the alternative framework, which will only patch 447 the kernel if an affected CPU is detected. 448 449 If unsure, say Y. 450 451config ARM64_ERRATUM_845719 452 bool "Cortex-A53: 845719: a load might read incorrect data" 453 depends on COMPAT 454 default y 455 help 456 This option adds an alternative code sequence to work around ARM 457 erratum 845719 on Cortex-A53 parts up to r0p4. 458 459 When running a compat (AArch32) userspace on an affected Cortex-A53 460 part, a load at EL0 from a virtual address that matches the bottom 32 461 bits of the virtual address used by a recent load at (AArch64) EL1 462 might return incorrect data. 463 464 The workaround is to write the contextidr_el1 register on exception 465 return to a 32-bit task. 466 Please note that this does not necessarily enable the workaround, 467 as it depends on the alternative framework, which will only patch 468 the kernel if an affected CPU is detected. 469 470 If unsure, say Y. 471 472config ARM64_ERRATUM_843419 473 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 474 default y 475 select ARM64_MODULE_PLTS if MODULES 476 help 477 This option links the kernel with '--fix-cortex-a53-843419' and 478 enables PLT support to replace certain ADRP instructions, which can 479 cause subsequent memory accesses to use an incorrect address on 480 Cortex-A53 parts up to r0p4. 481 482 If unsure, say Y. 483 484config ARM64_ERRATUM_1024718 485 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 486 default y 487 help 488 This option adds work around for Arm Cortex-A55 Erratum 1024718. 489 490 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect 491 update of the hardware dirty bit when the DBM/AP bits are updated 492 without a break-before-make. The work around is to disable the usage 493 of hardware DBM locally on the affected cores. CPUs not affected by 494 erratum will continue to use the feature. 495 496 If unsure, say Y. 497 498config ARM64_ERRATUM_1188873 499 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 500 default y 501 select ARM_ARCH_TIMER_OOL_WORKAROUND 502 help 503 This option adds work arounds for ARM Cortex-A76 erratum 1188873 504 505 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause 506 register corruption when accessing the timer registers from 507 AArch32 userspace. 508 509 If unsure, say Y. 510 511config ARM64_ERRATUM_1165522 512 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 513 default y 514 help 515 This option adds work arounds for ARM Cortex-A76 erratum 1165522 516 517 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 518 corrupted TLBs by speculating an AT instruction during a guest 519 context switch. 520 521 If unsure, say Y. 522 523config ARM64_ERRATUM_1286807 524 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 525 default y 526 select ARM64_WORKAROUND_REPEAT_TLBI 527 help 528 This option adds workaround for ARM Cortex-A76 erratum 1286807 529 530 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 531 address for a cacheable mapping of a location is being 532 accessed by a core while another core is remapping the virtual 533 address to a new physical page using the recommended 534 break-before-make sequence, then under very rare circumstances 535 TLBI+DSB completes before a read using the translation being 536 invalidated has been observed by other observers. The 537 workaround repeats the TLBI+DSB operation. 538 539 If unsure, say Y. 540 541config CAVIUM_ERRATUM_22375 542 bool "Cavium erratum 22375, 24313" 543 default y 544 help 545 Enable workaround for erratum 22375, 24313. 546 547 This implements two gicv3-its errata workarounds for ThunderX. Both 548 with small impact affecting only ITS table allocation. 549 550 erratum 22375: only alloc 8MB table size 551 erratum 24313: ignore memory access type 552 553 The fixes are in ITS initialization and basically ignore memory access 554 type and table size provided by the TYPER and BASER registers. 555 556 If unsure, say Y. 557 558config CAVIUM_ERRATUM_23144 559 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 560 depends on NUMA 561 default y 562 help 563 ITS SYNC command hang for cross node io and collections/cpu mapping. 564 565 If unsure, say Y. 566 567config CAVIUM_ERRATUM_23154 568 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 569 default y 570 help 571 The gicv3 of ThunderX requires a modified version for 572 reading the IAR status to ensure data synchronization 573 (access to icc_iar1_el1 is not sync'ed before and after). 574 575 If unsure, say Y. 576 577config CAVIUM_ERRATUM_27456 578 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 579 default y 580 help 581 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 582 instructions may cause the icache to become corrupted if it 583 contains data for a non-current ASID. The fix is to 584 invalidate the icache when changing the mm context. 585 586 If unsure, say Y. 587 588config CAVIUM_ERRATUM_30115 589 bool "Cavium erratum 30115: Guest may disable interrupts in host" 590 default y 591 help 592 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 593 1.2, and T83 Pass 1.0, KVM guest execution may disable 594 interrupts in host. Trapping both GICv3 group-0 and group-1 595 accesses sidesteps the issue. 596 597 If unsure, say Y. 598 599config QCOM_FALKOR_ERRATUM_1003 600 bool "Falkor E1003: Incorrect translation due to ASID change" 601 default y 602 help 603 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 604 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 605 in TTBR1_EL1, this situation only occurs in the entry trampoline and 606 then only for entries in the walk cache, since the leaf translation 607 is unchanged. Work around the erratum by invalidating the walk cache 608 entries for the trampoline before entering the kernel proper. 609 610config ARM64_WORKAROUND_REPEAT_TLBI 611 bool 612 help 613 Enable the repeat TLBI workaround for Falkor erratum 1009 and 614 Cortex-A76 erratum 1286807. 615 616config QCOM_FALKOR_ERRATUM_1009 617 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 618 default y 619 select ARM64_WORKAROUND_REPEAT_TLBI 620 help 621 On Falkor v1, the CPU may prematurely complete a DSB following a 622 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 623 one more time to fix the issue. 624 625 If unsure, say Y. 626 627config QCOM_QDF2400_ERRATUM_0065 628 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 629 default y 630 help 631 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 632 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 633 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 634 635 If unsure, say Y. 636 637config SOCIONEXT_SYNQUACER_PREITS 638 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 639 default y 640 help 641 Socionext Synquacer SoCs implement a separate h/w block to generate 642 MSI doorbell writes with non-zero values for the device ID. 643 644 If unsure, say Y. 645 646config HISILICON_ERRATUM_161600802 647 bool "Hip07 161600802: Erroneous redistributor VLPI base" 648 default y 649 help 650 The HiSilicon Hip07 SoC usees the wrong redistributor base 651 when issued ITS commands such as VMOVP and VMAPP, and requires 652 a 128kB offset to be applied to the target address in this commands. 653 654 If unsure, say Y. 655 656config QCOM_FALKOR_ERRATUM_E1041 657 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 658 default y 659 help 660 Falkor CPU may speculatively fetch instructions from an improper 661 memory location when MMU translation is changed from SCTLR_ELn[M]=1 662 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 663 664 If unsure, say Y. 665 666endmenu 667 668 669choice 670 prompt "Page size" 671 default ARM64_4K_PAGES 672 help 673 Page size (translation granule) configuration. 674 675config ARM64_4K_PAGES 676 bool "4KB" 677 help 678 This feature enables 4KB pages support. 679 680config ARM64_16K_PAGES 681 bool "16KB" 682 help 683 The system will use 16KB pages support. AArch32 emulation 684 requires applications compiled with 16K (or a multiple of 16K) 685 aligned segments. 686 687config ARM64_64K_PAGES 688 bool "64KB" 689 help 690 This feature enables 64KB pages support (4KB by default) 691 allowing only two levels of page tables and faster TLB 692 look-up. AArch32 emulation requires applications compiled 693 with 64K aligned segments. 694 695endchoice 696 697choice 698 prompt "Virtual address space size" 699 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 700 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 701 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 702 help 703 Allows choosing one of multiple possible virtual address 704 space sizes. The level of translation table is determined by 705 a combination of page size and virtual address space size. 706 707config ARM64_VA_BITS_36 708 bool "36-bit" if EXPERT 709 depends on ARM64_16K_PAGES 710 711config ARM64_VA_BITS_39 712 bool "39-bit" 713 depends on ARM64_4K_PAGES 714 715config ARM64_VA_BITS_42 716 bool "42-bit" 717 depends on ARM64_64K_PAGES 718 719config ARM64_VA_BITS_47 720 bool "47-bit" 721 depends on ARM64_16K_PAGES 722 723config ARM64_VA_BITS_48 724 bool "48-bit" 725 726config ARM64_USER_VA_BITS_52 727 bool "52-bit (user)" 728 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 729 help 730 Enable 52-bit virtual addressing for userspace when explicitly 731 requested via a hint to mmap(). The kernel will continue to 732 use 48-bit virtual addresses for its own mappings. 733 734 NOTE: Enabling 52-bit virtual addressing in conjunction with 735 ARMv8.3 Pointer Authentication will result in the PAC being 736 reduced from 7 bits to 3 bits, which may have a significant 737 impact on its susceptibility to brute-force attacks. 738 739 If unsure, select 48-bit virtual addressing instead. 740 741endchoice 742 743config ARM64_FORCE_52BIT 744 bool "Force 52-bit virtual addresses for userspace" 745 depends on ARM64_USER_VA_BITS_52 && EXPERT 746 help 747 For systems with 52-bit userspace VAs enabled, the kernel will attempt 748 to maintain compatibility with older software by providing 48-bit VAs 749 unless a hint is supplied to mmap. 750 751 This configuration option disables the 48-bit compatibility logic, and 752 forces all userspace addresses to be 52-bit on HW that supports it. One 753 should only enable this configuration option for stress testing userspace 754 memory management code. If unsure say N here. 755 756config ARM64_VA_BITS 757 int 758 default 36 if ARM64_VA_BITS_36 759 default 39 if ARM64_VA_BITS_39 760 default 42 if ARM64_VA_BITS_42 761 default 47 if ARM64_VA_BITS_47 762 default 48 if ARM64_VA_BITS_48 || ARM64_USER_VA_BITS_52 763 764choice 765 prompt "Physical address space size" 766 default ARM64_PA_BITS_48 767 help 768 Choose the maximum physical address range that the kernel will 769 support. 770 771config ARM64_PA_BITS_48 772 bool "48-bit" 773 774config ARM64_PA_BITS_52 775 bool "52-bit (ARMv8.2)" 776 depends on ARM64_64K_PAGES 777 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 778 help 779 Enable support for a 52-bit physical address space, introduced as 780 part of the ARMv8.2-LPA extension. 781 782 With this enabled, the kernel will also continue to work on CPUs that 783 do not support ARMv8.2-LPA, but with some added memory overhead (and 784 minor performance overhead). 785 786endchoice 787 788config ARM64_PA_BITS 789 int 790 default 48 if ARM64_PA_BITS_48 791 default 52 if ARM64_PA_BITS_52 792 793config CPU_BIG_ENDIAN 794 bool "Build big-endian kernel" 795 help 796 Say Y if you plan on running a kernel in big-endian mode. 797 798config SCHED_MC 799 bool "Multi-core scheduler support" 800 help 801 Multi-core scheduler support improves the CPU scheduler's decision 802 making when dealing with multi-core CPU chips at a cost of slightly 803 increased overhead in some places. If unsure say N here. 804 805config SCHED_SMT 806 bool "SMT scheduler support" 807 help 808 Improves the CPU scheduler's decision making when dealing with 809 MultiThreading at a cost of slightly increased overhead in some 810 places. If unsure say N here. 811 812config NR_CPUS 813 int "Maximum number of CPUs (2-4096)" 814 range 2 4096 815 # These have to remain sorted largest to smallest 816 default "64" 817 818config HOTPLUG_CPU 819 bool "Support for hot-pluggable CPUs" 820 select GENERIC_IRQ_MIGRATION 821 help 822 Say Y here to experiment with turning CPUs off and on. CPUs 823 can be controlled through /sys/devices/system/cpu. 824 825# Common NUMA Features 826config NUMA 827 bool "Numa Memory Allocation and Scheduler Support" 828 select ACPI_NUMA if ACPI 829 select OF_NUMA 830 help 831 Enable NUMA (Non Uniform Memory Access) support. 832 833 The kernel will try to allocate memory used by a CPU on the 834 local memory of the CPU and add some more 835 NUMA awareness to the kernel. 836 837config NODES_SHIFT 838 int "Maximum NUMA Nodes (as a power of 2)" 839 range 1 10 840 default "2" 841 depends on NEED_MULTIPLE_NODES 842 help 843 Specify the maximum number of NUMA Nodes available on the target 844 system. Increases memory reserved to accommodate various tables. 845 846config USE_PERCPU_NUMA_NODE_ID 847 def_bool y 848 depends on NUMA 849 850config HAVE_SETUP_PER_CPU_AREA 851 def_bool y 852 depends on NUMA 853 854config NEED_PER_CPU_EMBED_FIRST_CHUNK 855 def_bool y 856 depends on NUMA 857 858config HOLES_IN_ZONE 859 def_bool y 860 861source kernel/Kconfig.hz 862 863config ARCH_SUPPORTS_DEBUG_PAGEALLOC 864 def_bool y 865 866config ARCH_SPARSEMEM_ENABLE 867 def_bool y 868 select SPARSEMEM_VMEMMAP_ENABLE 869 870config ARCH_SPARSEMEM_DEFAULT 871 def_bool ARCH_SPARSEMEM_ENABLE 872 873config ARCH_SELECT_MEMORY_MODEL 874 def_bool ARCH_SPARSEMEM_ENABLE 875 876config ARCH_FLATMEM_ENABLE 877 def_bool !NUMA 878 879config HAVE_ARCH_PFN_VALID 880 def_bool y 881 882config HW_PERF_EVENTS 883 def_bool y 884 depends on ARM_PMU 885 886config SYS_SUPPORTS_HUGETLBFS 887 def_bool y 888 889config ARCH_WANT_HUGE_PMD_SHARE 890 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 891 892config ARCH_HAS_CACHE_LINE_SIZE 893 def_bool y 894 895config SECCOMP 896 bool "Enable seccomp to safely compute untrusted bytecode" 897 ---help--- 898 This kernel feature is useful for number crunching applications 899 that may need to compute untrusted bytecode during their 900 execution. By using pipes or other transports made available to 901 the process as file descriptors supporting the read/write 902 syscalls, it's possible to isolate those applications in 903 their own address space using seccomp. Once seccomp is 904 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 905 and the task is only allowed to execute a few safe syscalls 906 defined by each seccomp mode. 907 908config PARAVIRT 909 bool "Enable paravirtualization code" 910 help 911 This changes the kernel so it can modify itself when it is run 912 under a hypervisor, potentially improving performance significantly 913 over full virtualization. 914 915config PARAVIRT_TIME_ACCOUNTING 916 bool "Paravirtual steal time accounting" 917 select PARAVIRT 918 default n 919 help 920 Select this option to enable fine granularity task steal time 921 accounting. Time spent executing other tasks in parallel with 922 the current vCPU is discounted from the vCPU power. To account for 923 that, there can be a small performance impact. 924 925 If in doubt, say N here. 926 927config KEXEC 928 depends on PM_SLEEP_SMP 929 select KEXEC_CORE 930 bool "kexec system call" 931 ---help--- 932 kexec is a system call that implements the ability to shutdown your 933 current kernel, and to start another kernel. It is like a reboot 934 but it is independent of the system firmware. And like a reboot 935 you can start any kernel with it, not just Linux. 936 937config KEXEC_FILE 938 bool "kexec file based system call" 939 select KEXEC_CORE 940 help 941 This is new version of kexec system call. This system call is 942 file based and takes file descriptors as system call argument 943 for kernel and initramfs as opposed to list of segments as 944 accepted by previous system call. 945 946config KEXEC_VERIFY_SIG 947 bool "Verify kernel signature during kexec_file_load() syscall" 948 depends on KEXEC_FILE 949 help 950 Select this option to verify a signature with loaded kernel 951 image. If configured, any attempt of loading a image without 952 valid signature will fail. 953 954 In addition to that option, you need to enable signature 955 verification for the corresponding kernel image type being 956 loaded in order for this to work. 957 958config KEXEC_IMAGE_VERIFY_SIG 959 bool "Enable Image signature verification support" 960 default y 961 depends on KEXEC_VERIFY_SIG 962 depends on EFI && SIGNED_PE_FILE_VERIFICATION 963 help 964 Enable Image signature verification support. 965 966comment "Support for PE file signature verification disabled" 967 depends on KEXEC_VERIFY_SIG 968 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 969 970config CRASH_DUMP 971 bool "Build kdump crash kernel" 972 help 973 Generate crash dump after being started by kexec. This should 974 be normally only set in special crash dump kernels which are 975 loaded in the main kernel with kexec-tools into a specially 976 reserved region and then later executed after a crash by 977 kdump/kexec. 978 979 For more details see Documentation/kdump/kdump.txt 980 981config XEN_DOM0 982 def_bool y 983 depends on XEN 984 985config XEN 986 bool "Xen guest support on ARM64" 987 depends on ARM64 && OF 988 select SWIOTLB_XEN 989 select PARAVIRT 990 help 991 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 992 993config FORCE_MAX_ZONEORDER 994 int 995 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 996 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 997 default "11" 998 help 999 The kernel memory allocator divides physically contiguous memory 1000 blocks into "zones", where each zone is a power of two number of 1001 pages. This option selects the largest power of two that the kernel 1002 keeps in the memory allocator. If you need to allocate very large 1003 blocks of physically contiguous memory, then you may need to 1004 increase this value. 1005 1006 This config option is actually maximum order plus one. For example, 1007 a value of 11 means that the largest free memory block is 2^10 pages. 1008 1009 We make sure that we can allocate upto a HugePage size for each configuration. 1010 Hence we have : 1011 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1012 1013 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1014 4M allocations matching the default size used by generic code. 1015 1016config UNMAP_KERNEL_AT_EL0 1017 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1018 default y 1019 help 1020 Speculation attacks against some high-performance processors can 1021 be used to bypass MMU permission checks and leak kernel data to 1022 userspace. This can be defended against by unmapping the kernel 1023 when running in userspace, mapping it back in on exception entry 1024 via a trampoline page in the vector table. 1025 1026 If unsure, say Y. 1027 1028config HARDEN_BRANCH_PREDICTOR 1029 bool "Harden the branch predictor against aliasing attacks" if EXPERT 1030 default y 1031 help 1032 Speculation attacks against some high-performance processors rely on 1033 being able to manipulate the branch predictor for a victim context by 1034 executing aliasing branches in the attacker context. Such attacks 1035 can be partially mitigated against by clearing internal branch 1036 predictor state and limiting the prediction logic in some situations. 1037 1038 This config option will take CPU-specific actions to harden the 1039 branch predictor against aliasing attacks and may rely on specific 1040 instruction sequences or control bits being set by the system 1041 firmware. 1042 1043 If unsure, say Y. 1044 1045config HARDEN_EL2_VECTORS 1046 bool "Harden EL2 vector mapping against system register leak" if EXPERT 1047 default y 1048 help 1049 Speculation attacks against some high-performance processors can 1050 be used to leak privileged information such as the vector base 1051 register, resulting in a potential defeat of the EL2 layout 1052 randomization. 1053 1054 This config option will map the vectors to a fixed location, 1055 independent of the EL2 code mapping, so that revealing VBAR_EL2 1056 to an attacker does not give away any extra information. This 1057 only gets enabled on affected CPUs. 1058 1059 If unsure, say Y. 1060 1061config ARM64_SSBD 1062 bool "Speculative Store Bypass Disable" if EXPERT 1063 default y 1064 help 1065 This enables mitigation of the bypassing of previous stores 1066 by speculative loads. 1067 1068 If unsure, say Y. 1069 1070config RODATA_FULL_DEFAULT_ENABLED 1071 bool "Apply r/o permissions of VM areas also to their linear aliases" 1072 default y 1073 help 1074 Apply read-only attributes of VM areas to the linear alias of 1075 the backing pages as well. This prevents code or read-only data 1076 from being modified (inadvertently or intentionally) via another 1077 mapping of the same memory page. This additional enhancement can 1078 be turned off at runtime by passing rodata=[off|on] (and turned on 1079 with rodata=full if this option is set to 'n') 1080 1081 This requires the linear region to be mapped down to pages, 1082 which may adversely affect performance in some cases. 1083 1084menuconfig ARMV8_DEPRECATED 1085 bool "Emulate deprecated/obsolete ARMv8 instructions" 1086 depends on COMPAT 1087 depends on SYSCTL 1088 help 1089 Legacy software support may require certain instructions 1090 that have been deprecated or obsoleted in the architecture. 1091 1092 Enable this config to enable selective emulation of these 1093 features. 1094 1095 If unsure, say Y 1096 1097if ARMV8_DEPRECATED 1098 1099config SWP_EMULATION 1100 bool "Emulate SWP/SWPB instructions" 1101 help 1102 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1103 they are always undefined. Say Y here to enable software 1104 emulation of these instructions for userspace using LDXR/STXR. 1105 1106 In some older versions of glibc [<=2.8] SWP is used during futex 1107 trylock() operations with the assumption that the code will not 1108 be preempted. This invalid assumption may be more likely to fail 1109 with SWP emulation enabled, leading to deadlock of the user 1110 application. 1111 1112 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1113 on an external transaction monitoring block called a global 1114 monitor to maintain update atomicity. If your system does not 1115 implement a global monitor, this option can cause programs that 1116 perform SWP operations to uncached memory to deadlock. 1117 1118 If unsure, say Y 1119 1120config CP15_BARRIER_EMULATION 1121 bool "Emulate CP15 Barrier instructions" 1122 help 1123 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1124 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1125 strongly recommended to use the ISB, DSB, and DMB 1126 instructions instead. 1127 1128 Say Y here to enable software emulation of these 1129 instructions for AArch32 userspace code. When this option is 1130 enabled, CP15 barrier usage is traced which can help 1131 identify software that needs updating. 1132 1133 If unsure, say Y 1134 1135config SETEND_EMULATION 1136 bool "Emulate SETEND instruction" 1137 help 1138 The SETEND instruction alters the data-endianness of the 1139 AArch32 EL0, and is deprecated in ARMv8. 1140 1141 Say Y here to enable software emulation of the instruction 1142 for AArch32 userspace code. 1143 1144 Note: All the cpus on the system must have mixed endian support at EL0 1145 for this feature to be enabled. If a new CPU - which doesn't support mixed 1146 endian - is hotplugged in after this feature has been enabled, there could 1147 be unexpected results in the applications. 1148 1149 If unsure, say Y 1150endif 1151 1152config ARM64_SW_TTBR0_PAN 1153 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1154 help 1155 Enabling this option prevents the kernel from accessing 1156 user-space memory directly by pointing TTBR0_EL1 to a reserved 1157 zeroed area and reserved ASID. The user access routines 1158 restore the valid TTBR0_EL1 temporarily. 1159 1160menu "ARMv8.1 architectural features" 1161 1162config ARM64_HW_AFDBM 1163 bool "Support for hardware updates of the Access and Dirty page flags" 1164 default y 1165 help 1166 The ARMv8.1 architecture extensions introduce support for 1167 hardware updates of the access and dirty information in page 1168 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1169 capable processors, accesses to pages with PTE_AF cleared will 1170 set this bit instead of raising an access flag fault. 1171 Similarly, writes to read-only pages with the DBM bit set will 1172 clear the read-only bit (AP[2]) instead of raising a 1173 permission fault. 1174 1175 Kernels built with this configuration option enabled continue 1176 to work on pre-ARMv8.1 hardware and the performance impact is 1177 minimal. If unsure, say Y. 1178 1179config ARM64_PAN 1180 bool "Enable support for Privileged Access Never (PAN)" 1181 default y 1182 help 1183 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1184 prevents the kernel or hypervisor from accessing user-space (EL0) 1185 memory directly. 1186 1187 Choosing this option will cause any unprotected (not using 1188 copy_to_user et al) memory access to fail with a permission fault. 1189 1190 The feature is detected at runtime, and will remain as a 'nop' 1191 instruction if the cpu does not implement the feature. 1192 1193config ARM64_LSE_ATOMICS 1194 bool "Atomic instructions" 1195 default y 1196 help 1197 As part of the Large System Extensions, ARMv8.1 introduces new 1198 atomic instructions that are designed specifically to scale in 1199 very large systems. 1200 1201 Say Y here to make use of these instructions for the in-kernel 1202 atomic routines. This incurs a small overhead on CPUs that do 1203 not support these instructions and requires the kernel to be 1204 built with binutils >= 2.25 in order for the new instructions 1205 to be used. 1206 1207config ARM64_VHE 1208 bool "Enable support for Virtualization Host Extensions (VHE)" 1209 default y 1210 help 1211 Virtualization Host Extensions (VHE) allow the kernel to run 1212 directly at EL2 (instead of EL1) on processors that support 1213 it. This leads to better performance for KVM, as they reduce 1214 the cost of the world switch. 1215 1216 Selecting this option allows the VHE feature to be detected 1217 at runtime, and does not affect processors that do not 1218 implement this feature. 1219 1220endmenu 1221 1222menu "ARMv8.2 architectural features" 1223 1224config ARM64_UAO 1225 bool "Enable support for User Access Override (UAO)" 1226 default y 1227 help 1228 User Access Override (UAO; part of the ARMv8.2 Extensions) 1229 causes the 'unprivileged' variant of the load/store instructions to 1230 be overridden to be privileged. 1231 1232 This option changes get_user() and friends to use the 'unprivileged' 1233 variant of the load/store instructions. This ensures that user-space 1234 really did have access to the supplied memory. When addr_limit is 1235 set to kernel memory the UAO bit will be set, allowing privileged 1236 access to kernel memory. 1237 1238 Choosing this option will cause copy_to_user() et al to use user-space 1239 memory permissions. 1240 1241 The feature is detected at runtime, the kernel will use the 1242 regular load/store instructions if the cpu does not implement the 1243 feature. 1244 1245config ARM64_PMEM 1246 bool "Enable support for persistent memory" 1247 select ARCH_HAS_PMEM_API 1248 select ARCH_HAS_UACCESS_FLUSHCACHE 1249 help 1250 Say Y to enable support for the persistent memory API based on the 1251 ARMv8.2 DCPoP feature. 1252 1253 The feature is detected at runtime, and the kernel will use DC CVAC 1254 operations if DC CVAP is not supported (following the behaviour of 1255 DC CVAP itself if the system does not define a point of persistence). 1256 1257config ARM64_RAS_EXTN 1258 bool "Enable support for RAS CPU Extensions" 1259 default y 1260 help 1261 CPUs that support the Reliability, Availability and Serviceability 1262 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1263 errors, classify them and report them to software. 1264 1265 On CPUs with these extensions system software can use additional 1266 barriers to determine if faults are pending and read the 1267 classification from a new set of registers. 1268 1269 Selecting this feature will allow the kernel to use these barriers 1270 and access the new registers if the system supports the extension. 1271 Platform RAS features may additionally depend on firmware support. 1272 1273config ARM64_CNP 1274 bool "Enable support for Common Not Private (CNP) translations" 1275 default y 1276 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1277 help 1278 Common Not Private (CNP) allows translation table entries to 1279 be shared between different PEs in the same inner shareable 1280 domain, so the hardware can use this fact to optimise the 1281 caching of such entries in the TLB. 1282 1283 Selecting this option allows the CNP feature to be detected 1284 at runtime, and does not affect PEs that do not implement 1285 this feature. 1286 1287endmenu 1288 1289menu "ARMv8.3 architectural features" 1290 1291config ARM64_PTR_AUTH 1292 bool "Enable support for pointer authentication" 1293 default y 1294 help 1295 Pointer authentication (part of the ARMv8.3 Extensions) provides 1296 instructions for signing and authenticating pointers against secret 1297 keys, which can be used to mitigate Return Oriented Programming (ROP) 1298 and other attacks. 1299 1300 This option enables these instructions at EL0 (i.e. for userspace). 1301 1302 Choosing this option will cause the kernel to initialise secret keys 1303 for each process at exec() time, with these keys being 1304 context-switched along with the process. 1305 1306 The feature is detected at runtime. If the feature is not present in 1307 hardware it will not be advertised to userspace nor will it be 1308 enabled. 1309 1310endmenu 1311 1312config ARM64_SVE 1313 bool "ARM Scalable Vector Extension support" 1314 default y 1315 depends on !KVM || ARM64_VHE 1316 help 1317 The Scalable Vector Extension (SVE) is an extension to the AArch64 1318 execution state which complements and extends the SIMD functionality 1319 of the base architecture to support much larger vectors and to enable 1320 additional vectorisation opportunities. 1321 1322 To enable use of this extension on CPUs that implement it, say Y. 1323 1324 Note that for architectural reasons, firmware _must_ implement SVE 1325 support when running on SVE capable hardware. The required support 1326 is present in: 1327 1328 * version 1.5 and later of the ARM Trusted Firmware 1329 * the AArch64 boot wrapper since commit 5e1261e08abf 1330 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1331 1332 For other firmware implementations, consult the firmware documentation 1333 or vendor. 1334 1335 If you need the kernel to boot on SVE-capable hardware with broken 1336 firmware, you may need to say N here until you get your firmware 1337 fixed. Otherwise, you may experience firmware panics or lockups when 1338 booting the kernel. If unsure and you are not observing these 1339 symptoms, you should assume that it is safe to say Y. 1340 1341 CPUs that support SVE are architecturally required to support the 1342 Virtualization Host Extensions (VHE), so the kernel makes no 1343 provision for supporting SVE alongside KVM without VHE enabled. 1344 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support 1345 KVM in the same kernel image. 1346 1347config ARM64_MODULE_PLTS 1348 bool 1349 select HAVE_MOD_ARCH_SPECIFIC 1350 1351config RELOCATABLE 1352 bool 1353 help 1354 This builds the kernel as a Position Independent Executable (PIE), 1355 which retains all relocation metadata required to relocate the 1356 kernel binary at runtime to a different virtual address than the 1357 address it was linked at. 1358 Since AArch64 uses the RELA relocation format, this requires a 1359 relocation pass at runtime even if the kernel is loaded at the 1360 same address it was linked at. 1361 1362config RANDOMIZE_BASE 1363 bool "Randomize the address of the kernel image" 1364 select ARM64_MODULE_PLTS if MODULES 1365 select RELOCATABLE 1366 help 1367 Randomizes the virtual address at which the kernel image is 1368 loaded, as a security feature that deters exploit attempts 1369 relying on knowledge of the location of kernel internals. 1370 1371 It is the bootloader's job to provide entropy, by passing a 1372 random u64 value in /chosen/kaslr-seed at kernel entry. 1373 1374 When booting via the UEFI stub, it will invoke the firmware's 1375 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 1376 to the kernel proper. In addition, it will randomise the physical 1377 location of the kernel Image as well. 1378 1379 If unsure, say N. 1380 1381config RANDOMIZE_MODULE_REGION_FULL 1382 bool "Randomize the module region over a 4 GB range" 1383 depends on RANDOMIZE_BASE 1384 default y 1385 help 1386 Randomizes the location of the module region inside a 4 GB window 1387 covering the core kernel. This way, it is less likely for modules 1388 to leak information about the location of core kernel data structures 1389 but it does imply that function calls between modules and the core 1390 kernel will need to be resolved via veneers in the module PLT. 1391 1392 When this option is not set, the module region will be randomized over 1393 a limited range that contains the [_stext, _etext] interval of the 1394 core kernel, so branch relocations are always in range. 1395 1396config CC_HAVE_STACKPROTECTOR_SYSREG 1397 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 1398 1399config STACKPROTECTOR_PER_TASK 1400 def_bool y 1401 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 1402 1403endmenu 1404 1405menu "Boot options" 1406 1407config ARM64_ACPI_PARKING_PROTOCOL 1408 bool "Enable support for the ARM64 ACPI parking protocol" 1409 depends on ACPI 1410 help 1411 Enable support for the ARM64 ACPI parking protocol. If disabled 1412 the kernel will not allow booting through the ARM64 ACPI parking 1413 protocol even if the corresponding data is present in the ACPI 1414 MADT table. 1415 1416config CMDLINE 1417 string "Default kernel command string" 1418 default "" 1419 help 1420 Provide a set of default command-line options at build time by 1421 entering them here. As a minimum, you should specify the the 1422 root device (e.g. root=/dev/nfs). 1423 1424config CMDLINE_FORCE 1425 bool "Always use the default kernel command string" 1426 help 1427 Always use the default kernel command string, even if the boot 1428 loader passes other arguments to the kernel. 1429 This is useful if you cannot or don't want to change the 1430 command-line options your boot loader passes to the kernel. 1431 1432config EFI_STUB 1433 bool 1434 1435config EFI 1436 bool "UEFI runtime support" 1437 depends on OF && !CPU_BIG_ENDIAN 1438 depends on KERNEL_MODE_NEON 1439 select ARCH_SUPPORTS_ACPI 1440 select LIBFDT 1441 select UCS2_STRING 1442 select EFI_PARAMS_FROM_FDT 1443 select EFI_RUNTIME_WRAPPERS 1444 select EFI_STUB 1445 select EFI_ARMSTUB 1446 default y 1447 help 1448 This option provides support for runtime services provided 1449 by UEFI firmware (such as non-volatile variables, realtime 1450 clock, and platform reset). A UEFI stub is also provided to 1451 allow the kernel to be booted as an EFI application. This 1452 is only useful on systems that have UEFI firmware. 1453 1454config DMI 1455 bool "Enable support for SMBIOS (DMI) tables" 1456 depends on EFI 1457 default y 1458 help 1459 This enables SMBIOS/DMI feature for systems. 1460 1461 This option is only useful on systems that have UEFI firmware. 1462 However, even with this option, the resultant kernel should 1463 continue to boot on existing non-UEFI platforms. 1464 1465endmenu 1466 1467config COMPAT 1468 bool "Kernel support for 32-bit EL0" 1469 depends on ARM64_4K_PAGES || EXPERT 1470 select COMPAT_BINFMT_ELF if BINFMT_ELF 1471 select HAVE_UID16 1472 select OLD_SIGSUSPEND3 1473 select COMPAT_OLD_SIGACTION 1474 help 1475 This option enables support for a 32-bit EL0 running under a 64-bit 1476 kernel at EL1. AArch32-specific components such as system calls, 1477 the user helper functions, VFP support and the ptrace interface are 1478 handled appropriately by the kernel. 1479 1480 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1481 that you will only be able to execute AArch32 binaries that were compiled 1482 with page size aligned segments. 1483 1484 If you want to execute 32-bit userspace applications, say Y. 1485 1486config SYSVIPC_COMPAT 1487 def_bool y 1488 depends on COMPAT && SYSVIPC 1489 1490menu "Power management options" 1491 1492source "kernel/power/Kconfig" 1493 1494config ARCH_HIBERNATION_POSSIBLE 1495 def_bool y 1496 depends on CPU_PM 1497 1498config ARCH_HIBERNATION_HEADER 1499 def_bool y 1500 depends on HIBERNATION 1501 1502config ARCH_SUSPEND_POSSIBLE 1503 def_bool y 1504 1505endmenu 1506 1507menu "CPU Power Management" 1508 1509source "drivers/cpuidle/Kconfig" 1510 1511source "drivers/cpufreq/Kconfig" 1512 1513endmenu 1514 1515source "drivers/firmware/Kconfig" 1516 1517source "drivers/acpi/Kconfig" 1518 1519source "arch/arm64/kvm/Kconfig" 1520 1521if CRYPTO 1522source "arch/arm64/crypto/Kconfig" 1523endif 1524