xref: /openbmc/linux/arch/arm64/Kconfig (revision b5f184fbdb03b4fcc1141de34dd5ec964ca5d99e)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_CCA_REQUIRED if ACPI
5	select ACPI_GENERIC_GSI if ACPI
6	select ACPI_GTDT if ACPI
7	select ACPI_IORT if ACPI
8	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9	select ACPI_MCFG if (ACPI && PCI)
10	select ACPI_SPCR_TABLE if ACPI
11	select ACPI_PPTT if ACPI
12	select ARCH_HAS_DEBUG_WX
13	select ARCH_BINFMT_ELF_STATE
14	select ARCH_HAS_DEBUG_VIRTUAL
15	select ARCH_HAS_DEBUG_VM_PGTABLE
16	select ARCH_HAS_DMA_PREP_COHERENT
17	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18	select ARCH_HAS_FAST_MULTIPLIER
19	select ARCH_HAS_FORTIFY_SOURCE
20	select ARCH_HAS_GCOV_PROFILE_ALL
21	select ARCH_HAS_GIGANTIC_PAGE
22	select ARCH_HAS_KCOV
23	select ARCH_HAS_KEEPINITRD
24	select ARCH_HAS_MEMBARRIER_SYNC_CORE
25	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
26	select ARCH_HAS_PTE_DEVMAP
27	select ARCH_HAS_PTE_SPECIAL
28	select ARCH_HAS_SETUP_DMA_OPS
29	select ARCH_HAS_SET_DIRECT_MAP
30	select ARCH_HAS_SET_MEMORY
31	select ARCH_STACKWALK
32	select ARCH_HAS_STRICT_KERNEL_RWX
33	select ARCH_HAS_STRICT_MODULE_RWX
34	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
35	select ARCH_HAS_SYNC_DMA_FOR_CPU
36	select ARCH_HAS_SYSCALL_WRAPPER
37	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
38	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
39	select ARCH_HAVE_ELF_PROT
40	select ARCH_HAVE_NMI_SAFE_CMPXCHG
41	select ARCH_INLINE_READ_LOCK if !PREEMPTION
42	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
43	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
44	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
45	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
46	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
47	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
48	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
49	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
50	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
51	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
52	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
53	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
54	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
55	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
56	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
57	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
58	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
59	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
60	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
61	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
62	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
63	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
64	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
65	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
66	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
67	select ARCH_KEEP_MEMBLOCK
68	select ARCH_USE_CMPXCHG_LOCKREF
69	select ARCH_USE_GNU_PROPERTY
70	select ARCH_USE_QUEUED_RWLOCKS
71	select ARCH_USE_QUEUED_SPINLOCKS
72	select ARCH_USE_SYM_ANNOTATIONS
73	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
74	select ARCH_SUPPORTS_MEMORY_FAILURE
75	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
76	select ARCH_SUPPORTS_ATOMIC_RMW
77	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 && (GCC_VERSION >= 50000 || CC_IS_CLANG)
78	select ARCH_SUPPORTS_NUMA_BALANCING
79	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
80	select ARCH_WANT_DEFAULT_BPF_JIT
81	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
82	select ARCH_WANT_FRAME_POINTERS
83	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
84	select ARCH_WANT_LD_ORPHAN_WARN
85	select ARCH_HAS_UBSAN_SANITIZE_ALL
86	select ARM_AMBA
87	select ARM_ARCH_TIMER
88	select ARM_GIC
89	select AUDIT_ARCH_COMPAT_GENERIC
90	select ARM_GIC_V2M if PCI
91	select ARM_GIC_V3
92	select ARM_GIC_V3_ITS if PCI
93	select ARM_PSCI_FW
94	select BUILDTIME_TABLE_SORT
95	select CLONE_BACKWARDS
96	select COMMON_CLK
97	select CPU_PM if (SUSPEND || CPU_IDLE)
98	select CRC32
99	select DCACHE_WORD_ACCESS
100	select DMA_DIRECT_REMAP
101	select EDAC_SUPPORT
102	select FRAME_POINTER
103	select GENERIC_ALLOCATOR
104	select GENERIC_ARCH_TOPOLOGY
105	select GENERIC_CLOCKEVENTS_BROADCAST
106	select GENERIC_CPU_AUTOPROBE
107	select GENERIC_CPU_VULNERABILITIES
108	select GENERIC_EARLY_IOREMAP
109	select GENERIC_IDLE_POLL_SETUP
110	select GENERIC_IRQ_IPI
111	select GENERIC_IRQ_MULTI_HANDLER
112	select GENERIC_IRQ_PROBE
113	select GENERIC_IRQ_SHOW
114	select GENERIC_IRQ_SHOW_LEVEL
115	select GENERIC_LIB_DEVMEM_IS_ALLOWED
116	select GENERIC_PCI_IOMAP
117	select GENERIC_PTDUMP
118	select GENERIC_SCHED_CLOCK
119	select GENERIC_SMP_IDLE_THREAD
120	select GENERIC_STRNCPY_FROM_USER
121	select GENERIC_STRNLEN_USER
122	select GENERIC_TIME_VSYSCALL
123	select GENERIC_GETTIMEOFDAY
124	select GENERIC_VDSO_TIME_NS
125	select HANDLE_DOMAIN_IRQ
126	select HARDIRQS_SW_RESEND
127	select HAVE_MOVE_PMD
128	select HAVE_MOVE_PUD
129	select HAVE_PCI
130	select HAVE_ACPI_APEI if (ACPI && EFI)
131	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
132	select HAVE_ARCH_AUDITSYSCALL
133	select HAVE_ARCH_BITREVERSE
134	select HAVE_ARCH_COMPILER_H
135	select HAVE_ARCH_HUGE_VMAP
136	select HAVE_ARCH_JUMP_LABEL
137	select HAVE_ARCH_JUMP_LABEL_RELATIVE
138	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
139	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
140	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
141	select HAVE_ARCH_KGDB
142	select HAVE_ARCH_MMAP_RND_BITS
143	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
144	select HAVE_ARCH_PFN_VALID
145	select HAVE_ARCH_PREL32_RELOCATIONS
146	select HAVE_ARCH_SECCOMP_FILTER
147	select HAVE_ARCH_STACKLEAK
148	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
149	select HAVE_ARCH_TRACEHOOK
150	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
151	select HAVE_ARCH_VMAP_STACK
152	select HAVE_ARM_SMCCC
153	select HAVE_ASM_MODVERSIONS
154	select HAVE_EBPF_JIT
155	select HAVE_C_RECORDMCOUNT
156	select HAVE_CMPXCHG_DOUBLE
157	select HAVE_CMPXCHG_LOCAL
158	select HAVE_CONTEXT_TRACKING
159	select HAVE_DEBUG_BUGVERBOSE
160	select HAVE_DEBUG_KMEMLEAK
161	select HAVE_DMA_CONTIGUOUS
162	select HAVE_DYNAMIC_FTRACE
163	select HAVE_DYNAMIC_FTRACE_WITH_REGS \
164		if $(cc-option,-fpatchable-function-entry=2)
165	select HAVE_EFFICIENT_UNALIGNED_ACCESS
166	select HAVE_FAST_GUP
167	select HAVE_FTRACE_MCOUNT_RECORD
168	select HAVE_FUNCTION_TRACER
169	select HAVE_FUNCTION_ERROR_INJECTION
170	select HAVE_FUNCTION_GRAPH_TRACER
171	select HAVE_GCC_PLUGINS
172	select HAVE_HW_BREAKPOINT if PERF_EVENTS
173	select HAVE_IRQ_TIME_ACCOUNTING
174	select HAVE_NMI
175	select HAVE_PATA_PLATFORM
176	select HAVE_PERF_EVENTS
177	select HAVE_PERF_REGS
178	select HAVE_PERF_USER_STACK_DUMP
179	select HAVE_REGS_AND_STACK_ACCESS_API
180	select HAVE_FUNCTION_ARG_ACCESS_API
181	select HAVE_FUTEX_CMPXCHG if FUTEX
182	select MMU_GATHER_RCU_TABLE_FREE
183	select HAVE_RSEQ
184	select HAVE_STACKPROTECTOR
185	select HAVE_SYSCALL_TRACEPOINTS
186	select HAVE_KPROBES
187	select HAVE_KRETPROBES
188	select HAVE_GENERIC_VDSO
189	select IOMMU_DMA if IOMMU_SUPPORT
190	select IRQ_DOMAIN
191	select IRQ_FORCED_THREADING
192	select MODULES_USE_ELF_RELA
193	select NEED_DMA_MAP_STATE
194	select NEED_SG_DMA_LENGTH
195	select OF
196	select OF_EARLY_FLATTREE
197	select PCI_DOMAINS_GENERIC if PCI
198	select PCI_ECAM if (ACPI && PCI)
199	select PCI_SYSCALL if PCI
200	select POWER_RESET
201	select POWER_SUPPLY
202	select SPARSE_IRQ
203	select SWIOTLB
204	select SYSCTL_EXCEPTION_TRACE
205	select THREAD_INFO_IN_TASK
206	help
207	  ARM 64-bit (AArch64) Linux support.
208
209config 64BIT
210	def_bool y
211
212config MMU
213	def_bool y
214
215config ARM64_PAGE_SHIFT
216	int
217	default 16 if ARM64_64K_PAGES
218	default 14 if ARM64_16K_PAGES
219	default 12
220
221config ARM64_CONT_PTE_SHIFT
222	int
223	default 5 if ARM64_64K_PAGES
224	default 7 if ARM64_16K_PAGES
225	default 4
226
227config ARM64_CONT_PMD_SHIFT
228	int
229	default 5 if ARM64_64K_PAGES
230	default 5 if ARM64_16K_PAGES
231	default 4
232
233config ARCH_MMAP_RND_BITS_MIN
234       default 14 if ARM64_64K_PAGES
235       default 16 if ARM64_16K_PAGES
236       default 18
237
238# max bits determined by the following formula:
239#  VA_BITS - PAGE_SHIFT - 3
240config ARCH_MMAP_RND_BITS_MAX
241       default 19 if ARM64_VA_BITS=36
242       default 24 if ARM64_VA_BITS=39
243       default 27 if ARM64_VA_BITS=42
244       default 30 if ARM64_VA_BITS=47
245       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
246       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
247       default 33 if ARM64_VA_BITS=48
248       default 14 if ARM64_64K_PAGES
249       default 16 if ARM64_16K_PAGES
250       default 18
251
252config ARCH_MMAP_RND_COMPAT_BITS_MIN
253       default 7 if ARM64_64K_PAGES
254       default 9 if ARM64_16K_PAGES
255       default 11
256
257config ARCH_MMAP_RND_COMPAT_BITS_MAX
258       default 16
259
260config NO_IOPORT_MAP
261	def_bool y if !PCI
262
263config STACKTRACE_SUPPORT
264	def_bool y
265
266config ILLEGAL_POINTER_VALUE
267	hex
268	default 0xdead000000000000
269
270config LOCKDEP_SUPPORT
271	def_bool y
272
273config TRACE_IRQFLAGS_SUPPORT
274	def_bool y
275
276config GENERIC_BUG
277	def_bool y
278	depends on BUG
279
280config GENERIC_BUG_RELATIVE_POINTERS
281	def_bool y
282	depends on GENERIC_BUG
283
284config GENERIC_HWEIGHT
285	def_bool y
286
287config GENERIC_CSUM
288        def_bool y
289
290config GENERIC_CALIBRATE_DELAY
291	def_bool y
292
293config ZONE_DMA
294	bool "Support DMA zone" if EXPERT
295	default y
296
297config ZONE_DMA32
298	bool "Support DMA32 zone" if EXPERT
299	default y
300
301config ARCH_ENABLE_MEMORY_HOTPLUG
302	def_bool y
303
304config ARCH_ENABLE_MEMORY_HOTREMOVE
305	def_bool y
306
307config SMP
308	def_bool y
309
310config KERNEL_MODE_NEON
311	def_bool y
312
313config FIX_EARLYCON_MEM
314	def_bool y
315
316config PGTABLE_LEVELS
317	int
318	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
319	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
320	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
321	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
322	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
323	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
324
325config ARCH_SUPPORTS_UPROBES
326	def_bool y
327
328config ARCH_PROC_KCORE_TEXT
329	def_bool y
330
331config BROKEN_GAS_INST
332	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
333
334config KASAN_SHADOW_OFFSET
335	hex
336	depends on KASAN_GENERIC || KASAN_SW_TAGS
337	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
338	default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
339	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
340	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
341	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
342	default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
343	default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
344	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
345	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
346	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
347	default 0xffffffffffffffff
348
349source "arch/arm64/Kconfig.platforms"
350
351menu "Kernel Features"
352
353menu "ARM errata workarounds via the alternatives framework"
354
355config ARM64_WORKAROUND_CLEAN_CACHE
356	bool
357
358config ARM64_ERRATUM_826319
359	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
360	default y
361	select ARM64_WORKAROUND_CLEAN_CACHE
362	help
363	  This option adds an alternative code sequence to work around ARM
364	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
365	  AXI master interface and an L2 cache.
366
367	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
368	  and is unable to accept a certain write via this interface, it will
369	  not progress on read data presented on the read data channel and the
370	  system can deadlock.
371
372	  The workaround promotes data cache clean instructions to
373	  data cache clean-and-invalidate.
374	  Please note that this does not necessarily enable the workaround,
375	  as it depends on the alternative framework, which will only patch
376	  the kernel if an affected CPU is detected.
377
378	  If unsure, say Y.
379
380config ARM64_ERRATUM_827319
381	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
382	default y
383	select ARM64_WORKAROUND_CLEAN_CACHE
384	help
385	  This option adds an alternative code sequence to work around ARM
386	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
387	  master interface and an L2 cache.
388
389	  Under certain conditions this erratum can cause a clean line eviction
390	  to occur at the same time as another transaction to the same address
391	  on the AMBA 5 CHI interface, which can cause data corruption if the
392	  interconnect reorders the two transactions.
393
394	  The workaround promotes data cache clean instructions to
395	  data cache clean-and-invalidate.
396	  Please note that this does not necessarily enable the workaround,
397	  as it depends on the alternative framework, which will only patch
398	  the kernel if an affected CPU is detected.
399
400	  If unsure, say Y.
401
402config ARM64_ERRATUM_824069
403	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
404	default y
405	select ARM64_WORKAROUND_CLEAN_CACHE
406	help
407	  This option adds an alternative code sequence to work around ARM
408	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
409	  to a coherent interconnect.
410
411	  If a Cortex-A53 processor is executing a store or prefetch for
412	  write instruction at the same time as a processor in another
413	  cluster is executing a cache maintenance operation to the same
414	  address, then this erratum might cause a clean cache line to be
415	  incorrectly marked as dirty.
416
417	  The workaround promotes data cache clean instructions to
418	  data cache clean-and-invalidate.
419	  Please note that this option does not necessarily enable the
420	  workaround, as it depends on the alternative framework, which will
421	  only patch the kernel if an affected CPU is detected.
422
423	  If unsure, say Y.
424
425config ARM64_ERRATUM_819472
426	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
427	default y
428	select ARM64_WORKAROUND_CLEAN_CACHE
429	help
430	  This option adds an alternative code sequence to work around ARM
431	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
432	  present when it is connected to a coherent interconnect.
433
434	  If the processor is executing a load and store exclusive sequence at
435	  the same time as a processor in another cluster is executing a cache
436	  maintenance operation to the same address, then this erratum might
437	  cause data corruption.
438
439	  The workaround promotes data cache clean instructions to
440	  data cache clean-and-invalidate.
441	  Please note that this does not necessarily enable the workaround,
442	  as it depends on the alternative framework, which will only patch
443	  the kernel if an affected CPU is detected.
444
445	  If unsure, say Y.
446
447config ARM64_ERRATUM_832075
448	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
449	default y
450	help
451	  This option adds an alternative code sequence to work around ARM
452	  erratum 832075 on Cortex-A57 parts up to r1p2.
453
454	  Affected Cortex-A57 parts might deadlock when exclusive load/store
455	  instructions to Write-Back memory are mixed with Device loads.
456
457	  The workaround is to promote device loads to use Load-Acquire
458	  semantics.
459	  Please note that this does not necessarily enable the workaround,
460	  as it depends on the alternative framework, which will only patch
461	  the kernel if an affected CPU is detected.
462
463	  If unsure, say Y.
464
465config ARM64_ERRATUM_834220
466	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
467	depends on KVM
468	default y
469	help
470	  This option adds an alternative code sequence to work around ARM
471	  erratum 834220 on Cortex-A57 parts up to r1p2.
472
473	  Affected Cortex-A57 parts might report a Stage 2 translation
474	  fault as the result of a Stage 1 fault for load crossing a
475	  page boundary when there is a permission or device memory
476	  alignment fault at Stage 1 and a translation fault at Stage 2.
477
478	  The workaround is to verify that the Stage 1 translation
479	  doesn't generate a fault before handling the Stage 2 fault.
480	  Please note that this does not necessarily enable the workaround,
481	  as it depends on the alternative framework, which will only patch
482	  the kernel if an affected CPU is detected.
483
484	  If unsure, say Y.
485
486config ARM64_ERRATUM_845719
487	bool "Cortex-A53: 845719: a load might read incorrect data"
488	depends on COMPAT
489	default y
490	help
491	  This option adds an alternative code sequence to work around ARM
492	  erratum 845719 on Cortex-A53 parts up to r0p4.
493
494	  When running a compat (AArch32) userspace on an affected Cortex-A53
495	  part, a load at EL0 from a virtual address that matches the bottom 32
496	  bits of the virtual address used by a recent load at (AArch64) EL1
497	  might return incorrect data.
498
499	  The workaround is to write the contextidr_el1 register on exception
500	  return to a 32-bit task.
501	  Please note that this does not necessarily enable the workaround,
502	  as it depends on the alternative framework, which will only patch
503	  the kernel if an affected CPU is detected.
504
505	  If unsure, say Y.
506
507config ARM64_ERRATUM_843419
508	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
509	default y
510	select ARM64_MODULE_PLTS if MODULES
511	help
512	  This option links the kernel with '--fix-cortex-a53-843419' and
513	  enables PLT support to replace certain ADRP instructions, which can
514	  cause subsequent memory accesses to use an incorrect address on
515	  Cortex-A53 parts up to r0p4.
516
517	  If unsure, say Y.
518
519config ARM64_ERRATUM_1024718
520	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
521	default y
522	help
523	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
524
525	  Affected Cortex-A55 cores (all revisions) could cause incorrect
526	  update of the hardware dirty bit when the DBM/AP bits are updated
527	  without a break-before-make. The workaround is to disable the usage
528	  of hardware DBM locally on the affected cores. CPUs not affected by
529	  this erratum will continue to use the feature.
530
531	  If unsure, say Y.
532
533config ARM64_ERRATUM_1418040
534	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
535	default y
536	depends on COMPAT
537	help
538	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
539	  errata 1188873 and 1418040.
540
541	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
542	  cause register corruption when accessing the timer registers
543	  from AArch32 userspace.
544
545	  If unsure, say Y.
546
547config ARM64_WORKAROUND_SPECULATIVE_AT
548	bool
549
550config ARM64_ERRATUM_1165522
551	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
552	default y
553	select ARM64_WORKAROUND_SPECULATIVE_AT
554	help
555	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
556
557	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
558	  corrupted TLBs by speculating an AT instruction during a guest
559	  context switch.
560
561	  If unsure, say Y.
562
563config ARM64_ERRATUM_1319367
564	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
565	default y
566	select ARM64_WORKAROUND_SPECULATIVE_AT
567	help
568	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
569	  and A72 erratum 1319367
570
571	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
572	  speculating an AT instruction during a guest context switch.
573
574	  If unsure, say Y.
575
576config ARM64_ERRATUM_1530923
577	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
578	default y
579	select ARM64_WORKAROUND_SPECULATIVE_AT
580	help
581	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
582
583	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
584	  corrupted TLBs by speculating an AT instruction during a guest
585	  context switch.
586
587	  If unsure, say Y.
588
589config ARM64_WORKAROUND_REPEAT_TLBI
590	bool
591
592config ARM64_ERRATUM_1286807
593	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
594	default y
595	select ARM64_WORKAROUND_REPEAT_TLBI
596	help
597	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
598
599	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
600	  address for a cacheable mapping of a location is being
601	  accessed by a core while another core is remapping the virtual
602	  address to a new physical page using the recommended
603	  break-before-make sequence, then under very rare circumstances
604	  TLBI+DSB completes before a read using the translation being
605	  invalidated has been observed by other observers. The
606	  workaround repeats the TLBI+DSB operation.
607
608config ARM64_ERRATUM_1463225
609	bool "Cortex-A76: Software Step might prevent interrupt recognition"
610	default y
611	help
612	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
613
614	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
615	  of a system call instruction (SVC) can prevent recognition of
616	  subsequent interrupts when software stepping is disabled in the
617	  exception handler of the system call and either kernel debugging
618	  is enabled or VHE is in use.
619
620	  Work around the erratum by triggering a dummy step exception
621	  when handling a system call from a task that is being stepped
622	  in a VHE configuration of the kernel.
623
624	  If unsure, say Y.
625
626config ARM64_ERRATUM_1542419
627	bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
628	default y
629	help
630	  This option adds a workaround for ARM Neoverse-N1 erratum
631	  1542419.
632
633	  Affected Neoverse-N1 cores could execute a stale instruction when
634	  modified by another CPU. The workaround depends on a firmware
635	  counterpart.
636
637	  Workaround the issue by hiding the DIC feature from EL0. This
638	  forces user-space to perform cache maintenance.
639
640	  If unsure, say Y.
641
642config ARM64_ERRATUM_1508412
643	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
644	default y
645	help
646	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
647
648	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
649	  of a store-exclusive or read of PAR_EL1 and a load with device or
650	  non-cacheable memory attributes. The workaround depends on a firmware
651	  counterpart.
652
653	  KVM guests must also have the workaround implemented or they can
654	  deadlock the system.
655
656	  Work around the issue by inserting DMB SY barriers around PAR_EL1
657	  register reads and warning KVM users. The DMB barrier is sufficient
658	  to prevent a speculative PAR_EL1 read.
659
660	  If unsure, say Y.
661
662config CAVIUM_ERRATUM_22375
663	bool "Cavium erratum 22375, 24313"
664	default y
665	help
666	  Enable workaround for errata 22375 and 24313.
667
668	  This implements two gicv3-its errata workarounds for ThunderX. Both
669	  with a small impact affecting only ITS table allocation.
670
671	    erratum 22375: only alloc 8MB table size
672	    erratum 24313: ignore memory access type
673
674	  The fixes are in ITS initialization and basically ignore memory access
675	  type and table size provided by the TYPER and BASER registers.
676
677	  If unsure, say Y.
678
679config CAVIUM_ERRATUM_23144
680	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
681	depends on NUMA
682	default y
683	help
684	  ITS SYNC command hang for cross node io and collections/cpu mapping.
685
686	  If unsure, say Y.
687
688config CAVIUM_ERRATUM_23154
689	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
690	default y
691	help
692	  The gicv3 of ThunderX requires a modified version for
693	  reading the IAR status to ensure data synchronization
694	  (access to icc_iar1_el1 is not sync'ed before and after).
695
696	  If unsure, say Y.
697
698config CAVIUM_ERRATUM_27456
699	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
700	default y
701	help
702	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
703	  instructions may cause the icache to become corrupted if it
704	  contains data for a non-current ASID.  The fix is to
705	  invalidate the icache when changing the mm context.
706
707	  If unsure, say Y.
708
709config CAVIUM_ERRATUM_30115
710	bool "Cavium erratum 30115: Guest may disable interrupts in host"
711	default y
712	help
713	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
714	  1.2, and T83 Pass 1.0, KVM guest execution may disable
715	  interrupts in host. Trapping both GICv3 group-0 and group-1
716	  accesses sidesteps the issue.
717
718	  If unsure, say Y.
719
720config CAVIUM_TX2_ERRATUM_219
721	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
722	default y
723	help
724	  On Cavium ThunderX2, a load, store or prefetch instruction between a
725	  TTBR update and the corresponding context synchronizing operation can
726	  cause a spurious Data Abort to be delivered to any hardware thread in
727	  the CPU core.
728
729	  Work around the issue by avoiding the problematic code sequence and
730	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
731	  trap handler performs the corresponding register access, skips the
732	  instruction and ensures context synchronization by virtue of the
733	  exception return.
734
735	  If unsure, say Y.
736
737config FUJITSU_ERRATUM_010001
738	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
739	default y
740	help
741	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
742	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
743	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
744	  This fault occurs under a specific hardware condition when a
745	  load/store instruction performs an address translation using:
746	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
747	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
748	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
749	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
750
751	  The workaround is to ensure these bits are clear in TCR_ELx.
752	  The workaround only affects the Fujitsu-A64FX.
753
754	  If unsure, say Y.
755
756config HISILICON_ERRATUM_161600802
757	bool "Hip07 161600802: Erroneous redistributor VLPI base"
758	default y
759	help
760	  The HiSilicon Hip07 SoC uses the wrong redistributor base
761	  when issued ITS commands such as VMOVP and VMAPP, and requires
762	  a 128kB offset to be applied to the target address in this commands.
763
764	  If unsure, say Y.
765
766config QCOM_FALKOR_ERRATUM_1003
767	bool "Falkor E1003: Incorrect translation due to ASID change"
768	default y
769	help
770	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
771	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
772	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
773	  then only for entries in the walk cache, since the leaf translation
774	  is unchanged. Work around the erratum by invalidating the walk cache
775	  entries for the trampoline before entering the kernel proper.
776
777config QCOM_FALKOR_ERRATUM_1009
778	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
779	default y
780	select ARM64_WORKAROUND_REPEAT_TLBI
781	help
782	  On Falkor v1, the CPU may prematurely complete a DSB following a
783	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
784	  one more time to fix the issue.
785
786	  If unsure, say Y.
787
788config QCOM_QDF2400_ERRATUM_0065
789	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
790	default y
791	help
792	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
793	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
794	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
795
796	  If unsure, say Y.
797
798config QCOM_FALKOR_ERRATUM_E1041
799	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
800	default y
801	help
802	  Falkor CPU may speculatively fetch instructions from an improper
803	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
804	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
805
806	  If unsure, say Y.
807
808config SOCIONEXT_SYNQUACER_PREITS
809	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
810	default y
811	help
812	  Socionext Synquacer SoCs implement a separate h/w block to generate
813	  MSI doorbell writes with non-zero values for the device ID.
814
815	  If unsure, say Y.
816
817endmenu
818
819
820choice
821	prompt "Page size"
822	default ARM64_4K_PAGES
823	help
824	  Page size (translation granule) configuration.
825
826config ARM64_4K_PAGES
827	bool "4KB"
828	help
829	  This feature enables 4KB pages support.
830
831config ARM64_16K_PAGES
832	bool "16KB"
833	help
834	  The system will use 16KB pages support. AArch32 emulation
835	  requires applications compiled with 16K (or a multiple of 16K)
836	  aligned segments.
837
838config ARM64_64K_PAGES
839	bool "64KB"
840	help
841	  This feature enables 64KB pages support (4KB by default)
842	  allowing only two levels of page tables and faster TLB
843	  look-up. AArch32 emulation requires applications compiled
844	  with 64K aligned segments.
845
846endchoice
847
848choice
849	prompt "Virtual address space size"
850	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
851	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
852	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
853	help
854	  Allows choosing one of multiple possible virtual address
855	  space sizes. The level of translation table is determined by
856	  a combination of page size and virtual address space size.
857
858config ARM64_VA_BITS_36
859	bool "36-bit" if EXPERT
860	depends on ARM64_16K_PAGES
861
862config ARM64_VA_BITS_39
863	bool "39-bit"
864	depends on ARM64_4K_PAGES
865
866config ARM64_VA_BITS_42
867	bool "42-bit"
868	depends on ARM64_64K_PAGES
869
870config ARM64_VA_BITS_47
871	bool "47-bit"
872	depends on ARM64_16K_PAGES
873
874config ARM64_VA_BITS_48
875	bool "48-bit"
876
877config ARM64_VA_BITS_52
878	bool "52-bit"
879	depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
880	help
881	  Enable 52-bit virtual addressing for userspace when explicitly
882	  requested via a hint to mmap(). The kernel will also use 52-bit
883	  virtual addresses for its own mappings (provided HW support for
884	  this feature is available, otherwise it reverts to 48-bit).
885
886	  NOTE: Enabling 52-bit virtual addressing in conjunction with
887	  ARMv8.3 Pointer Authentication will result in the PAC being
888	  reduced from 7 bits to 3 bits, which may have a significant
889	  impact on its susceptibility to brute-force attacks.
890
891	  If unsure, select 48-bit virtual addressing instead.
892
893endchoice
894
895config ARM64_FORCE_52BIT
896	bool "Force 52-bit virtual addresses for userspace"
897	depends on ARM64_VA_BITS_52 && EXPERT
898	help
899	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
900	  to maintain compatibility with older software by providing 48-bit VAs
901	  unless a hint is supplied to mmap.
902
903	  This configuration option disables the 48-bit compatibility logic, and
904	  forces all userspace addresses to be 52-bit on HW that supports it. One
905	  should only enable this configuration option for stress testing userspace
906	  memory management code. If unsure say N here.
907
908config ARM64_VA_BITS
909	int
910	default 36 if ARM64_VA_BITS_36
911	default 39 if ARM64_VA_BITS_39
912	default 42 if ARM64_VA_BITS_42
913	default 47 if ARM64_VA_BITS_47
914	default 48 if ARM64_VA_BITS_48
915	default 52 if ARM64_VA_BITS_52
916
917choice
918	prompt "Physical address space size"
919	default ARM64_PA_BITS_48
920	help
921	  Choose the maximum physical address range that the kernel will
922	  support.
923
924config ARM64_PA_BITS_48
925	bool "48-bit"
926
927config ARM64_PA_BITS_52
928	bool "52-bit (ARMv8.2)"
929	depends on ARM64_64K_PAGES
930	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
931	help
932	  Enable support for a 52-bit physical address space, introduced as
933	  part of the ARMv8.2-LPA extension.
934
935	  With this enabled, the kernel will also continue to work on CPUs that
936	  do not support ARMv8.2-LPA, but with some added memory overhead (and
937	  minor performance overhead).
938
939endchoice
940
941config ARM64_PA_BITS
942	int
943	default 48 if ARM64_PA_BITS_48
944	default 52 if ARM64_PA_BITS_52
945
946choice
947	prompt "Endianness"
948	default CPU_LITTLE_ENDIAN
949	help
950	  Select the endianness of data accesses performed by the CPU. Userspace
951	  applications will need to be compiled and linked for the endianness
952	  that is selected here.
953
954config CPU_BIG_ENDIAN
955	bool "Build big-endian kernel"
956	depends on !LD_IS_LLD || LLD_VERSION >= 130000
957	help
958	  Say Y if you plan on running a kernel with a big-endian userspace.
959
960config CPU_LITTLE_ENDIAN
961	bool "Build little-endian kernel"
962	help
963	  Say Y if you plan on running a kernel with a little-endian userspace.
964	  This is usually the case for distributions targeting arm64.
965
966endchoice
967
968config SCHED_MC
969	bool "Multi-core scheduler support"
970	help
971	  Multi-core scheduler support improves the CPU scheduler's decision
972	  making when dealing with multi-core CPU chips at a cost of slightly
973	  increased overhead in some places. If unsure say N here.
974
975config SCHED_SMT
976	bool "SMT scheduler support"
977	help
978	  Improves the CPU scheduler's decision making when dealing with
979	  MultiThreading at a cost of slightly increased overhead in some
980	  places. If unsure say N here.
981
982config NR_CPUS
983	int "Maximum number of CPUs (2-4096)"
984	range 2 4096
985	default "256"
986
987config HOTPLUG_CPU
988	bool "Support for hot-pluggable CPUs"
989	select GENERIC_IRQ_MIGRATION
990	help
991	  Say Y here to experiment with turning CPUs off and on.  CPUs
992	  can be controlled through /sys/devices/system/cpu.
993
994# Common NUMA Features
995config NUMA
996	bool "NUMA Memory Allocation and Scheduler Support"
997	select ACPI_NUMA if ACPI
998	select OF_NUMA
999	help
1000	  Enable NUMA (Non-Uniform Memory Access) support.
1001
1002	  The kernel will try to allocate memory used by a CPU on the
1003	  local memory of the CPU and add some more
1004	  NUMA awareness to the kernel.
1005
1006config NODES_SHIFT
1007	int "Maximum NUMA Nodes (as a power of 2)"
1008	range 1 10
1009	default "4"
1010	depends on NEED_MULTIPLE_NODES
1011	help
1012	  Specify the maximum number of NUMA Nodes available on the target
1013	  system.  Increases memory reserved to accommodate various tables.
1014
1015config USE_PERCPU_NUMA_NODE_ID
1016	def_bool y
1017	depends on NUMA
1018
1019config HAVE_SETUP_PER_CPU_AREA
1020	def_bool y
1021	depends on NUMA
1022
1023config NEED_PER_CPU_EMBED_FIRST_CHUNK
1024	def_bool y
1025	depends on NUMA
1026
1027config HOLES_IN_ZONE
1028	def_bool y
1029
1030source "kernel/Kconfig.hz"
1031
1032config ARCH_SPARSEMEM_ENABLE
1033	def_bool y
1034	select SPARSEMEM_VMEMMAP_ENABLE
1035
1036config ARCH_SPARSEMEM_DEFAULT
1037	def_bool ARCH_SPARSEMEM_ENABLE
1038
1039config ARCH_SELECT_MEMORY_MODEL
1040	def_bool ARCH_SPARSEMEM_ENABLE
1041
1042config ARCH_FLATMEM_ENABLE
1043	def_bool !NUMA
1044
1045config HW_PERF_EVENTS
1046	def_bool y
1047	depends on ARM_PMU
1048
1049config SYS_SUPPORTS_HUGETLBFS
1050	def_bool y
1051
1052config ARCH_WANT_HUGE_PMD_SHARE
1053
1054config ARCH_HAS_CACHE_LINE_SIZE
1055	def_bool y
1056
1057config ARCH_ENABLE_SPLIT_PMD_PTLOCK
1058	def_bool y if PGTABLE_LEVELS > 2
1059
1060# Supported by clang >= 7.0
1061config CC_HAVE_SHADOW_CALL_STACK
1062	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1063
1064config PARAVIRT
1065	bool "Enable paravirtualization code"
1066	help
1067	  This changes the kernel so it can modify itself when it is run
1068	  under a hypervisor, potentially improving performance significantly
1069	  over full virtualization.
1070
1071config PARAVIRT_TIME_ACCOUNTING
1072	bool "Paravirtual steal time accounting"
1073	select PARAVIRT
1074	help
1075	  Select this option to enable fine granularity task steal time
1076	  accounting. Time spent executing other tasks in parallel with
1077	  the current vCPU is discounted from the vCPU power. To account for
1078	  that, there can be a small performance impact.
1079
1080	  If in doubt, say N here.
1081
1082config KEXEC
1083	depends on PM_SLEEP_SMP
1084	select KEXEC_CORE
1085	bool "kexec system call"
1086	help
1087	  kexec is a system call that implements the ability to shutdown your
1088	  current kernel, and to start another kernel.  It is like a reboot
1089	  but it is independent of the system firmware.   And like a reboot
1090	  you can start any kernel with it, not just Linux.
1091
1092config KEXEC_FILE
1093	bool "kexec file based system call"
1094	select KEXEC_CORE
1095	help
1096	  This is new version of kexec system call. This system call is
1097	  file based and takes file descriptors as system call argument
1098	  for kernel and initramfs as opposed to list of segments as
1099	  accepted by previous system call.
1100
1101config KEXEC_SIG
1102	bool "Verify kernel signature during kexec_file_load() syscall"
1103	depends on KEXEC_FILE
1104	help
1105	  Select this option to verify a signature with loaded kernel
1106	  image. If configured, any attempt of loading a image without
1107	  valid signature will fail.
1108
1109	  In addition to that option, you need to enable signature
1110	  verification for the corresponding kernel image type being
1111	  loaded in order for this to work.
1112
1113config KEXEC_IMAGE_VERIFY_SIG
1114	bool "Enable Image signature verification support"
1115	default y
1116	depends on KEXEC_SIG
1117	depends on EFI && SIGNED_PE_FILE_VERIFICATION
1118	help
1119	  Enable Image signature verification support.
1120
1121comment "Support for PE file signature verification disabled"
1122	depends on KEXEC_SIG
1123	depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1124
1125config CRASH_DUMP
1126	bool "Build kdump crash kernel"
1127	help
1128	  Generate crash dump after being started by kexec. This should
1129	  be normally only set in special crash dump kernels which are
1130	  loaded in the main kernel with kexec-tools into a specially
1131	  reserved region and then later executed after a crash by
1132	  kdump/kexec.
1133
1134	  For more details see Documentation/admin-guide/kdump/kdump.rst
1135
1136config TRANS_TABLE
1137	def_bool y
1138	depends on HIBERNATION
1139
1140config XEN_DOM0
1141	def_bool y
1142	depends on XEN
1143
1144config XEN
1145	bool "Xen guest support on ARM64"
1146	depends on ARM64 && OF
1147	select SWIOTLB_XEN
1148	select PARAVIRT
1149	help
1150	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1151
1152config FORCE_MAX_ZONEORDER
1153	int
1154	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1155	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1156	default "11"
1157	help
1158	  The kernel memory allocator divides physically contiguous memory
1159	  blocks into "zones", where each zone is a power of two number of
1160	  pages.  This option selects the largest power of two that the kernel
1161	  keeps in the memory allocator.  If you need to allocate very large
1162	  blocks of physically contiguous memory, then you may need to
1163	  increase this value.
1164
1165	  This config option is actually maximum order plus one. For example,
1166	  a value of 11 means that the largest free memory block is 2^10 pages.
1167
1168	  We make sure that we can allocate upto a HugePage size for each configuration.
1169	  Hence we have :
1170		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1171
1172	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1173	  4M allocations matching the default size used by generic code.
1174
1175config UNMAP_KERNEL_AT_EL0
1176	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1177	default y
1178	help
1179	  Speculation attacks against some high-performance processors can
1180	  be used to bypass MMU permission checks and leak kernel data to
1181	  userspace. This can be defended against by unmapping the kernel
1182	  when running in userspace, mapping it back in on exception entry
1183	  via a trampoline page in the vector table.
1184
1185	  If unsure, say Y.
1186
1187config RODATA_FULL_DEFAULT_ENABLED
1188	bool "Apply r/o permissions of VM areas also to their linear aliases"
1189	default y
1190	help
1191	  Apply read-only attributes of VM areas to the linear alias of
1192	  the backing pages as well. This prevents code or read-only data
1193	  from being modified (inadvertently or intentionally) via another
1194	  mapping of the same memory page. This additional enhancement can
1195	  be turned off at runtime by passing rodata=[off|on] (and turned on
1196	  with rodata=full if this option is set to 'n')
1197
1198	  This requires the linear region to be mapped down to pages,
1199	  which may adversely affect performance in some cases.
1200
1201config ARM64_SW_TTBR0_PAN
1202	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1203	help
1204	  Enabling this option prevents the kernel from accessing
1205	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1206	  zeroed area and reserved ASID. The user access routines
1207	  restore the valid TTBR0_EL1 temporarily.
1208
1209config ARM64_TAGGED_ADDR_ABI
1210	bool "Enable the tagged user addresses syscall ABI"
1211	default y
1212	help
1213	  When this option is enabled, user applications can opt in to a
1214	  relaxed ABI via prctl() allowing tagged addresses to be passed
1215	  to system calls as pointer arguments. For details, see
1216	  Documentation/arm64/tagged-address-abi.rst.
1217
1218menuconfig COMPAT
1219	bool "Kernel support for 32-bit EL0"
1220	depends on ARM64_4K_PAGES || EXPERT
1221	select HAVE_UID16
1222	select OLD_SIGSUSPEND3
1223	select COMPAT_OLD_SIGACTION
1224	help
1225	  This option enables support for a 32-bit EL0 running under a 64-bit
1226	  kernel at EL1. AArch32-specific components such as system calls,
1227	  the user helper functions, VFP support and the ptrace interface are
1228	  handled appropriately by the kernel.
1229
1230	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1231	  that you will only be able to execute AArch32 binaries that were compiled
1232	  with page size aligned segments.
1233
1234	  If you want to execute 32-bit userspace applications, say Y.
1235
1236if COMPAT
1237
1238config KUSER_HELPERS
1239	bool "Enable kuser helpers page for 32-bit applications"
1240	default y
1241	help
1242	  Warning: disabling this option may break 32-bit user programs.
1243
1244	  Provide kuser helpers to compat tasks. The kernel provides
1245	  helper code to userspace in read only form at a fixed location
1246	  to allow userspace to be independent of the CPU type fitted to
1247	  the system. This permits binaries to be run on ARMv4 through
1248	  to ARMv8 without modification.
1249
1250	  See Documentation/arm/kernel_user_helpers.rst for details.
1251
1252	  However, the fixed address nature of these helpers can be used
1253	  by ROP (return orientated programming) authors when creating
1254	  exploits.
1255
1256	  If all of the binaries and libraries which run on your platform
1257	  are built specifically for your platform, and make no use of
1258	  these helpers, then you can turn this option off to hinder
1259	  such exploits. However, in that case, if a binary or library
1260	  relying on those helpers is run, it will not function correctly.
1261
1262	  Say N here only if you are absolutely certain that you do not
1263	  need these helpers; otherwise, the safe option is to say Y.
1264
1265config COMPAT_VDSO
1266	bool "Enable vDSO for 32-bit applications"
1267	depends on !CPU_BIG_ENDIAN && "$(CROSS_COMPILE_COMPAT)" != ""
1268	select GENERIC_COMPAT_VDSO
1269	default y
1270	help
1271	  Place in the process address space of 32-bit applications an
1272	  ELF shared object providing fast implementations of gettimeofday
1273	  and clock_gettime.
1274
1275	  You must have a 32-bit build of glibc 2.22 or later for programs
1276	  to seamlessly take advantage of this.
1277
1278config THUMB2_COMPAT_VDSO
1279	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1280	depends on COMPAT_VDSO
1281	default y
1282	help
1283	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1284	  otherwise with '-marm'.
1285
1286menuconfig ARMV8_DEPRECATED
1287	bool "Emulate deprecated/obsolete ARMv8 instructions"
1288	depends on SYSCTL
1289	help
1290	  Legacy software support may require certain instructions
1291	  that have been deprecated or obsoleted in the architecture.
1292
1293	  Enable this config to enable selective emulation of these
1294	  features.
1295
1296	  If unsure, say Y
1297
1298if ARMV8_DEPRECATED
1299
1300config SWP_EMULATION
1301	bool "Emulate SWP/SWPB instructions"
1302	help
1303	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1304	  they are always undefined. Say Y here to enable software
1305	  emulation of these instructions for userspace using LDXR/STXR.
1306	  This feature can be controlled at runtime with the abi.swp
1307	  sysctl which is disabled by default.
1308
1309	  In some older versions of glibc [<=2.8] SWP is used during futex
1310	  trylock() operations with the assumption that the code will not
1311	  be preempted. This invalid assumption may be more likely to fail
1312	  with SWP emulation enabled, leading to deadlock of the user
1313	  application.
1314
1315	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1316	  on an external transaction monitoring block called a global
1317	  monitor to maintain update atomicity. If your system does not
1318	  implement a global monitor, this option can cause programs that
1319	  perform SWP operations to uncached memory to deadlock.
1320
1321	  If unsure, say Y
1322
1323config CP15_BARRIER_EMULATION
1324	bool "Emulate CP15 Barrier instructions"
1325	help
1326	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1327	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1328	  strongly recommended to use the ISB, DSB, and DMB
1329	  instructions instead.
1330
1331	  Say Y here to enable software emulation of these
1332	  instructions for AArch32 userspace code. When this option is
1333	  enabled, CP15 barrier usage is traced which can help
1334	  identify software that needs updating. This feature can be
1335	  controlled at runtime with the abi.cp15_barrier sysctl.
1336
1337	  If unsure, say Y
1338
1339config SETEND_EMULATION
1340	bool "Emulate SETEND instruction"
1341	help
1342	  The SETEND instruction alters the data-endianness of the
1343	  AArch32 EL0, and is deprecated in ARMv8.
1344
1345	  Say Y here to enable software emulation of the instruction
1346	  for AArch32 userspace code. This feature can be controlled
1347	  at runtime with the abi.setend sysctl.
1348
1349	  Note: All the cpus on the system must have mixed endian support at EL0
1350	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1351	  endian - is hotplugged in after this feature has been enabled, there could
1352	  be unexpected results in the applications.
1353
1354	  If unsure, say Y
1355endif
1356
1357endif
1358
1359menu "ARMv8.1 architectural features"
1360
1361config ARM64_HW_AFDBM
1362	bool "Support for hardware updates of the Access and Dirty page flags"
1363	default y
1364	help
1365	  The ARMv8.1 architecture extensions introduce support for
1366	  hardware updates of the access and dirty information in page
1367	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1368	  capable processors, accesses to pages with PTE_AF cleared will
1369	  set this bit instead of raising an access flag fault.
1370	  Similarly, writes to read-only pages with the DBM bit set will
1371	  clear the read-only bit (AP[2]) instead of raising a
1372	  permission fault.
1373
1374	  Kernels built with this configuration option enabled continue
1375	  to work on pre-ARMv8.1 hardware and the performance impact is
1376	  minimal. If unsure, say Y.
1377
1378config ARM64_PAN
1379	bool "Enable support for Privileged Access Never (PAN)"
1380	default y
1381	help
1382	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1383	 prevents the kernel or hypervisor from accessing user-space (EL0)
1384	 memory directly.
1385
1386	 Choosing this option will cause any unprotected (not using
1387	 copy_to_user et al) memory access to fail with a permission fault.
1388
1389	 The feature is detected at runtime, and will remain as a 'nop'
1390	 instruction if the cpu does not implement the feature.
1391
1392config AS_HAS_LDAPR
1393	def_bool $(as-instr,.arch_extension rcpc)
1394
1395config ARM64_LSE_ATOMICS
1396	bool
1397	default ARM64_USE_LSE_ATOMICS
1398	depends on $(as-instr,.arch_extension lse)
1399
1400config ARM64_USE_LSE_ATOMICS
1401	bool "Atomic instructions"
1402	depends on JUMP_LABEL
1403	default y
1404	help
1405	  As part of the Large System Extensions, ARMv8.1 introduces new
1406	  atomic instructions that are designed specifically to scale in
1407	  very large systems.
1408
1409	  Say Y here to make use of these instructions for the in-kernel
1410	  atomic routines. This incurs a small overhead on CPUs that do
1411	  not support these instructions and requires the kernel to be
1412	  built with binutils >= 2.25 in order for the new instructions
1413	  to be used.
1414
1415config ARM64_VHE
1416	bool "Enable support for Virtualization Host Extensions (VHE)"
1417	default y
1418	help
1419	  Virtualization Host Extensions (VHE) allow the kernel to run
1420	  directly at EL2 (instead of EL1) on processors that support
1421	  it. This leads to better performance for KVM, as they reduce
1422	  the cost of the world switch.
1423
1424	  Selecting this option allows the VHE feature to be detected
1425	  at runtime, and does not affect processors that do not
1426	  implement this feature.
1427
1428endmenu
1429
1430menu "ARMv8.2 architectural features"
1431
1432config ARM64_PMEM
1433	bool "Enable support for persistent memory"
1434	select ARCH_HAS_PMEM_API
1435	select ARCH_HAS_UACCESS_FLUSHCACHE
1436	help
1437	  Say Y to enable support for the persistent memory API based on the
1438	  ARMv8.2 DCPoP feature.
1439
1440	  The feature is detected at runtime, and the kernel will use DC CVAC
1441	  operations if DC CVAP is not supported (following the behaviour of
1442	  DC CVAP itself if the system does not define a point of persistence).
1443
1444config ARM64_RAS_EXTN
1445	bool "Enable support for RAS CPU Extensions"
1446	default y
1447	help
1448	  CPUs that support the Reliability, Availability and Serviceability
1449	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1450	  errors, classify them and report them to software.
1451
1452	  On CPUs with these extensions system software can use additional
1453	  barriers to determine if faults are pending and read the
1454	  classification from a new set of registers.
1455
1456	  Selecting this feature will allow the kernel to use these barriers
1457	  and access the new registers if the system supports the extension.
1458	  Platform RAS features may additionally depend on firmware support.
1459
1460config ARM64_CNP
1461	bool "Enable support for Common Not Private (CNP) translations"
1462	default y
1463	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1464	help
1465	  Common Not Private (CNP) allows translation table entries to
1466	  be shared between different PEs in the same inner shareable
1467	  domain, so the hardware can use this fact to optimise the
1468	  caching of such entries in the TLB.
1469
1470	  Selecting this option allows the CNP feature to be detected
1471	  at runtime, and does not affect PEs that do not implement
1472	  this feature.
1473
1474endmenu
1475
1476menu "ARMv8.3 architectural features"
1477
1478config ARM64_PTR_AUTH
1479	bool "Enable support for pointer authentication"
1480	default y
1481	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1482	# Modern compilers insert a .note.gnu.property section note for PAC
1483	# which is only understood by binutils starting with version 2.33.1.
1484	depends on LD_IS_LLD || LD_VERSION >= 233010000 || (CC_IS_GCC && GCC_VERSION < 90100)
1485	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1486	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1487	help
1488	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1489	  instructions for signing and authenticating pointers against secret
1490	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1491	  and other attacks.
1492
1493	  This option enables these instructions at EL0 (i.e. for userspace).
1494	  Choosing this option will cause the kernel to initialise secret keys
1495	  for each process at exec() time, with these keys being
1496	  context-switched along with the process.
1497
1498	  If the compiler supports the -mbranch-protection or
1499	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1500	  will also cause the kernel itself to be compiled with return address
1501	  protection. In this case, and if the target hardware is known to
1502	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1503	  disabled with minimal loss of protection.
1504
1505	  The feature is detected at runtime. If the feature is not present in
1506	  hardware it will not be advertised to userspace/KVM guest nor will it
1507	  be enabled.
1508
1509	  If the feature is present on the boot CPU but not on a late CPU, then
1510	  the late CPU will be parked. Also, if the boot CPU does not have
1511	  address auth and the late CPU has then the late CPU will still boot
1512	  but with the feature disabled. On such a system, this option should
1513	  not be selected.
1514
1515	  This feature works with FUNCTION_GRAPH_TRACER option only if
1516	  DYNAMIC_FTRACE_WITH_REGS is enabled.
1517
1518config CC_HAS_BRANCH_PROT_PAC_RET
1519	# GCC 9 or later, clang 8 or later
1520	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1521
1522config CC_HAS_SIGN_RETURN_ADDRESS
1523	# GCC 7, 8
1524	def_bool $(cc-option,-msign-return-address=all)
1525
1526config AS_HAS_PAC
1527	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1528
1529config AS_HAS_CFI_NEGATE_RA_STATE
1530	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1531
1532endmenu
1533
1534menu "ARMv8.4 architectural features"
1535
1536config ARM64_AMU_EXTN
1537	bool "Enable support for the Activity Monitors Unit CPU extension"
1538	default y
1539	help
1540	  The activity monitors extension is an optional extension introduced
1541	  by the ARMv8.4 CPU architecture. This enables support for version 1
1542	  of the activity monitors architecture, AMUv1.
1543
1544	  To enable the use of this extension on CPUs that implement it, say Y.
1545
1546	  Note that for architectural reasons, firmware _must_ implement AMU
1547	  support when running on CPUs that present the activity monitors
1548	  extension. The required support is present in:
1549	    * Version 1.5 and later of the ARM Trusted Firmware
1550
1551	  For kernels that have this configuration enabled but boot with broken
1552	  firmware, you may need to say N here until the firmware is fixed.
1553	  Otherwise you may experience firmware panics or lockups when
1554	  accessing the counter registers. Even if you are not observing these
1555	  symptoms, the values returned by the register reads might not
1556	  correctly reflect reality. Most commonly, the value read will be 0,
1557	  indicating that the counter is not enabled.
1558
1559config AS_HAS_ARMV8_4
1560	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1561
1562config ARM64_TLB_RANGE
1563	bool "Enable support for tlbi range feature"
1564	default y
1565	depends on AS_HAS_ARMV8_4
1566	help
1567	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1568	  range of input addresses.
1569
1570	  The feature introduces new assembly instructions, and they were
1571	  support when binutils >= 2.30.
1572
1573endmenu
1574
1575menu "ARMv8.5 architectural features"
1576
1577config AS_HAS_ARMV8_5
1578	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1579
1580config ARM64_BTI
1581	bool "Branch Target Identification support"
1582	default y
1583	help
1584	  Branch Target Identification (part of the ARMv8.5 Extensions)
1585	  provides a mechanism to limit the set of locations to which computed
1586	  branch instructions such as BR or BLR can jump.
1587
1588	  To make use of BTI on CPUs that support it, say Y.
1589
1590	  BTI is intended to provide complementary protection to other control
1591	  flow integrity protection mechanisms, such as the Pointer
1592	  authentication mechanism provided as part of the ARMv8.3 Extensions.
1593	  For this reason, it does not make sense to enable this option without
1594	  also enabling support for pointer authentication.  Thus, when
1595	  enabling this option you should also select ARM64_PTR_AUTH=y.
1596
1597	  Userspace binaries must also be specifically compiled to make use of
1598	  this mechanism.  If you say N here or the hardware does not support
1599	  BTI, such binaries can still run, but you get no additional
1600	  enforcement of branch destinations.
1601
1602config ARM64_BTI_KERNEL
1603	bool "Use Branch Target Identification for kernel"
1604	default y
1605	depends on ARM64_BTI
1606	depends on ARM64_PTR_AUTH
1607	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1608	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1609	depends on !CC_IS_GCC || GCC_VERSION >= 100100
1610	depends on !(CC_IS_CLANG && GCOV_KERNEL)
1611	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1612	help
1613	  Build the kernel with Branch Target Identification annotations
1614	  and enable enforcement of this for kernel code. When this option
1615	  is enabled and the system supports BTI all kernel code including
1616	  modular code must have BTI enabled.
1617
1618config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1619	# GCC 9 or later, clang 8 or later
1620	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1621
1622config ARM64_E0PD
1623	bool "Enable support for E0PD"
1624	default y
1625	help
1626	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
1627	  that EL0 accesses made via TTBR1 always fault in constant time,
1628	  providing similar benefits to KASLR as those provided by KPTI, but
1629	  with lower overhead and without disrupting legitimate access to
1630	  kernel memory such as SPE.
1631
1632	  This option enables E0PD for TTBR1 where available.
1633
1634config ARCH_RANDOM
1635	bool "Enable support for random number generation"
1636	default y
1637	help
1638	  Random number generation (part of the ARMv8.5 Extensions)
1639	  provides a high bandwidth, cryptographically secure
1640	  hardware random number generator.
1641
1642config ARM64_AS_HAS_MTE
1643	# Initial support for MTE went in binutils 2.32.0, checked with
1644	# ".arch armv8.5-a+memtag" below. However, this was incomplete
1645	# as a late addition to the final architecture spec (LDGM/STGM)
1646	# is only supported in the newer 2.32.x and 2.33 binutils
1647	# versions, hence the extra "stgm" instruction check below.
1648	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1649
1650config ARM64_MTE
1651	bool "Memory Tagging Extension support"
1652	default y
1653	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1654	depends on AS_HAS_ARMV8_5
1655	# Required for tag checking in the uaccess routines
1656	depends on ARM64_PAN
1657	select ARCH_USES_HIGH_VMA_FLAGS
1658	help
1659	  Memory Tagging (part of the ARMv8.5 Extensions) provides
1660	  architectural support for run-time, always-on detection of
1661	  various classes of memory error to aid with software debugging
1662	  to eliminate vulnerabilities arising from memory-unsafe
1663	  languages.
1664
1665	  This option enables the support for the Memory Tagging
1666	  Extension at EL0 (i.e. for userspace).
1667
1668	  Selecting this option allows the feature to be detected at
1669	  runtime. Any secondary CPU not implementing this feature will
1670	  not be allowed a late bring-up.
1671
1672	  Userspace binaries that want to use this feature must
1673	  explicitly opt in. The mechanism for the userspace is
1674	  described in:
1675
1676	  Documentation/arm64/memory-tagging-extension.rst.
1677
1678endmenu
1679
1680config ARM64_SVE
1681	bool "ARM Scalable Vector Extension support"
1682	default y
1683	depends on !KVM || ARM64_VHE
1684	help
1685	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1686	  execution state which complements and extends the SIMD functionality
1687	  of the base architecture to support much larger vectors and to enable
1688	  additional vectorisation opportunities.
1689
1690	  To enable use of this extension on CPUs that implement it, say Y.
1691
1692	  On CPUs that support the SVE2 extensions, this option will enable
1693	  those too.
1694
1695	  Note that for architectural reasons, firmware _must_ implement SVE
1696	  support when running on SVE capable hardware.  The required support
1697	  is present in:
1698
1699	    * version 1.5 and later of the ARM Trusted Firmware
1700	    * the AArch64 boot wrapper since commit 5e1261e08abf
1701	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1702
1703	  For other firmware implementations, consult the firmware documentation
1704	  or vendor.
1705
1706	  If you need the kernel to boot on SVE-capable hardware with broken
1707	  firmware, you may need to say N here until you get your firmware
1708	  fixed.  Otherwise, you may experience firmware panics or lockups when
1709	  booting the kernel.  If unsure and you are not observing these
1710	  symptoms, you should assume that it is safe to say Y.
1711
1712	  CPUs that support SVE are architecturally required to support the
1713	  Virtualization Host Extensions (VHE), so the kernel makes no
1714	  provision for supporting SVE alongside KVM without VHE enabled.
1715	  Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1716	  KVM in the same kernel image.
1717
1718config ARM64_MODULE_PLTS
1719	bool "Use PLTs to allow module memory to spill over into vmalloc area"
1720	depends on MODULES
1721	select HAVE_MOD_ARCH_SPECIFIC
1722	help
1723	  Allocate PLTs when loading modules so that jumps and calls whose
1724	  targets are too far away for their relative offsets to be encoded
1725	  in the instructions themselves can be bounced via veneers in the
1726	  module's PLT. This allows modules to be allocated in the generic
1727	  vmalloc area after the dedicated module memory area has been
1728	  exhausted.
1729
1730	  When running with address space randomization (KASLR), the module
1731	  region itself may be too far away for ordinary relative jumps and
1732	  calls, and so in that case, module PLTs are required and cannot be
1733	  disabled.
1734
1735	  Specific errata workaround(s) might also force module PLTs to be
1736	  enabled (ARM64_ERRATUM_843419).
1737
1738config ARM64_PSEUDO_NMI
1739	bool "Support for NMI-like interrupts"
1740	select ARM_GIC_V3
1741	help
1742	  Adds support for mimicking Non-Maskable Interrupts through the use of
1743	  GIC interrupt priority. This support requires version 3 or later of
1744	  ARM GIC.
1745
1746	  This high priority configuration for interrupts needs to be
1747	  explicitly enabled by setting the kernel parameter
1748	  "irqchip.gicv3_pseudo_nmi" to 1.
1749
1750	  If unsure, say N
1751
1752if ARM64_PSEUDO_NMI
1753config ARM64_DEBUG_PRIORITY_MASKING
1754	bool "Debug interrupt priority masking"
1755	help
1756	  This adds runtime checks to functions enabling/disabling
1757	  interrupts when using priority masking. The additional checks verify
1758	  the validity of ICC_PMR_EL1 when calling concerned functions.
1759
1760	  If unsure, say N
1761endif
1762
1763config RELOCATABLE
1764	bool "Build a relocatable kernel image" if EXPERT
1765	select ARCH_HAS_RELR
1766	default y
1767	help
1768	  This builds the kernel as a Position Independent Executable (PIE),
1769	  which retains all relocation metadata required to relocate the
1770	  kernel binary at runtime to a different virtual address than the
1771	  address it was linked at.
1772	  Since AArch64 uses the RELA relocation format, this requires a
1773	  relocation pass at runtime even if the kernel is loaded at the
1774	  same address it was linked at.
1775
1776config RANDOMIZE_BASE
1777	bool "Randomize the address of the kernel image"
1778	select ARM64_MODULE_PLTS if MODULES
1779	select RELOCATABLE
1780	help
1781	  Randomizes the virtual address at which the kernel image is
1782	  loaded, as a security feature that deters exploit attempts
1783	  relying on knowledge of the location of kernel internals.
1784
1785	  It is the bootloader's job to provide entropy, by passing a
1786	  random u64 value in /chosen/kaslr-seed at kernel entry.
1787
1788	  When booting via the UEFI stub, it will invoke the firmware's
1789	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1790	  to the kernel proper. In addition, it will randomise the physical
1791	  location of the kernel Image as well.
1792
1793	  If unsure, say N.
1794
1795config RANDOMIZE_MODULE_REGION_FULL
1796	bool "Randomize the module region over a 4 GB range"
1797	depends on RANDOMIZE_BASE
1798	default y
1799	help
1800	  Randomizes the location of the module region inside a 4 GB window
1801	  covering the core kernel. This way, it is less likely for modules
1802	  to leak information about the location of core kernel data structures
1803	  but it does imply that function calls between modules and the core
1804	  kernel will need to be resolved via veneers in the module PLT.
1805
1806	  When this option is not set, the module region will be randomized over
1807	  a limited range that contains the [_stext, _etext] interval of the
1808	  core kernel, so branch relocations are always in range.
1809
1810config CC_HAVE_STACKPROTECTOR_SYSREG
1811	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1812
1813config STACKPROTECTOR_PER_TASK
1814	def_bool y
1815	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1816
1817endmenu
1818
1819menu "Boot options"
1820
1821config ARM64_ACPI_PARKING_PROTOCOL
1822	bool "Enable support for the ARM64 ACPI parking protocol"
1823	depends on ACPI
1824	help
1825	  Enable support for the ARM64 ACPI parking protocol. If disabled
1826	  the kernel will not allow booting through the ARM64 ACPI parking
1827	  protocol even if the corresponding data is present in the ACPI
1828	  MADT table.
1829
1830config CMDLINE
1831	string "Default kernel command string"
1832	default ""
1833	help
1834	  Provide a set of default command-line options at build time by
1835	  entering them here. As a minimum, you should specify the the
1836	  root device (e.g. root=/dev/nfs).
1837
1838choice
1839	prompt "Kernel command line type" if CMDLINE != ""
1840	default CMDLINE_FROM_BOOTLOADER
1841	help
1842	  Choose how the kernel will handle the provided default kernel
1843	  command line string.
1844
1845config CMDLINE_FROM_BOOTLOADER
1846	bool "Use bootloader kernel arguments if available"
1847	help
1848	  Uses the command-line options passed by the boot loader. If
1849	  the boot loader doesn't provide any, the default kernel command
1850	  string provided in CMDLINE will be used.
1851
1852config CMDLINE_EXTEND
1853	bool "Extend bootloader kernel arguments"
1854	help
1855	  The command-line arguments provided by the boot loader will be
1856	  appended to the default kernel command string.
1857
1858config CMDLINE_FORCE
1859	bool "Always use the default kernel command string"
1860	help
1861	  Always use the default kernel command string, even if the boot
1862	  loader passes other arguments to the kernel.
1863	  This is useful if you cannot or don't want to change the
1864	  command-line options your boot loader passes to the kernel.
1865
1866endchoice
1867
1868config EFI_STUB
1869	bool
1870
1871config EFI
1872	bool "UEFI runtime support"
1873	depends on OF && !CPU_BIG_ENDIAN
1874	depends on KERNEL_MODE_NEON
1875	select ARCH_SUPPORTS_ACPI
1876	select LIBFDT
1877	select UCS2_STRING
1878	select EFI_PARAMS_FROM_FDT
1879	select EFI_RUNTIME_WRAPPERS
1880	select EFI_STUB
1881	select EFI_GENERIC_STUB
1882	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1883	default y
1884	help
1885	  This option provides support for runtime services provided
1886	  by UEFI firmware (such as non-volatile variables, realtime
1887          clock, and platform reset). A UEFI stub is also provided to
1888	  allow the kernel to be booted as an EFI application. This
1889	  is only useful on systems that have UEFI firmware.
1890
1891config DMI
1892	bool "Enable support for SMBIOS (DMI) tables"
1893	depends on EFI
1894	default y
1895	help
1896	  This enables SMBIOS/DMI feature for systems.
1897
1898	  This option is only useful on systems that have UEFI firmware.
1899	  However, even with this option, the resultant kernel should
1900	  continue to boot on existing non-UEFI platforms.
1901
1902endmenu
1903
1904config SYSVIPC_COMPAT
1905	def_bool y
1906	depends on COMPAT && SYSVIPC
1907
1908config ARCH_ENABLE_HUGEPAGE_MIGRATION
1909	def_bool y
1910	depends on HUGETLB_PAGE && MIGRATION
1911
1912config ARCH_ENABLE_THP_MIGRATION
1913	def_bool y
1914	depends on TRANSPARENT_HUGEPAGE
1915
1916menu "Power management options"
1917
1918source "kernel/power/Kconfig"
1919
1920config ARCH_HIBERNATION_POSSIBLE
1921	def_bool y
1922	depends on CPU_PM
1923
1924config ARCH_HIBERNATION_HEADER
1925	def_bool y
1926	depends on HIBERNATION
1927
1928config ARCH_SUSPEND_POSSIBLE
1929	def_bool y
1930
1931endmenu
1932
1933menu "CPU Power Management"
1934
1935source "drivers/cpuidle/Kconfig"
1936
1937source "drivers/cpufreq/Kconfig"
1938
1939endmenu
1940
1941source "drivers/firmware/Kconfig"
1942
1943source "drivers/acpi/Kconfig"
1944
1945source "arch/arm64/kvm/Kconfig"
1946
1947if CRYPTO
1948source "arch/arm64/crypto/Kconfig"
1949endif
1950