1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * linux/arch/arm/vfp/vfpinstr.h 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright (C) 2004 ARM Limited. 61da177e4SLinus Torvalds * Written by Deep Blue Solutions Limited. 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * VFP instruction masks. 91da177e4SLinus Torvalds */ 101da177e4SLinus Torvalds #define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000) 111da177e4SLinus Torvalds #define INST_CPRT(inst) ((inst) & (1 << 4)) 121da177e4SLinus Torvalds #define INST_CPRT_L(inst) ((inst) & (1 << 20)) 131da177e4SLinus Torvalds #define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12) 141da177e4SLinus Torvalds #define INST_CPRT_OP(inst) (((inst) >> 21) & 7) 151da177e4SLinus Torvalds #define INST_CPNUM(inst) ((inst) & 0xf00) 161da177e4SLinus Torvalds #define CPNUM(cp) ((cp) << 8) 171da177e4SLinus Torvalds 181da177e4SLinus Torvalds #define FOP_MASK (0x00b00040) 191da177e4SLinus Torvalds #define FOP_FMAC (0x00000000) 201da177e4SLinus Torvalds #define FOP_FNMAC (0x00000040) 211da177e4SLinus Torvalds #define FOP_FMSC (0x00100000) 221da177e4SLinus Torvalds #define FOP_FNMSC (0x00100040) 231da177e4SLinus Torvalds #define FOP_FMUL (0x00200000) 241da177e4SLinus Torvalds #define FOP_FNMUL (0x00200040) 251da177e4SLinus Torvalds #define FOP_FADD (0x00300000) 261da177e4SLinus Torvalds #define FOP_FSUB (0x00300040) 271da177e4SLinus Torvalds #define FOP_FDIV (0x00800000) 281da177e4SLinus Torvalds #define FOP_EXT (0x00b00040) 291da177e4SLinus Torvalds 301da177e4SLinus Torvalds #define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4) 311da177e4SLinus Torvalds 321da177e4SLinus Torvalds #define FEXT_MASK (0x000f0080) 331da177e4SLinus Torvalds #define FEXT_FCPY (0x00000000) 341da177e4SLinus Torvalds #define FEXT_FABS (0x00000080) 351da177e4SLinus Torvalds #define FEXT_FNEG (0x00010000) 361da177e4SLinus Torvalds #define FEXT_FSQRT (0x00010080) 371da177e4SLinus Torvalds #define FEXT_FCMP (0x00040000) 381da177e4SLinus Torvalds #define FEXT_FCMPE (0x00040080) 391da177e4SLinus Torvalds #define FEXT_FCMPZ (0x00050000) 401da177e4SLinus Torvalds #define FEXT_FCMPEZ (0x00050080) 411da177e4SLinus Torvalds #define FEXT_FCVT (0x00070080) 421da177e4SLinus Torvalds #define FEXT_FUITO (0x00080000) 431da177e4SLinus Torvalds #define FEXT_FSITO (0x00080080) 441da177e4SLinus Torvalds #define FEXT_FTOUI (0x000c0000) 451da177e4SLinus Torvalds #define FEXT_FTOUIZ (0x000c0080) 461da177e4SLinus Torvalds #define FEXT_FTOSI (0x000d0000) 471da177e4SLinus Torvalds #define FEXT_FTOSIZ (0x000d0080) 481da177e4SLinus Torvalds 491da177e4SLinus Torvalds #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) 501da177e4SLinus Torvalds 511da177e4SLinus Torvalds #define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) 5225ebee02SCatalin Marinas #define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18) 531da177e4SLinus Torvalds #define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5) 5425ebee02SCatalin Marinas #define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1) 551da177e4SLinus Torvalds #define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) 5625ebee02SCatalin Marinas #define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3) 571da177e4SLinus Torvalds 581da177e4SLinus Torvalds #define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00) 591da177e4SLinus Torvalds 601da177e4SLinus Torvalds #define FPSCR_N (1 << 31) 611da177e4SLinus Torvalds #define FPSCR_Z (1 << 30) 621da177e4SLinus Torvalds #define FPSCR_C (1 << 29) 631da177e4SLinus Torvalds #define FPSCR_V (1 << 28) 641da177e4SLinus Torvalds 652cbd1cc3SStefan Agner #ifdef CONFIG_AS_VFP_VMRS_FPINST 662cbd1cc3SStefan Agner 672cbd1cc3SStefan Agner #define fmrx(_vfp_) ({ \ 682cbd1cc3SStefan Agner u32 __v; \ 69*9fc60f2bSCalvin Owens asm volatile (".fpu vfpv2\n" \ 702cbd1cc3SStefan Agner "vmrs %0, " #_vfp_ \ 712cbd1cc3SStefan Agner : "=r" (__v) : : "cc"); \ 722cbd1cc3SStefan Agner __v; \ 732cbd1cc3SStefan Agner }) 742cbd1cc3SStefan Agner 75*9fc60f2bSCalvin Owens #define fmxr(_vfp_, _var_) ({ \ 76*9fc60f2bSCalvin Owens asm volatile (".fpu vfpv2\n" \ 772cbd1cc3SStefan Agner "vmsr " #_vfp_ ", %0" \ 78*9fc60f2bSCalvin Owens : : "r" (_var_) : "cc"); \ 79*9fc60f2bSCalvin Owens }) 802cbd1cc3SStefan Agner 812cbd1cc3SStefan Agner #else 822cbd1cc3SStefan Agner 831da177e4SLinus Torvalds #define vfpreg(_vfp_) #_vfp_ 841da177e4SLinus Torvalds 851da177e4SLinus Torvalds #define fmrx(_vfp_) ({ \ 861da177e4SLinus Torvalds u32 __v; \ 87*9fc60f2bSCalvin Owens asm volatile ("mrc p10, 7, %0, " vfpreg(_vfp_) "," \ 88*9fc60f2bSCalvin Owens "cr0, 0 @ fmrx %0, " #_vfp_ \ 896a39dd62SDaniel Jacobowitz : "=r" (__v) : : "cc"); \ 901da177e4SLinus Torvalds __v; \ 911da177e4SLinus Torvalds }) 921da177e4SLinus Torvalds 93*9fc60f2bSCalvin Owens #define fmxr(_vfp_, _var_) ({ \ 94*9fc60f2bSCalvin Owens asm volatile ("mcr p10, 7, %0, " vfpreg(_vfp_) "," \ 95*9fc60f2bSCalvin Owens "cr0, 0 @ fmxr " #_vfp_ ", %0" \ 96*9fc60f2bSCalvin Owens : : "r" (_var_) : "cc"); \ 97*9fc60f2bSCalvin Owens }) 981da177e4SLinus Torvalds 992cbd1cc3SStefan Agner #endif 1002cbd1cc3SStefan Agner 1011da177e4SLinus Torvalds u32 vfp_single_cpdo(u32 inst, u32 fpscr); 1021da177e4SLinus Torvalds u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs); 1031da177e4SLinus Torvalds 1041da177e4SLinus Torvalds u32 vfp_double_cpdo(u32 inst, u32 fpscr); 105