1b2f427a1SAndrew Lunn /*
2b2f427a1SAndrew Lunn * arch/arm/plat-orion/mpp.c
3b2f427a1SAndrew Lunn *
4b2f427a1SAndrew Lunn * MPP functions for Marvell orion SoCs
5b2f427a1SAndrew Lunn *
6b2f427a1SAndrew Lunn * This file is licensed under the terms of the GNU General Public
7b2f427a1SAndrew Lunn * License version 2. This program is licensed "as is" without any
8b2f427a1SAndrew Lunn * warranty of any kind, whether express or implied.
9b2f427a1SAndrew Lunn */
10b2f427a1SAndrew Lunn
11b2f427a1SAndrew Lunn #include <linux/kernel.h>
12b2f427a1SAndrew Lunn #include <linux/init.h>
13b2f427a1SAndrew Lunn #include <linux/mbus.h>
14b2f427a1SAndrew Lunn #include <linux/io.h>
15b2f427a1SAndrew Lunn #include <linux/gpio.h>
16ce91574cSRob Herring #include <plat/orion-gpio.h>
17b2f427a1SAndrew Lunn #include <plat/mpp.h>
18b2f427a1SAndrew Lunn
19b2f427a1SAndrew Lunn /* Address of the ith MPP control register */
mpp_ctrl_addr(unsigned int i,void __iomem * dev_bus)205a2f5501SThomas Petazzoni static __init void __iomem *mpp_ctrl_addr(unsigned int i,
215a2f5501SThomas Petazzoni void __iomem *dev_bus)
22b2f427a1SAndrew Lunn {
23b2f427a1SAndrew Lunn return dev_bus + (i) * 4;
24b2f427a1SAndrew Lunn }
25b2f427a1SAndrew Lunn
26b2f427a1SAndrew Lunn
orion_mpp_conf(unsigned int * mpp_list,unsigned int variant_mask,unsigned int mpp_max,void __iomem * dev_bus)27b2f427a1SAndrew Lunn void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
285a2f5501SThomas Petazzoni unsigned int mpp_max, void __iomem *dev_bus)
29b2f427a1SAndrew Lunn {
30b2f427a1SAndrew Lunn unsigned int mpp_nr_regs = (1 + mpp_max/8);
31*d4f79cb8SArnd Bergmann u32 mpp_ctrl[8];
32b2f427a1SAndrew Lunn int i;
33b2f427a1SAndrew Lunn
34b2f427a1SAndrew Lunn printk(KERN_DEBUG "initial MPP regs:");
35*d4f79cb8SArnd Bergmann if (mpp_nr_regs > ARRAY_SIZE(mpp_ctrl)) {
36*d4f79cb8SArnd Bergmann printk(KERN_ERR "orion_mpp_conf: invalid mpp_max\n");
37*d4f79cb8SArnd Bergmann return;
38*d4f79cb8SArnd Bergmann }
39*d4f79cb8SArnd Bergmann
40b2f427a1SAndrew Lunn for (i = 0; i < mpp_nr_regs; i++) {
41b2f427a1SAndrew Lunn mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
42b2f427a1SAndrew Lunn printk(" %08x", mpp_ctrl[i]);
43b2f427a1SAndrew Lunn }
44b2f427a1SAndrew Lunn printk("\n");
45b2f427a1SAndrew Lunn
46b2f427a1SAndrew Lunn for ( ; *mpp_list; mpp_list++) {
47b2f427a1SAndrew Lunn unsigned int num = MPP_NUM(*mpp_list);
48b2f427a1SAndrew Lunn unsigned int sel = MPP_SEL(*mpp_list);
49b2f427a1SAndrew Lunn int shift, gpio_mode;
50b2f427a1SAndrew Lunn
51b2f427a1SAndrew Lunn if (num > mpp_max) {
52b2f427a1SAndrew Lunn printk(KERN_ERR "orion_mpp_conf: invalid MPP "
53b2f427a1SAndrew Lunn "number (%u)\n", num);
54b2f427a1SAndrew Lunn continue;
55b2f427a1SAndrew Lunn }
56830f8b91SGerlando Falauto if (variant_mask && !(*mpp_list & variant_mask)) {
57b2f427a1SAndrew Lunn printk(KERN_WARNING
58b2f427a1SAndrew Lunn "orion_mpp_conf: requested MPP%u config "
59b2f427a1SAndrew Lunn "unavailable on this hardware\n", num);
60b2f427a1SAndrew Lunn continue;
61b2f427a1SAndrew Lunn }
62b2f427a1SAndrew Lunn
63b2f427a1SAndrew Lunn shift = (num & 7) << 2;
64b2f427a1SAndrew Lunn mpp_ctrl[num / 8] &= ~(0xf << shift);
65b2f427a1SAndrew Lunn mpp_ctrl[num / 8] |= sel << shift;
66b2f427a1SAndrew Lunn
67b2f427a1SAndrew Lunn gpio_mode = 0;
68b2f427a1SAndrew Lunn if (*mpp_list & MPP_INPUT_MASK)
69b2f427a1SAndrew Lunn gpio_mode |= GPIO_INPUT_OK;
70b2f427a1SAndrew Lunn if (*mpp_list & MPP_OUTPUT_MASK)
71b2f427a1SAndrew Lunn gpio_mode |= GPIO_OUTPUT_OK;
72b0654037SAndrew Lunn
73b2f427a1SAndrew Lunn orion_gpio_set_valid(num, gpio_mode);
74b2f427a1SAndrew Lunn }
75b2f427a1SAndrew Lunn
76b2f427a1SAndrew Lunn printk(KERN_DEBUG " final MPP regs:");
77b2f427a1SAndrew Lunn for (i = 0; i < mpp_nr_regs; i++) {
78b2f427a1SAndrew Lunn writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
79b2f427a1SAndrew Lunn printk(" %08x", mpp_ctrl[i]);
80b2f427a1SAndrew Lunn }
81b2f427a1SAndrew Lunn printk("\n");
82b2f427a1SAndrew Lunn }
83