1b6d1c33aSAndrew Lunn /* 2b6d1c33aSAndrew Lunn * arch/arm/plat-orion/include/plat/addr-map.h 3b6d1c33aSAndrew Lunn * 4b6d1c33aSAndrew Lunn * Marvell Orion SoC address map handling. 5b6d1c33aSAndrew Lunn * 6b6d1c33aSAndrew Lunn * This file is licensed under the terms of the GNU General Public 7b6d1c33aSAndrew Lunn * License version 2. This program is licensed "as is" without any 8b6d1c33aSAndrew Lunn * warranty of any kind, whether express or implied. 9b6d1c33aSAndrew Lunn */ 10b6d1c33aSAndrew Lunn 11b6d1c33aSAndrew Lunn #ifndef __PLAT_ADDR_MAP_H 12b6d1c33aSAndrew Lunn #define __PLAT_ADDR_MAP_H 13b6d1c33aSAndrew Lunn 1445173d5eSAndrew Lunn extern struct mbus_dram_target_info orion_mbus_dram_info; 1545173d5eSAndrew Lunn 16b6d1c33aSAndrew Lunn struct orion_addr_map_cfg { 17b6d1c33aSAndrew Lunn const int num_wins; /* Total number of windows */ 18b6d1c33aSAndrew Lunn const int remappable_wins; 1987d13641SThomas Petazzoni void __iomem *bridge_virt_base; 20*722202e1SGregory CLEMENT int hw_io_coherency; 21b6d1c33aSAndrew Lunn 22b6d1c33aSAndrew Lunn /* If NULL, the default cpu_win_can_remap will be used, using 23b6d1c33aSAndrew Lunn the value in remappable_wins */ 24b6d1c33aSAndrew Lunn int (*cpu_win_can_remap) (const struct orion_addr_map_cfg *cfg, 25b6d1c33aSAndrew Lunn const int win); 26b6d1c33aSAndrew Lunn /* If NULL, the default win_cfg_base will be used, using the 27b6d1c33aSAndrew Lunn value in bridge_virt_base */ 28b6d1c33aSAndrew Lunn void __iomem *(*win_cfg_base) (const struct orion_addr_map_cfg *cfg, 29b6d1c33aSAndrew Lunn const int win); 30b6d1c33aSAndrew Lunn }; 31b6d1c33aSAndrew Lunn 32b6d1c33aSAndrew Lunn /* 33b6d1c33aSAndrew Lunn * Information needed to setup one address mapping. 34b6d1c33aSAndrew Lunn */ 35b6d1c33aSAndrew Lunn struct orion_addr_map_info { 36b6d1c33aSAndrew Lunn const int win; 37b6d1c33aSAndrew Lunn const u32 base; 38b6d1c33aSAndrew Lunn const u32 size; 39b6d1c33aSAndrew Lunn const u8 target; 40b6d1c33aSAndrew Lunn const u8 attr; 41b6d1c33aSAndrew Lunn const int remap; 42b6d1c33aSAndrew Lunn }; 43b6d1c33aSAndrew Lunn 44b6d1c33aSAndrew Lunn void __init orion_config_wins(struct orion_addr_map_cfg *cfg, 45b6d1c33aSAndrew Lunn const struct orion_addr_map_info *info); 46b6d1c33aSAndrew Lunn 47b6d1c33aSAndrew Lunn void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg, 48b6d1c33aSAndrew Lunn const int win, const u32 base, 49b6d1c33aSAndrew Lunn const u32 size, const u8 target, 50b6d1c33aSAndrew Lunn const u8 attr, const int remap); 51b6d1c33aSAndrew Lunn 52b6d1c33aSAndrew Lunn void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, 539b7b7d8bSThomas Petazzoni const void __iomem *ddr_window_cpu_base); 54b6d1c33aSAndrew Lunn #endif 55