11da177e4SLinus Torvalds/* 21da177e4SLinus Torvalds NetWinder Floating Point Emulator 31da177e4SLinus Torvalds (c) Rebel.COM, 1998,1999 41da177e4SLinus Torvalds 51da177e4SLinus Torvalds Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 61da177e4SLinus Torvalds 71da177e4SLinus Torvalds This program is free software; you can redistribute it and/or modify 81da177e4SLinus Torvalds it under the terms of the GNU General Public License as published by 91da177e4SLinus Torvalds the Free Software Foundation; either version 2 of the License, or 101da177e4SLinus Torvalds (at your option) any later version. 111da177e4SLinus Torvalds 121da177e4SLinus Torvalds This program is distributed in the hope that it will be useful, 131da177e4SLinus Torvalds but WITHOUT ANY WARRANTY; without even the implied warranty of 141da177e4SLinus Torvalds MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 151da177e4SLinus Torvalds GNU General Public License for more details. 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds You should have received a copy of the GNU General Public License 181da177e4SLinus Torvalds along with this program; if not, write to the Free Software 191da177e4SLinus Torvalds Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 201da177e4SLinus Torvalds*/ 211da177e4SLinus Torvalds 221da177e4SLinus Torvaldsstatic inline unsigned long readRegister(const unsigned int nReg) 231da177e4SLinus Torvalds{ 241da177e4SLinus Torvalds /* Note: The CPU thinks it has dealt with the current instruction. 251da177e4SLinus Torvalds As a result the program counter has been advanced to the next 261da177e4SLinus Torvalds instruction, and points 4 bytes beyond the actual instruction 271da177e4SLinus Torvalds that caused the invalid instruction trap to occur. We adjust 281da177e4SLinus Torvalds for this in this routine. LDF/STF instructions with Rn = PC 291da177e4SLinus Torvalds depend on the PC being correct, as they use PC+8 in their 301da177e4SLinus Torvalds address calculations. */ 31*b66da4a4SRussell King struct pt_regs *regs = GET_USERREG(); 32*b66da4a4SRussell King unsigned int val = regs->uregs[nReg]; 331da177e4SLinus Torvalds if (REG_PC == nReg) 341da177e4SLinus Torvalds val -= 4; 351da177e4SLinus Torvalds return val; 361da177e4SLinus Torvalds} 371da177e4SLinus Torvalds 381da177e4SLinus Torvaldsstatic inline void 391da177e4SLinus TorvaldswriteRegister(const unsigned int nReg, const unsigned long val) 401da177e4SLinus Torvalds{ 41*b66da4a4SRussell King struct pt_regs *regs = GET_USERREG(); 42*b66da4a4SRussell King regs->uregs[nReg] = val; 431da177e4SLinus Torvalds} 441da177e4SLinus Torvalds 451da177e4SLinus Torvaldsstatic inline unsigned long readCPSR(void) 461da177e4SLinus Torvalds{ 471da177e4SLinus Torvalds return (readRegister(REG_CPSR)); 481da177e4SLinus Torvalds} 491da177e4SLinus Torvalds 501da177e4SLinus Torvaldsstatic inline void writeCPSR(const unsigned long val) 511da177e4SLinus Torvalds{ 521da177e4SLinus Torvalds writeRegister(REG_CPSR, val); 531da177e4SLinus Torvalds} 541da177e4SLinus Torvalds 551da177e4SLinus Torvaldsstatic inline unsigned long readConditionCodes(void) 561da177e4SLinus Torvalds{ 571da177e4SLinus Torvalds#ifdef __FPEM_TEST__ 581da177e4SLinus Torvalds return (0); 591da177e4SLinus Torvalds#else 601da177e4SLinus Torvalds return (readCPSR() & CC_MASK); 611da177e4SLinus Torvalds#endif 621da177e4SLinus Torvalds} 631da177e4SLinus Torvalds 641da177e4SLinus Torvaldsstatic inline void writeConditionCodes(const unsigned long val) 651da177e4SLinus Torvalds{ 66*b66da4a4SRussell King struct pt_regs *regs = GET_USERREG(); 671da177e4SLinus Torvalds unsigned long rval; 681da177e4SLinus Torvalds /* 691da177e4SLinus Torvalds * Operate directly on userRegisters since 701da177e4SLinus Torvalds * the CPSR may be the PC register itself. 711da177e4SLinus Torvalds */ 72*b66da4a4SRussell King rval = regs->ARM_cpsr & ~CC_MASK; 73*b66da4a4SRussell King regs->ARM_cpsr = rval | (val & CC_MASK); 741da177e4SLinus Torvalds} 75