1 /* 2 * Based on linux/arch/arm/mm/nommu.c 3 * 4 * ARM PMSAv7 supporting functions. 5 */ 6 7 #include <linux/memblock.h> 8 9 #include <asm/cp15.h> 10 #include <asm/cputype.h> 11 #include <asm/mpu.h> 12 13 #include "mm.h" 14 15 static unsigned int __initdata mpu_min_region_order; 16 static unsigned int __initdata mpu_max_regions; 17 18 #define DRBAR __ACCESS_CP15(c6, 0, c1, 0) 19 #define IRBAR __ACCESS_CP15(c6, 0, c1, 1) 20 #define DRSR __ACCESS_CP15(c6, 0, c1, 2) 21 #define IRSR __ACCESS_CP15(c6, 0, c1, 3) 22 #define DRACR __ACCESS_CP15(c6, 0, c1, 4) 23 #define IRACR __ACCESS_CP15(c6, 0, c1, 5) 24 #define RNGNR __ACCESS_CP15(c6, 0, c2, 0) 25 26 /* Region number */ 27 static inline void rgnr_write(u32 v) 28 { 29 write_sysreg(v, RNGNR); 30 } 31 32 /* Data-side / unified region attributes */ 33 34 /* Region access control register */ 35 static inline void dracr_write(u32 v) 36 { 37 write_sysreg(v, DRACR); 38 } 39 40 /* Region size register */ 41 static inline void drsr_write(u32 v) 42 { 43 write_sysreg(v, DRSR); 44 } 45 46 /* Region base address register */ 47 static inline void drbar_write(u32 v) 48 { 49 write_sysreg(v, DRBAR); 50 } 51 52 static inline u32 drbar_read(void) 53 { 54 return read_sysreg(DRBAR); 55 } 56 /* Optional instruction-side region attributes */ 57 58 /* I-side Region access control register */ 59 static inline void iracr_write(u32 v) 60 { 61 write_sysreg(v, IRACR); 62 } 63 64 /* I-side Region size register */ 65 static inline void irsr_write(u32 v) 66 { 67 write_sysreg(v, IRSR); 68 } 69 70 /* I-side Region base address register */ 71 static inline void irbar_write(u32 v) 72 { 73 write_sysreg(v, IRBAR); 74 } 75 76 static inline u32 irbar_read(void) 77 { 78 return read_sysreg(IRBAR); 79 } 80 81 static int __init mpu_present(void) 82 { 83 return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); 84 } 85 86 /* MPU initialisation functions */ 87 void __init adjust_lowmem_bounds_mpu(void) 88 { 89 phys_addr_t phys_offset = PHYS_OFFSET; 90 phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size; 91 struct memblock_region *reg; 92 bool first = true; 93 phys_addr_t mem_start; 94 phys_addr_t mem_end; 95 96 if (!mpu_present()) 97 return; 98 99 for_each_memblock(memory, reg) { 100 if (first) { 101 /* 102 * Initially only use memory continuous from 103 * PHYS_OFFSET */ 104 if (reg->base != phys_offset) 105 panic("First memory bank must be contiguous from PHYS_OFFSET"); 106 107 mem_start = reg->base; 108 mem_end = reg->base + reg->size; 109 specified_mem_size = reg->size; 110 first = false; 111 } else { 112 /* 113 * memblock auto merges contiguous blocks, remove 114 * all blocks afterwards in one go (we can't remove 115 * blocks separately while iterating) 116 */ 117 pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n", 118 &mem_end, ®->base); 119 memblock_remove(reg->base, 0 - reg->base); 120 break; 121 } 122 } 123 124 /* 125 * MPU has curious alignment requirements: Size must be power of 2, and 126 * region start must be aligned to the region size 127 */ 128 if (phys_offset != 0) 129 pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n"); 130 131 /* 132 * Maximum aligned region might overflow phys_addr_t if phys_offset is 133 * 0. Hence we keep everything below 4G until we take the smaller of 134 * the aligned_region_size and rounded_mem_size, one of which is 135 * guaranteed to be smaller than the maximum physical address. 136 */ 137 aligned_region_size = (phys_offset - 1) ^ (phys_offset); 138 /* Find the max power-of-two sized region that fits inside our bank */ 139 rounded_mem_size = (1 << __fls(specified_mem_size)) - 1; 140 141 /* The actual region size is the smaller of the two */ 142 aligned_region_size = aligned_region_size < rounded_mem_size 143 ? aligned_region_size + 1 144 : rounded_mem_size + 1; 145 146 if (aligned_region_size != specified_mem_size) { 147 pr_warn("Truncating memory from %pa to %pa (MPU region constraints)", 148 &specified_mem_size, &aligned_region_size); 149 memblock_remove(mem_start + aligned_region_size, 150 specified_mem_size - aligned_region_size); 151 152 mem_end = mem_start + aligned_region_size; 153 } 154 155 pr_debug("MPU Region from %pa size %pa (end %pa))\n", 156 &phys_offset, &aligned_region_size, &mem_end); 157 158 } 159 160 static int __init __mpu_max_regions(void) 161 { 162 /* 163 * We don't support a different number of I/D side regions so if we 164 * have separate instruction and data memory maps then return 165 * whichever side has a smaller number of supported regions. 166 */ 167 u32 dregions, iregions, mpuir; 168 169 mpuir = read_cpuid(CPUID_MPUIR); 170 171 dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION; 172 173 /* Check for separate d-side and i-side memory maps */ 174 if (mpuir & MPUIR_nU) 175 iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION; 176 177 /* Use the smallest of the two maxima */ 178 return min(dregions, iregions); 179 } 180 181 static int __init mpu_iside_independent(void) 182 { 183 /* MPUIR.nU specifies whether there is *not* a unified memory map */ 184 return read_cpuid(CPUID_MPUIR) & MPUIR_nU; 185 } 186 187 static int __init __mpu_min_region_order(void) 188 { 189 u32 drbar_result, irbar_result; 190 191 /* We've kept a region free for this probing */ 192 rgnr_write(MPU_PROBE_REGION); 193 isb(); 194 /* 195 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum 196 * region order 197 */ 198 drbar_write(0xFFFFFFFC); 199 drbar_result = irbar_result = drbar_read(); 200 drbar_write(0x0); 201 /* If the MPU is non-unified, we use the larger of the two minima*/ 202 if (mpu_iside_independent()) { 203 irbar_write(0xFFFFFFFC); 204 irbar_result = irbar_read(); 205 irbar_write(0x0); 206 } 207 isb(); /* Ensure that MPU region operations have completed */ 208 /* Return whichever result is larger */ 209 210 return __ffs(max(drbar_result, irbar_result)); 211 } 212 213 static int __init mpu_setup_region(unsigned int number, phys_addr_t start, 214 unsigned int size_order, unsigned int properties) 215 { 216 u32 size_data; 217 218 /* We kept a region free for probing resolution of MPU regions*/ 219 if (number > mpu_max_regions 220 || number >= MPU_MAX_REGIONS) 221 return -ENOENT; 222 223 if (size_order > 32) 224 return -ENOMEM; 225 226 if (size_order < mpu_min_region_order) 227 return -ENOMEM; 228 229 /* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */ 230 size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN; 231 232 dsb(); /* Ensure all previous data accesses occur with old mappings */ 233 rgnr_write(number); 234 isb(); 235 drbar_write(start); 236 dracr_write(properties); 237 isb(); /* Propagate properties before enabling region */ 238 drsr_write(size_data); 239 240 /* Check for independent I-side registers */ 241 if (mpu_iside_independent()) { 242 irbar_write(start); 243 iracr_write(properties); 244 isb(); 245 irsr_write(size_data); 246 } 247 isb(); 248 249 /* Store region info (we treat i/d side the same, so only store d) */ 250 mpu_rgn_info.rgns[number].dracr = properties; 251 mpu_rgn_info.rgns[number].drbar = start; 252 mpu_rgn_info.rgns[number].drsr = size_data; 253 254 mpu_rgn_info.used++; 255 256 return 0; 257 } 258 259 /* 260 * Set up default MPU regions, doing nothing if there is no MPU 261 */ 262 void __init mpu_setup(void) 263 { 264 int region = 0, err = 0; 265 266 if (!mpu_present()) 267 return; 268 269 /* Free-up MPU_PROBE_REGION */ 270 mpu_min_region_order = __mpu_min_region_order(); 271 272 /* How many regions are supported */ 273 mpu_max_regions = __mpu_max_regions(); 274 275 /* Now setup MPU (order is important) */ 276 277 /* Background */ 278 err |= mpu_setup_region(region++, 0, 32, 279 MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA); 280 281 /* RAM */ 282 err |= mpu_setup_region(region++, PHYS_OFFSET, 283 ilog2(memblock.memory.regions[0].size), 284 MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); 285 286 /* Vectors */ 287 err |= mpu_setup_region(region++, vectors_base, 288 ilog2(2 * PAGE_SIZE), 289 MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL); 290 if (err) { 291 panic("MPU region initialization failure! %d", err); 292 } else { 293 pr_info("Using ARMv7 PMSA Compliant MPU. " 294 "Region independence: %s, Used %d of %d regions\n", 295 mpu_iside_independent() ? "Yes" : "No", 296 mpu_rgn_info.used, mpu_max_regions); 297 } 298 } 299