1 /* 2 * linux/arch/arm/mm/mmu.c 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/bootmem.h> 15 #include <linux/mman.h> 16 #include <linux/nodemask.h> 17 18 #include <asm/mach-types.h> 19 #include <asm/setup.h> 20 #include <asm/sizes.h> 21 #include <asm/tlb.h> 22 23 #include <asm/mach/arch.h> 24 #include <asm/mach/map.h> 25 26 #include "mm.h" 27 28 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 29 30 extern void _stext, _etext, __data_start, _end; 31 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 32 33 /* 34 * empty_zero_page is a special page that is used for 35 * zero-initialized data and COW. 36 */ 37 struct page *empty_zero_page; 38 EXPORT_SYMBOL(empty_zero_page); 39 40 /* 41 * The pmd table for the upper-most set of pages. 42 */ 43 pmd_t *top_pmd; 44 45 #define CPOLICY_UNCACHED 0 46 #define CPOLICY_BUFFERED 1 47 #define CPOLICY_WRITETHROUGH 2 48 #define CPOLICY_WRITEBACK 3 49 #define CPOLICY_WRITEALLOC 4 50 51 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 52 static unsigned int ecc_mask __initdata = 0; 53 pgprot_t pgprot_user; 54 pgprot_t pgprot_kernel; 55 56 EXPORT_SYMBOL(pgprot_user); 57 EXPORT_SYMBOL(pgprot_kernel); 58 59 struct cachepolicy { 60 const char policy[16]; 61 unsigned int cr_mask; 62 unsigned int pmd; 63 unsigned int pte; 64 }; 65 66 static struct cachepolicy cache_policies[] __initdata = { 67 { 68 .policy = "uncached", 69 .cr_mask = CR_W|CR_C, 70 .pmd = PMD_SECT_UNCACHED, 71 .pte = L_PTE_MT_UNCACHED, 72 }, { 73 .policy = "buffered", 74 .cr_mask = CR_C, 75 .pmd = PMD_SECT_BUFFERED, 76 .pte = L_PTE_MT_BUFFERABLE, 77 }, { 78 .policy = "writethrough", 79 .cr_mask = 0, 80 .pmd = PMD_SECT_WT, 81 .pte = L_PTE_MT_WRITETHROUGH, 82 }, { 83 .policy = "writeback", 84 .cr_mask = 0, 85 .pmd = PMD_SECT_WB, 86 .pte = L_PTE_MT_WRITEBACK, 87 }, { 88 .policy = "writealloc", 89 .cr_mask = 0, 90 .pmd = PMD_SECT_WBWA, 91 .pte = L_PTE_MT_WRITEALLOC, 92 } 93 }; 94 95 /* 96 * These are useful for identifying cache coherency 97 * problems by allowing the cache or the cache and 98 * writebuffer to be turned off. (Note: the write 99 * buffer should not be on and the cache off). 100 */ 101 static void __init early_cachepolicy(char **p) 102 { 103 int i; 104 105 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 106 int len = strlen(cache_policies[i].policy); 107 108 if (memcmp(*p, cache_policies[i].policy, len) == 0) { 109 cachepolicy = i; 110 cr_alignment &= ~cache_policies[i].cr_mask; 111 cr_no_alignment &= ~cache_policies[i].cr_mask; 112 *p += len; 113 break; 114 } 115 } 116 if (i == ARRAY_SIZE(cache_policies)) 117 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 118 if (cpu_architecture() >= CPU_ARCH_ARMv6) { 119 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); 120 cachepolicy = CPOLICY_WRITEBACK; 121 } 122 flush_cache_all(); 123 set_cr(cr_alignment); 124 } 125 __early_param("cachepolicy=", early_cachepolicy); 126 127 static void __init early_nocache(char **__unused) 128 { 129 char *p = "buffered"; 130 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); 131 early_cachepolicy(&p); 132 } 133 __early_param("nocache", early_nocache); 134 135 static void __init early_nowrite(char **__unused) 136 { 137 char *p = "uncached"; 138 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); 139 early_cachepolicy(&p); 140 } 141 __early_param("nowb", early_nowrite); 142 143 static void __init early_ecc(char **p) 144 { 145 if (memcmp(*p, "on", 2) == 0) { 146 ecc_mask = PMD_PROTECTION; 147 *p += 2; 148 } else if (memcmp(*p, "off", 3) == 0) { 149 ecc_mask = 0; 150 *p += 3; 151 } 152 } 153 __early_param("ecc=", early_ecc); 154 155 static int __init noalign_setup(char *__unused) 156 { 157 cr_alignment &= ~CR_A; 158 cr_no_alignment &= ~CR_A; 159 set_cr(cr_alignment); 160 return 1; 161 } 162 __setup("noalign", noalign_setup); 163 164 #ifndef CONFIG_SMP 165 void adjust_cr(unsigned long mask, unsigned long set) 166 { 167 unsigned long flags; 168 169 mask &= ~CR_A; 170 171 set &= mask; 172 173 local_irq_save(flags); 174 175 cr_no_alignment = (cr_no_alignment & ~mask) | set; 176 cr_alignment = (cr_alignment & ~mask) | set; 177 178 set_cr((get_cr() & ~mask) | set); 179 180 local_irq_restore(flags); 181 } 182 #endif 183 184 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE 185 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_XN|PMD_SECT_AP_WRITE 186 187 static struct mem_type mem_types[] = { 188 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 189 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 190 L_PTE_SHARED, 191 .prot_l1 = PMD_TYPE_TABLE, 192 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_UNCACHED, 193 .domain = DOMAIN_IO, 194 }, 195 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 196 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 197 .prot_l1 = PMD_TYPE_TABLE, 198 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_TEX(2), 199 .domain = DOMAIN_IO, 200 }, 201 [MT_DEVICE_CACHED] = { /* ioremap_cached */ 202 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 203 .prot_l1 = PMD_TYPE_TABLE, 204 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 205 .domain = DOMAIN_IO, 206 }, 207 [MT_DEVICE_WC] = { /* ioremap_wc */ 208 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 209 .prot_l1 = PMD_TYPE_TABLE, 210 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_BUFFERABLE, 211 .domain = DOMAIN_IO, 212 }, 213 [MT_CACHECLEAN] = { 214 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 215 .domain = DOMAIN_KERNEL, 216 }, 217 [MT_MINICLEAN] = { 218 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 219 .domain = DOMAIN_KERNEL, 220 }, 221 [MT_LOW_VECTORS] = { 222 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 223 L_PTE_EXEC, 224 .prot_l1 = PMD_TYPE_TABLE, 225 .domain = DOMAIN_USER, 226 }, 227 [MT_HIGH_VECTORS] = { 228 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 229 L_PTE_USER | L_PTE_EXEC, 230 .prot_l1 = PMD_TYPE_TABLE, 231 .domain = DOMAIN_USER, 232 }, 233 [MT_MEMORY] = { 234 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 235 .domain = DOMAIN_KERNEL, 236 }, 237 [MT_ROM] = { 238 .prot_sect = PMD_TYPE_SECT, 239 .domain = DOMAIN_KERNEL, 240 }, 241 }; 242 243 const struct mem_type *get_mem_type(unsigned int type) 244 { 245 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 246 } 247 248 /* 249 * Adjust the PMD section entries according to the CPU in use. 250 */ 251 static void __init build_mem_type_table(void) 252 { 253 struct cachepolicy *cp; 254 unsigned int cr = get_cr(); 255 unsigned int user_pgprot, kern_pgprot, vecs_pgprot; 256 int cpu_arch = cpu_architecture(); 257 int i; 258 259 if (cpu_arch < CPU_ARCH_ARMv6) { 260 #if defined(CONFIG_CPU_DCACHE_DISABLE) 261 if (cachepolicy > CPOLICY_BUFFERED) 262 cachepolicy = CPOLICY_BUFFERED; 263 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 264 if (cachepolicy > CPOLICY_WRITETHROUGH) 265 cachepolicy = CPOLICY_WRITETHROUGH; 266 #endif 267 } 268 if (cpu_arch < CPU_ARCH_ARMv5) { 269 if (cachepolicy >= CPOLICY_WRITEALLOC) 270 cachepolicy = CPOLICY_WRITEBACK; 271 ecc_mask = 0; 272 } 273 #ifdef CONFIG_SMP 274 cachepolicy = CPOLICY_WRITEALLOC; 275 #endif 276 277 /* 278 * On non-Xscale3 ARMv5-and-older systems, use CB=01 279 * (Uncached/Buffered) for ioremap_wc() mappings. On XScale3 280 * and ARMv6+, use TEXCB=00100 mappings (Inner/Outer Uncacheable 281 * in xsc3 parlance, Uncached Normal in ARMv6 parlance). 282 */ 283 if (cpu_is_xsc3() || cpu_arch >= CPU_ARCH_ARMv6) { 284 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 285 mem_types[MT_DEVICE_WC].prot_sect &= ~PMD_SECT_BUFFERABLE; 286 } 287 288 /* 289 * ARMv5 and lower, bit 4 must be set for page tables. 290 * (was: cache "update-able on write" bit on ARM610) 291 * However, Xscale cores require this bit to be cleared. 292 */ 293 if (cpu_is_xscale()) { 294 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 295 mem_types[i].prot_sect &= ~PMD_BIT4; 296 mem_types[i].prot_l1 &= ~PMD_BIT4; 297 } 298 } else if (cpu_arch < CPU_ARCH_ARMv6) { 299 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 300 if (mem_types[i].prot_l1) 301 mem_types[i].prot_l1 |= PMD_BIT4; 302 if (mem_types[i].prot_sect) 303 mem_types[i].prot_sect |= PMD_BIT4; 304 } 305 } 306 307 cp = &cache_policies[cachepolicy]; 308 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 309 310 #ifndef CONFIG_SMP 311 /* 312 * Only use write-through for non-SMP systems 313 */ 314 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) 315 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; 316 #endif 317 318 /* 319 * Enable CPU-specific coherency if supported. 320 * (Only available on XSC3 at the moment.) 321 */ 322 if (arch_is_coherent()) { 323 if (cpu_is_xsc3()) { 324 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 325 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 326 } 327 } 328 329 /* 330 * ARMv6 and above have extended page tables. 331 */ 332 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 333 /* 334 * Mark cache clean areas and XIP ROM read only 335 * from SVC mode and no access from userspace. 336 */ 337 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 338 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 339 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 340 341 /* 342 * Mark the device area as "shared device" 343 */ 344 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 345 346 #ifdef CONFIG_SMP 347 /* 348 * Mark memory with the "shared" attribute for SMP systems 349 */ 350 user_pgprot |= L_PTE_SHARED; 351 kern_pgprot |= L_PTE_SHARED; 352 vecs_pgprot |= L_PTE_SHARED; 353 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 354 #endif 355 } 356 357 for (i = 0; i < 16; i++) { 358 unsigned long v = pgprot_val(protection_map[i]); 359 protection_map[i] = __pgprot(v | user_pgprot); 360 } 361 362 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 363 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 364 365 if (cpu_arch < CPU_ARCH_ARMv5) 366 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1); 367 368 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 369 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 370 L_PTE_DIRTY | L_PTE_WRITE | 371 L_PTE_EXEC | kern_pgprot); 372 373 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 374 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 375 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 376 mem_types[MT_ROM].prot_sect |= cp->pmd; 377 378 switch (cp->pmd) { 379 case PMD_SECT_WT: 380 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 381 break; 382 case PMD_SECT_WB: 383 case PMD_SECT_WBWA: 384 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 385 break; 386 } 387 printk("Memory policy: ECC %sabled, Data cache %s\n", 388 ecc_mask ? "en" : "dis", cp->policy); 389 390 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 391 struct mem_type *t = &mem_types[i]; 392 if (t->prot_l1) 393 t->prot_l1 |= PMD_DOMAIN(t->domain); 394 if (t->prot_sect) 395 t->prot_sect |= PMD_DOMAIN(t->domain); 396 } 397 } 398 399 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 400 401 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 402 unsigned long end, unsigned long pfn, 403 const struct mem_type *type) 404 { 405 pte_t *pte; 406 407 if (pmd_none(*pmd)) { 408 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); 409 __pmd_populate(pmd, __pa(pte) | type->prot_l1); 410 } 411 412 pte = pte_offset_kernel(pmd, addr); 413 do { 414 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); 415 pfn++; 416 } while (pte++, addr += PAGE_SIZE, addr != end); 417 } 418 419 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, 420 unsigned long end, unsigned long phys, 421 const struct mem_type *type) 422 { 423 pmd_t *pmd = pmd_offset(pgd, addr); 424 425 /* 426 * Try a section mapping - end, addr and phys must all be aligned 427 * to a section boundary. Note that PMDs refer to the individual 428 * L1 entries, whereas PGDs refer to a group of L1 entries making 429 * up one logical pointer to an L2 table. 430 */ 431 if (((addr | end | phys) & ~SECTION_MASK) == 0) { 432 pmd_t *p = pmd; 433 434 if (addr & SECTION_SIZE) 435 pmd++; 436 437 do { 438 *pmd = __pmd(phys | type->prot_sect); 439 phys += SECTION_SIZE; 440 } while (pmd++, addr += SECTION_SIZE, addr != end); 441 442 flush_pmd_entry(p); 443 } else { 444 /* 445 * No need to loop; pte's aren't interested in the 446 * individual L1 entries. 447 */ 448 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); 449 } 450 } 451 452 static void __init create_36bit_mapping(struct map_desc *md, 453 const struct mem_type *type) 454 { 455 unsigned long phys, addr, length, end; 456 pgd_t *pgd; 457 458 addr = md->virtual; 459 phys = (unsigned long)__pfn_to_phys(md->pfn); 460 length = PAGE_ALIGN(md->length); 461 462 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 463 printk(KERN_ERR "MM: CPU does not support supersection " 464 "mapping for 0x%08llx at 0x%08lx\n", 465 __pfn_to_phys((u64)md->pfn), addr); 466 return; 467 } 468 469 /* N.B. ARMv6 supersections are only defined to work with domain 0. 470 * Since domain assignments can in fact be arbitrary, the 471 * 'domain == 0' check below is required to insure that ARMv6 472 * supersections are only allocated for domain 0 regardless 473 * of the actual domain assignments in use. 474 */ 475 if (type->domain) { 476 printk(KERN_ERR "MM: invalid domain in supersection " 477 "mapping for 0x%08llx at 0x%08lx\n", 478 __pfn_to_phys((u64)md->pfn), addr); 479 return; 480 } 481 482 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 483 printk(KERN_ERR "MM: cannot create mapping for " 484 "0x%08llx at 0x%08lx invalid alignment\n", 485 __pfn_to_phys((u64)md->pfn), addr); 486 return; 487 } 488 489 /* 490 * Shift bits [35:32] of address into bits [23:20] of PMD 491 * (See ARMv6 spec). 492 */ 493 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 494 495 pgd = pgd_offset_k(addr); 496 end = addr + length; 497 do { 498 pmd_t *pmd = pmd_offset(pgd, addr); 499 int i; 500 501 for (i = 0; i < 16; i++) 502 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); 503 504 addr += SUPERSECTION_SIZE; 505 phys += SUPERSECTION_SIZE; 506 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 507 } while (addr != end); 508 } 509 510 /* 511 * Create the page directory entries and any necessary 512 * page tables for the mapping specified by `md'. We 513 * are able to cope here with varying sizes and address 514 * offsets, and we take full advantage of sections and 515 * supersections. 516 */ 517 void __init create_mapping(struct map_desc *md) 518 { 519 unsigned long phys, addr, length, end; 520 const struct mem_type *type; 521 pgd_t *pgd; 522 523 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 524 printk(KERN_WARNING "BUG: not creating mapping for " 525 "0x%08llx at 0x%08lx in user region\n", 526 __pfn_to_phys((u64)md->pfn), md->virtual); 527 return; 528 } 529 530 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 531 md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { 532 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " 533 "overlaps vmalloc space\n", 534 __pfn_to_phys((u64)md->pfn), md->virtual); 535 } 536 537 type = &mem_types[md->type]; 538 539 /* 540 * Catch 36-bit addresses 541 */ 542 if (md->pfn >= 0x100000) { 543 create_36bit_mapping(md, type); 544 return; 545 } 546 547 addr = md->virtual & PAGE_MASK; 548 phys = (unsigned long)__pfn_to_phys(md->pfn); 549 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 550 551 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 552 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " 553 "be mapped using pages, ignoring.\n", 554 __pfn_to_phys(md->pfn), addr); 555 return; 556 } 557 558 pgd = pgd_offset_k(addr); 559 end = addr + length; 560 do { 561 unsigned long next = pgd_addr_end(addr, end); 562 563 alloc_init_section(pgd, addr, next, phys, type); 564 565 phys += next - addr; 566 addr = next; 567 } while (pgd++, addr != end); 568 } 569 570 /* 571 * Create the architecture specific mappings 572 */ 573 void __init iotable_init(struct map_desc *io_desc, int nr) 574 { 575 int i; 576 577 for (i = 0; i < nr; i++) 578 create_mapping(io_desc + i); 579 } 580 581 static int __init check_membank_valid(struct membank *mb) 582 { 583 /* 584 * Check whether this memory region has non-zero size. 585 */ 586 if (mb->size == 0) 587 return 0; 588 589 /* 590 * Check whether this memory region would entirely overlap 591 * the vmalloc area. 592 */ 593 if (phys_to_virt(mb->start) >= VMALLOC_MIN) { 594 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " 595 "(vmalloc region overlap).\n", 596 mb->start, mb->start + mb->size - 1); 597 return 0; 598 } 599 600 /* 601 * Check whether this memory region would partially overlap 602 * the vmalloc area. 603 */ 604 if (phys_to_virt(mb->start + mb->size) < phys_to_virt(mb->start) || 605 phys_to_virt(mb->start + mb->size) > VMALLOC_MIN) { 606 unsigned long newsize = VMALLOC_MIN - phys_to_virt(mb->start); 607 608 printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " 609 "to -%.8lx (vmalloc region overlap).\n", 610 mb->start, mb->start + mb->size - 1, 611 mb->start + newsize - 1); 612 mb->size = newsize; 613 } 614 615 return 1; 616 } 617 618 static void __init sanity_check_meminfo(struct meminfo *mi) 619 { 620 int i; 621 int j; 622 623 for (i = 0, j = 0; i < mi->nr_banks; i++) { 624 if (check_membank_valid(&mi->bank[i])) 625 mi->bank[j++] = mi->bank[i]; 626 } 627 mi->nr_banks = j; 628 } 629 630 static inline void prepare_page_table(struct meminfo *mi) 631 { 632 unsigned long addr; 633 634 /* 635 * Clear out all the mappings below the kernel image. 636 */ 637 for (addr = 0; addr < MODULE_START; addr += PGDIR_SIZE) 638 pmd_clear(pmd_off_k(addr)); 639 640 #ifdef CONFIG_XIP_KERNEL 641 /* The XIP kernel is mapped in the module area -- skip over it */ 642 addr = ((unsigned long)&_etext + PGDIR_SIZE - 1) & PGDIR_MASK; 643 #endif 644 for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) 645 pmd_clear(pmd_off_k(addr)); 646 647 /* 648 * Clear out all the kernel space mappings, except for the first 649 * memory bank, up to the end of the vmalloc region. 650 */ 651 for (addr = __phys_to_virt(mi->bank[0].start + mi->bank[0].size); 652 addr < VMALLOC_END; addr += PGDIR_SIZE) 653 pmd_clear(pmd_off_k(addr)); 654 } 655 656 /* 657 * Reserve the various regions of node 0 658 */ 659 void __init reserve_node_zero(pg_data_t *pgdat) 660 { 661 unsigned long res_size = 0; 662 663 /* 664 * Register the kernel text and data with bootmem. 665 * Note that this can only be in node 0. 666 */ 667 #ifdef CONFIG_XIP_KERNEL 668 reserve_bootmem_node(pgdat, __pa(&__data_start), &_end - &__data_start, 669 BOOTMEM_DEFAULT); 670 #else 671 reserve_bootmem_node(pgdat, __pa(&_stext), &_end - &_stext, 672 BOOTMEM_DEFAULT); 673 #endif 674 675 /* 676 * Reserve the page tables. These are already in use, 677 * and can only be in node 0. 678 */ 679 reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), 680 PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT); 681 682 /* 683 * Hmm... This should go elsewhere, but we really really need to 684 * stop things allocating the low memory; ideally we need a better 685 * implementation of GFP_DMA which does not assume that DMA-able 686 * memory starts at zero. 687 */ 688 if (machine_is_integrator() || machine_is_cintegrator()) 689 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; 690 691 /* 692 * These should likewise go elsewhere. They pre-reserve the 693 * screen memory region at the start of main system memory. 694 */ 695 if (machine_is_edb7211()) 696 res_size = 0x00020000; 697 if (machine_is_p720t()) 698 res_size = 0x00014000; 699 700 /* H1940 and RX3715 need to reserve this for suspend */ 701 702 if (machine_is_h1940() || machine_is_rx3715()) { 703 reserve_bootmem_node(pgdat, 0x30003000, 0x1000, 704 BOOTMEM_DEFAULT); 705 reserve_bootmem_node(pgdat, 0x30081000, 0x1000, 706 BOOTMEM_DEFAULT); 707 } 708 709 #ifdef CONFIG_SA1111 710 /* 711 * Because of the SA1111 DMA bug, we want to preserve our 712 * precious DMA-able memory... 713 */ 714 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; 715 #endif 716 if (res_size) 717 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size, 718 BOOTMEM_DEFAULT); 719 } 720 721 /* 722 * Set up device the mappings. Since we clear out the page tables for all 723 * mappings above VMALLOC_END, we will remove any debug device mappings. 724 * This means you have to be careful how you debug this function, or any 725 * called function. This means you can't use any function or debugging 726 * method which may touch any device, otherwise the kernel _will_ crash. 727 */ 728 static void __init devicemaps_init(struct machine_desc *mdesc) 729 { 730 struct map_desc map; 731 unsigned long addr; 732 void *vectors; 733 734 /* 735 * Allocate the vector page early. 736 */ 737 vectors = alloc_bootmem_low_pages(PAGE_SIZE); 738 BUG_ON(!vectors); 739 740 for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) 741 pmd_clear(pmd_off_k(addr)); 742 743 /* 744 * Map the kernel if it is XIP. 745 * It is always first in the modulearea. 746 */ 747 #ifdef CONFIG_XIP_KERNEL 748 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 749 map.virtual = MODULE_START; 750 map.length = ((unsigned long)&_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; 751 map.type = MT_ROM; 752 create_mapping(&map); 753 #endif 754 755 /* 756 * Map the cache flushing regions. 757 */ 758 #ifdef FLUSH_BASE 759 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 760 map.virtual = FLUSH_BASE; 761 map.length = SZ_1M; 762 map.type = MT_CACHECLEAN; 763 create_mapping(&map); 764 #endif 765 #ifdef FLUSH_BASE_MINICACHE 766 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 767 map.virtual = FLUSH_BASE_MINICACHE; 768 map.length = SZ_1M; 769 map.type = MT_MINICLEAN; 770 create_mapping(&map); 771 #endif 772 773 /* 774 * Create a mapping for the machine vectors at the high-vectors 775 * location (0xffff0000). If we aren't using high-vectors, also 776 * create a mapping at the low-vectors virtual address. 777 */ 778 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 779 map.virtual = 0xffff0000; 780 map.length = PAGE_SIZE; 781 map.type = MT_HIGH_VECTORS; 782 create_mapping(&map); 783 784 if (!vectors_high()) { 785 map.virtual = 0; 786 map.type = MT_LOW_VECTORS; 787 create_mapping(&map); 788 } 789 790 /* 791 * Ask the machine support to map in the statically mapped devices. 792 */ 793 if (mdesc->map_io) 794 mdesc->map_io(); 795 796 /* 797 * Finally flush the caches and tlb to ensure that we're in a 798 * consistent state wrt the writebuffer. This also ensures that 799 * any write-allocated cache lines in the vector page are written 800 * back. After this point, we can start to touch devices again. 801 */ 802 local_flush_tlb_all(); 803 flush_cache_all(); 804 } 805 806 /* 807 * paging_init() sets up the page tables, initialises the zone memory 808 * maps, and sets up the zero page, bad page and bad page tables. 809 */ 810 void __init paging_init(struct meminfo *mi, struct machine_desc *mdesc) 811 { 812 void *zero_page; 813 814 build_mem_type_table(); 815 sanity_check_meminfo(mi); 816 prepare_page_table(mi); 817 bootmem_init(mi); 818 devicemaps_init(mdesc); 819 820 top_pmd = pmd_off_k(0xffff0000); 821 822 /* 823 * allocate the zero page. Note that we count on this going ok. 824 */ 825 zero_page = alloc_bootmem_low_pages(PAGE_SIZE); 826 memzero(zero_page, PAGE_SIZE); 827 empty_zero_page = virt_to_page(zero_page); 828 flush_dcache_page(empty_zero_page); 829 } 830 831 /* 832 * In order to soft-boot, we need to insert a 1:1 mapping in place of 833 * the user-mode pages. This will then ensure that we have predictable 834 * results when turning the mmu off 835 */ 836 void setup_mm_for_reboot(char mode) 837 { 838 unsigned long base_pmdval; 839 pgd_t *pgd; 840 int i; 841 842 if (current->mm && current->mm->pgd) 843 pgd = current->mm->pgd; 844 else 845 pgd = init_mm.pgd; 846 847 base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; 848 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) 849 base_pmdval |= PMD_BIT4; 850 851 for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { 852 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; 853 pmd_t *pmd; 854 855 pmd = pmd_off(pgd, i << PGDIR_SHIFT); 856 pmd[0] = __pmd(pmdval); 857 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); 858 flush_pmd_entry(pmd); 859 } 860 } 861