1 /* 2 * linux/arch/arm/mm/mmu.c 3 * 4 * Copyright (C) 1995-2005 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/errno.h> 13 #include <linux/init.h> 14 #include <linux/mman.h> 15 #include <linux/nodemask.h> 16 #include <linux/memblock.h> 17 #include <linux/fs.h> 18 #include <linux/vmalloc.h> 19 20 #include <asm/cp15.h> 21 #include <asm/cputype.h> 22 #include <asm/sections.h> 23 #include <asm/cachetype.h> 24 #include <asm/setup.h> 25 #include <asm/sizes.h> 26 #include <asm/smp_plat.h> 27 #include <asm/tlb.h> 28 #include <asm/highmem.h> 29 #include <asm/system_info.h> 30 #include <asm/traps.h> 31 32 #include <asm/mach/arch.h> 33 #include <asm/mach/map.h> 34 35 #include "mm.h" 36 37 /* 38 * empty_zero_page is a special page that is used for 39 * zero-initialized data and COW. 40 */ 41 struct page *empty_zero_page; 42 EXPORT_SYMBOL(empty_zero_page); 43 44 /* 45 * The pmd table for the upper-most set of pages. 46 */ 47 pmd_t *top_pmd; 48 49 #define CPOLICY_UNCACHED 0 50 #define CPOLICY_BUFFERED 1 51 #define CPOLICY_WRITETHROUGH 2 52 #define CPOLICY_WRITEBACK 3 53 #define CPOLICY_WRITEALLOC 4 54 55 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; 56 static unsigned int ecc_mask __initdata = 0; 57 pgprot_t pgprot_user; 58 pgprot_t pgprot_kernel; 59 60 EXPORT_SYMBOL(pgprot_user); 61 EXPORT_SYMBOL(pgprot_kernel); 62 63 struct cachepolicy { 64 const char policy[16]; 65 unsigned int cr_mask; 66 pmdval_t pmd; 67 pteval_t pte; 68 }; 69 70 static struct cachepolicy cache_policies[] __initdata = { 71 { 72 .policy = "uncached", 73 .cr_mask = CR_W|CR_C, 74 .pmd = PMD_SECT_UNCACHED, 75 .pte = L_PTE_MT_UNCACHED, 76 }, { 77 .policy = "buffered", 78 .cr_mask = CR_C, 79 .pmd = PMD_SECT_BUFFERED, 80 .pte = L_PTE_MT_BUFFERABLE, 81 }, { 82 .policy = "writethrough", 83 .cr_mask = 0, 84 .pmd = PMD_SECT_WT, 85 .pte = L_PTE_MT_WRITETHROUGH, 86 }, { 87 .policy = "writeback", 88 .cr_mask = 0, 89 .pmd = PMD_SECT_WB, 90 .pte = L_PTE_MT_WRITEBACK, 91 }, { 92 .policy = "writealloc", 93 .cr_mask = 0, 94 .pmd = PMD_SECT_WBWA, 95 .pte = L_PTE_MT_WRITEALLOC, 96 } 97 }; 98 99 /* 100 * These are useful for identifying cache coherency 101 * problems by allowing the cache or the cache and 102 * writebuffer to be turned off. (Note: the write 103 * buffer should not be on and the cache off). 104 */ 105 static int __init early_cachepolicy(char *p) 106 { 107 int i; 108 109 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { 110 int len = strlen(cache_policies[i].policy); 111 112 if (memcmp(p, cache_policies[i].policy, len) == 0) { 113 cachepolicy = i; 114 cr_alignment &= ~cache_policies[i].cr_mask; 115 cr_no_alignment &= ~cache_policies[i].cr_mask; 116 break; 117 } 118 } 119 if (i == ARRAY_SIZE(cache_policies)) 120 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); 121 /* 122 * This restriction is partly to do with the way we boot; it is 123 * unpredictable to have memory mapped using two different sets of 124 * memory attributes (shared, type, and cache attribs). We can not 125 * change these attributes once the initial assembly has setup the 126 * page tables. 127 */ 128 if (cpu_architecture() >= CPU_ARCH_ARMv6) { 129 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); 130 cachepolicy = CPOLICY_WRITEBACK; 131 } 132 flush_cache_all(); 133 set_cr(cr_alignment); 134 return 0; 135 } 136 early_param("cachepolicy", early_cachepolicy); 137 138 static int __init early_nocache(char *__unused) 139 { 140 char *p = "buffered"; 141 printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); 142 early_cachepolicy(p); 143 return 0; 144 } 145 early_param("nocache", early_nocache); 146 147 static int __init early_nowrite(char *__unused) 148 { 149 char *p = "uncached"; 150 printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); 151 early_cachepolicy(p); 152 return 0; 153 } 154 early_param("nowb", early_nowrite); 155 156 #ifndef CONFIG_ARM_LPAE 157 static int __init early_ecc(char *p) 158 { 159 if (memcmp(p, "on", 2) == 0) 160 ecc_mask = PMD_PROTECTION; 161 else if (memcmp(p, "off", 3) == 0) 162 ecc_mask = 0; 163 return 0; 164 } 165 early_param("ecc", early_ecc); 166 #endif 167 168 static int __init noalign_setup(char *__unused) 169 { 170 cr_alignment &= ~CR_A; 171 cr_no_alignment &= ~CR_A; 172 set_cr(cr_alignment); 173 return 1; 174 } 175 __setup("noalign", noalign_setup); 176 177 #ifndef CONFIG_SMP 178 void adjust_cr(unsigned long mask, unsigned long set) 179 { 180 unsigned long flags; 181 182 mask &= ~CR_A; 183 184 set &= mask; 185 186 local_irq_save(flags); 187 188 cr_no_alignment = (cr_no_alignment & ~mask) | set; 189 cr_alignment = (cr_alignment & ~mask) | set; 190 191 set_cr((get_cr() & ~mask) | set); 192 193 local_irq_restore(flags); 194 } 195 #endif 196 197 #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN 198 #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE 199 200 static struct mem_type mem_types[] = { 201 [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ 202 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | 203 L_PTE_SHARED, 204 .prot_l1 = PMD_TYPE_TABLE, 205 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, 206 .domain = DOMAIN_IO, 207 }, 208 [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ 209 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, 210 .prot_l1 = PMD_TYPE_TABLE, 211 .prot_sect = PROT_SECT_DEVICE, 212 .domain = DOMAIN_IO, 213 }, 214 [MT_DEVICE_CACHED] = { /* ioremap_cached */ 215 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, 216 .prot_l1 = PMD_TYPE_TABLE, 217 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, 218 .domain = DOMAIN_IO, 219 }, 220 [MT_DEVICE_WC] = { /* ioremap_wc */ 221 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, 222 .prot_l1 = PMD_TYPE_TABLE, 223 .prot_sect = PROT_SECT_DEVICE, 224 .domain = DOMAIN_IO, 225 }, 226 [MT_UNCACHED] = { 227 .prot_pte = PROT_PTE_DEVICE, 228 .prot_l1 = PMD_TYPE_TABLE, 229 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 230 .domain = DOMAIN_IO, 231 }, 232 [MT_CACHECLEAN] = { 233 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 234 .domain = DOMAIN_KERNEL, 235 }, 236 #ifndef CONFIG_ARM_LPAE 237 [MT_MINICLEAN] = { 238 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, 239 .domain = DOMAIN_KERNEL, 240 }, 241 #endif 242 [MT_LOW_VECTORS] = { 243 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 244 L_PTE_RDONLY, 245 .prot_l1 = PMD_TYPE_TABLE, 246 .domain = DOMAIN_USER, 247 }, 248 [MT_HIGH_VECTORS] = { 249 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 250 L_PTE_USER | L_PTE_RDONLY, 251 .prot_l1 = PMD_TYPE_TABLE, 252 .domain = DOMAIN_USER, 253 }, 254 [MT_MEMORY] = { 255 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 256 .prot_l1 = PMD_TYPE_TABLE, 257 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 258 .domain = DOMAIN_KERNEL, 259 }, 260 [MT_ROM] = { 261 .prot_sect = PMD_TYPE_SECT, 262 .domain = DOMAIN_KERNEL, 263 }, 264 [MT_MEMORY_NONCACHED] = { 265 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 266 L_PTE_MT_BUFFERABLE, 267 .prot_l1 = PMD_TYPE_TABLE, 268 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, 269 .domain = DOMAIN_KERNEL, 270 }, 271 [MT_MEMORY_DTCM] = { 272 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 273 L_PTE_XN, 274 .prot_l1 = PMD_TYPE_TABLE, 275 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, 276 .domain = DOMAIN_KERNEL, 277 }, 278 [MT_MEMORY_ITCM] = { 279 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, 280 .prot_l1 = PMD_TYPE_TABLE, 281 .domain = DOMAIN_KERNEL, 282 }, 283 [MT_MEMORY_SO] = { 284 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | 285 L_PTE_MT_UNCACHED, 286 .prot_l1 = PMD_TYPE_TABLE, 287 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | 288 PMD_SECT_UNCACHED | PMD_SECT_XN, 289 .domain = DOMAIN_KERNEL, 290 }, 291 }; 292 293 const struct mem_type *get_mem_type(unsigned int type) 294 { 295 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; 296 } 297 EXPORT_SYMBOL(get_mem_type); 298 299 /* 300 * Adjust the PMD section entries according to the CPU in use. 301 */ 302 static void __init build_mem_type_table(void) 303 { 304 struct cachepolicy *cp; 305 unsigned int cr = get_cr(); 306 pteval_t user_pgprot, kern_pgprot, vecs_pgprot; 307 int cpu_arch = cpu_architecture(); 308 int i; 309 310 if (cpu_arch < CPU_ARCH_ARMv6) { 311 #if defined(CONFIG_CPU_DCACHE_DISABLE) 312 if (cachepolicy > CPOLICY_BUFFERED) 313 cachepolicy = CPOLICY_BUFFERED; 314 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) 315 if (cachepolicy > CPOLICY_WRITETHROUGH) 316 cachepolicy = CPOLICY_WRITETHROUGH; 317 #endif 318 } 319 if (cpu_arch < CPU_ARCH_ARMv5) { 320 if (cachepolicy >= CPOLICY_WRITEALLOC) 321 cachepolicy = CPOLICY_WRITEBACK; 322 ecc_mask = 0; 323 } 324 if (is_smp()) 325 cachepolicy = CPOLICY_WRITEALLOC; 326 327 /* 328 * Strip out features not present on earlier architectures. 329 * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those 330 * without extended page tables don't have the 'Shared' bit. 331 */ 332 if (cpu_arch < CPU_ARCH_ARMv5) 333 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 334 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); 335 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) 336 for (i = 0; i < ARRAY_SIZE(mem_types); i++) 337 mem_types[i].prot_sect &= ~PMD_SECT_S; 338 339 /* 340 * ARMv5 and lower, bit 4 must be set for page tables (was: cache 341 * "update-able on write" bit on ARM610). However, Xscale and 342 * Xscale3 require this bit to be cleared. 343 */ 344 if (cpu_is_xscale() || cpu_is_xsc3()) { 345 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 346 mem_types[i].prot_sect &= ~PMD_BIT4; 347 mem_types[i].prot_l1 &= ~PMD_BIT4; 348 } 349 } else if (cpu_arch < CPU_ARCH_ARMv6) { 350 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 351 if (mem_types[i].prot_l1) 352 mem_types[i].prot_l1 |= PMD_BIT4; 353 if (mem_types[i].prot_sect) 354 mem_types[i].prot_sect |= PMD_BIT4; 355 } 356 } 357 358 /* 359 * Mark the device areas according to the CPU/architecture. 360 */ 361 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { 362 if (!cpu_is_xsc3()) { 363 /* 364 * Mark device regions on ARMv6+ as execute-never 365 * to prevent speculative instruction fetches. 366 */ 367 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; 368 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; 369 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; 370 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; 371 } 372 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 373 /* 374 * For ARMv7 with TEX remapping, 375 * - shared device is SXCB=1100 376 * - nonshared device is SXCB=0100 377 * - write combine device mem is SXCB=0001 378 * (Uncached Normal memory) 379 */ 380 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); 381 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); 382 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 383 } else if (cpu_is_xsc3()) { 384 /* 385 * For Xscale3, 386 * - shared device is TEXCB=00101 387 * - nonshared device is TEXCB=01000 388 * - write combine device mem is TEXCB=00100 389 * (Inner/Outer Uncacheable in xsc3 parlance) 390 */ 391 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; 392 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 393 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 394 } else { 395 /* 396 * For ARMv6 and ARMv7 without TEX remapping, 397 * - shared device is TEXCB=00001 398 * - nonshared device is TEXCB=01000 399 * - write combine device mem is TEXCB=00100 400 * (Uncached Normal in ARMv6 parlance). 401 */ 402 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; 403 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); 404 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); 405 } 406 } else { 407 /* 408 * On others, write combining is "Uncached/Buffered" 409 */ 410 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; 411 } 412 413 /* 414 * Now deal with the memory-type mappings 415 */ 416 cp = &cache_policies[cachepolicy]; 417 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 418 419 /* 420 * Only use write-through for non-SMP systems 421 */ 422 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) 423 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; 424 425 /* 426 * Enable CPU-specific coherency if supported. 427 * (Only available on XSC3 at the moment.) 428 */ 429 if (arch_is_coherent() && cpu_is_xsc3()) { 430 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 431 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 432 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 433 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; 434 } 435 /* 436 * ARMv6 and above have extended page tables. 437 */ 438 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { 439 #ifndef CONFIG_ARM_LPAE 440 /* 441 * Mark cache clean areas and XIP ROM read only 442 * from SVC mode and no access from userspace. 443 */ 444 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 445 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 446 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 447 #endif 448 449 if (is_smp()) { 450 /* 451 * Mark memory with the "shared" attribute 452 * for SMP systems 453 */ 454 user_pgprot |= L_PTE_SHARED; 455 kern_pgprot |= L_PTE_SHARED; 456 vecs_pgprot |= L_PTE_SHARED; 457 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 458 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 459 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 460 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 461 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 462 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 463 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 464 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; 465 } 466 } 467 468 /* 469 * Non-cacheable Normal - intended for memory areas that must 470 * not cause dirty cache line writebacks when used 471 */ 472 if (cpu_arch >= CPU_ARCH_ARMv6) { 473 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { 474 /* Non-cacheable Normal is XCB = 001 */ 475 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 476 PMD_SECT_BUFFERED; 477 } else { 478 /* For both ARMv6 and non-TEX-remapping ARMv7 */ 479 mem_types[MT_MEMORY_NONCACHED].prot_sect |= 480 PMD_SECT_TEX(1); 481 } 482 } else { 483 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; 484 } 485 486 #ifdef CONFIG_ARM_LPAE 487 /* 488 * Do not generate access flag faults for the kernel mappings. 489 */ 490 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 491 mem_types[i].prot_pte |= PTE_EXT_AF; 492 mem_types[i].prot_sect |= PMD_SECT_AF; 493 } 494 kern_pgprot |= PTE_EXT_AF; 495 vecs_pgprot |= PTE_EXT_AF; 496 #endif 497 498 for (i = 0; i < 16; i++) { 499 unsigned long v = pgprot_val(protection_map[i]); 500 protection_map[i] = __pgprot(v | user_pgprot); 501 } 502 503 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; 504 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; 505 506 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); 507 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | 508 L_PTE_DIRTY | kern_pgprot); 509 510 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; 511 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; 512 mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; 513 mem_types[MT_MEMORY].prot_pte |= kern_pgprot; 514 mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; 515 mem_types[MT_ROM].prot_sect |= cp->pmd; 516 517 switch (cp->pmd) { 518 case PMD_SECT_WT: 519 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; 520 break; 521 case PMD_SECT_WB: 522 case PMD_SECT_WBWA: 523 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; 524 break; 525 } 526 printk("Memory policy: ECC %sabled, Data cache %s\n", 527 ecc_mask ? "en" : "dis", cp->policy); 528 529 for (i = 0; i < ARRAY_SIZE(mem_types); i++) { 530 struct mem_type *t = &mem_types[i]; 531 if (t->prot_l1) 532 t->prot_l1 |= PMD_DOMAIN(t->domain); 533 if (t->prot_sect) 534 t->prot_sect |= PMD_DOMAIN(t->domain); 535 } 536 } 537 538 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 539 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 540 unsigned long size, pgprot_t vma_prot) 541 { 542 if (!pfn_valid(pfn)) 543 return pgprot_noncached(vma_prot); 544 else if (file->f_flags & O_SYNC) 545 return pgprot_writecombine(vma_prot); 546 return vma_prot; 547 } 548 EXPORT_SYMBOL(phys_mem_access_prot); 549 #endif 550 551 #define vectors_base() (vectors_high() ? 0xffff0000 : 0) 552 553 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) 554 { 555 void *ptr = __va(memblock_alloc(sz, align)); 556 memset(ptr, 0, sz); 557 return ptr; 558 } 559 560 static void __init *early_alloc(unsigned long sz) 561 { 562 return early_alloc_aligned(sz, sz); 563 } 564 565 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) 566 { 567 if (pmd_none(*pmd)) { 568 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); 569 __pmd_populate(pmd, __pa(pte), prot); 570 } 571 BUG_ON(pmd_bad(*pmd)); 572 return pte_offset_kernel(pmd, addr); 573 } 574 575 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, 576 unsigned long end, unsigned long pfn, 577 const struct mem_type *type) 578 { 579 pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); 580 do { 581 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); 582 pfn++; 583 } while (pte++, addr += PAGE_SIZE, addr != end); 584 } 585 586 static void __init alloc_init_section(pud_t *pud, unsigned long addr, 587 unsigned long end, phys_addr_t phys, 588 const struct mem_type *type) 589 { 590 pmd_t *pmd = pmd_offset(pud, addr); 591 592 /* 593 * Try a section mapping - end, addr and phys must all be aligned 594 * to a section boundary. Note that PMDs refer to the individual 595 * L1 entries, whereas PGDs refer to a group of L1 entries making 596 * up one logical pointer to an L2 table. 597 */ 598 if (((addr | end | phys) & ~SECTION_MASK) == 0) { 599 pmd_t *p = pmd; 600 601 #ifndef CONFIG_ARM_LPAE 602 if (addr & SECTION_SIZE) 603 pmd++; 604 #endif 605 606 do { 607 *pmd = __pmd(phys | type->prot_sect); 608 phys += SECTION_SIZE; 609 } while (pmd++, addr += SECTION_SIZE, addr != end); 610 611 flush_pmd_entry(p); 612 } else { 613 /* 614 * No need to loop; pte's aren't interested in the 615 * individual L1 entries. 616 */ 617 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); 618 } 619 } 620 621 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, 622 unsigned long end, unsigned long phys, const struct mem_type *type) 623 { 624 pud_t *pud = pud_offset(pgd, addr); 625 unsigned long next; 626 627 do { 628 next = pud_addr_end(addr, end); 629 alloc_init_section(pud, addr, next, phys, type); 630 phys += next - addr; 631 } while (pud++, addr = next, addr != end); 632 } 633 634 #ifndef CONFIG_ARM_LPAE 635 static void __init create_36bit_mapping(struct map_desc *md, 636 const struct mem_type *type) 637 { 638 unsigned long addr, length, end; 639 phys_addr_t phys; 640 pgd_t *pgd; 641 642 addr = md->virtual; 643 phys = __pfn_to_phys(md->pfn); 644 length = PAGE_ALIGN(md->length); 645 646 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { 647 printk(KERN_ERR "MM: CPU does not support supersection " 648 "mapping for 0x%08llx at 0x%08lx\n", 649 (long long)__pfn_to_phys((u64)md->pfn), addr); 650 return; 651 } 652 653 /* N.B. ARMv6 supersections are only defined to work with domain 0. 654 * Since domain assignments can in fact be arbitrary, the 655 * 'domain == 0' check below is required to insure that ARMv6 656 * supersections are only allocated for domain 0 regardless 657 * of the actual domain assignments in use. 658 */ 659 if (type->domain) { 660 printk(KERN_ERR "MM: invalid domain in supersection " 661 "mapping for 0x%08llx at 0x%08lx\n", 662 (long long)__pfn_to_phys((u64)md->pfn), addr); 663 return; 664 } 665 666 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { 667 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" 668 " at 0x%08lx invalid alignment\n", 669 (long long)__pfn_to_phys((u64)md->pfn), addr); 670 return; 671 } 672 673 /* 674 * Shift bits [35:32] of address into bits [23:20] of PMD 675 * (See ARMv6 spec). 676 */ 677 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); 678 679 pgd = pgd_offset_k(addr); 680 end = addr + length; 681 do { 682 pud_t *pud = pud_offset(pgd, addr); 683 pmd_t *pmd = pmd_offset(pud, addr); 684 int i; 685 686 for (i = 0; i < 16; i++) 687 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); 688 689 addr += SUPERSECTION_SIZE; 690 phys += SUPERSECTION_SIZE; 691 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; 692 } while (addr != end); 693 } 694 #endif /* !CONFIG_ARM_LPAE */ 695 696 /* 697 * Create the page directory entries and any necessary 698 * page tables for the mapping specified by `md'. We 699 * are able to cope here with varying sizes and address 700 * offsets, and we take full advantage of sections and 701 * supersections. 702 */ 703 static void __init create_mapping(struct map_desc *md) 704 { 705 unsigned long addr, length, end; 706 phys_addr_t phys; 707 const struct mem_type *type; 708 pgd_t *pgd; 709 710 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { 711 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" 712 " at 0x%08lx in user region\n", 713 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 714 return; 715 } 716 717 if ((md->type == MT_DEVICE || md->type == MT_ROM) && 718 md->virtual >= PAGE_OFFSET && 719 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { 720 printk(KERN_WARNING "BUG: mapping for 0x%08llx" 721 " at 0x%08lx out of vmalloc space\n", 722 (long long)__pfn_to_phys((u64)md->pfn), md->virtual); 723 } 724 725 type = &mem_types[md->type]; 726 727 #ifndef CONFIG_ARM_LPAE 728 /* 729 * Catch 36-bit addresses 730 */ 731 if (md->pfn >= 0x100000) { 732 create_36bit_mapping(md, type); 733 return; 734 } 735 #endif 736 737 addr = md->virtual & PAGE_MASK; 738 phys = __pfn_to_phys(md->pfn); 739 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 740 741 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { 742 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " 743 "be mapped using pages, ignoring.\n", 744 (long long)__pfn_to_phys(md->pfn), addr); 745 return; 746 } 747 748 pgd = pgd_offset_k(addr); 749 end = addr + length; 750 do { 751 unsigned long next = pgd_addr_end(addr, end); 752 753 alloc_init_pud(pgd, addr, next, phys, type); 754 755 phys += next - addr; 756 addr = next; 757 } while (pgd++, addr != end); 758 } 759 760 /* 761 * Create the architecture specific mappings 762 */ 763 void __init iotable_init(struct map_desc *io_desc, int nr) 764 { 765 struct map_desc *md; 766 struct vm_struct *vm; 767 768 if (!nr) 769 return; 770 771 vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm)); 772 773 for (md = io_desc; nr; md++, nr--) { 774 create_mapping(md); 775 vm->addr = (void *)(md->virtual & PAGE_MASK); 776 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); 777 vm->phys_addr = __pfn_to_phys(md->pfn); 778 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; 779 vm->flags |= VM_ARM_MTYPE(md->type); 780 vm->caller = iotable_init; 781 vm_area_add_early(vm++); 782 } 783 } 784 785 static void * __initdata vmalloc_min = 786 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); 787 788 /* 789 * vmalloc=size forces the vmalloc area to be exactly 'size' 790 * bytes. This can be used to increase (or decrease) the vmalloc 791 * area - the default is 240m. 792 */ 793 static int __init early_vmalloc(char *arg) 794 { 795 unsigned long vmalloc_reserve = memparse(arg, NULL); 796 797 if (vmalloc_reserve < SZ_16M) { 798 vmalloc_reserve = SZ_16M; 799 printk(KERN_WARNING 800 "vmalloc area too small, limiting to %luMB\n", 801 vmalloc_reserve >> 20); 802 } 803 804 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { 805 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); 806 printk(KERN_WARNING 807 "vmalloc area is too big, limiting to %luMB\n", 808 vmalloc_reserve >> 20); 809 } 810 811 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); 812 return 0; 813 } 814 early_param("vmalloc", early_vmalloc); 815 816 static phys_addr_t lowmem_limit __initdata = 0; 817 818 void __init sanity_check_meminfo(void) 819 { 820 int i, j, highmem = 0; 821 822 for (i = 0, j = 0; i < meminfo.nr_banks; i++) { 823 struct membank *bank = &meminfo.bank[j]; 824 *bank = meminfo.bank[i]; 825 826 if (bank->start > ULONG_MAX) 827 highmem = 1; 828 829 #ifdef CONFIG_HIGHMEM 830 if (__va(bank->start) >= vmalloc_min || 831 __va(bank->start) < (void *)PAGE_OFFSET) 832 highmem = 1; 833 834 bank->highmem = highmem; 835 836 /* 837 * Split those memory banks which are partially overlapping 838 * the vmalloc area greatly simplifying things later. 839 */ 840 if (!highmem && __va(bank->start) < vmalloc_min && 841 bank->size > vmalloc_min - __va(bank->start)) { 842 if (meminfo.nr_banks >= NR_BANKS) { 843 printk(KERN_CRIT "NR_BANKS too low, " 844 "ignoring high memory\n"); 845 } else { 846 memmove(bank + 1, bank, 847 (meminfo.nr_banks - i) * sizeof(*bank)); 848 meminfo.nr_banks++; 849 i++; 850 bank[1].size -= vmalloc_min - __va(bank->start); 851 bank[1].start = __pa(vmalloc_min - 1) + 1; 852 bank[1].highmem = highmem = 1; 853 j++; 854 } 855 bank->size = vmalloc_min - __va(bank->start); 856 } 857 #else 858 bank->highmem = highmem; 859 860 /* 861 * Highmem banks not allowed with !CONFIG_HIGHMEM. 862 */ 863 if (highmem) { 864 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " 865 "(!CONFIG_HIGHMEM).\n", 866 (unsigned long long)bank->start, 867 (unsigned long long)bank->start + bank->size - 1); 868 continue; 869 } 870 871 /* 872 * Check whether this memory bank would entirely overlap 873 * the vmalloc area. 874 */ 875 if (__va(bank->start) >= vmalloc_min || 876 __va(bank->start) < (void *)PAGE_OFFSET) { 877 printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " 878 "(vmalloc region overlap).\n", 879 (unsigned long long)bank->start, 880 (unsigned long long)bank->start + bank->size - 1); 881 continue; 882 } 883 884 /* 885 * Check whether this memory bank would partially overlap 886 * the vmalloc area. 887 */ 888 if (__va(bank->start + bank->size) > vmalloc_min || 889 __va(bank->start + bank->size) < __va(bank->start)) { 890 unsigned long newsize = vmalloc_min - __va(bank->start); 891 printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " 892 "to -%.8llx (vmalloc region overlap).\n", 893 (unsigned long long)bank->start, 894 (unsigned long long)bank->start + bank->size - 1, 895 (unsigned long long)bank->start + newsize - 1); 896 bank->size = newsize; 897 } 898 #endif 899 if (!bank->highmem && bank->start + bank->size > lowmem_limit) 900 lowmem_limit = bank->start + bank->size; 901 902 j++; 903 } 904 #ifdef CONFIG_HIGHMEM 905 if (highmem) { 906 const char *reason = NULL; 907 908 if (cache_is_vipt_aliasing()) { 909 /* 910 * Interactions between kmap and other mappings 911 * make highmem support with aliasing VIPT caches 912 * rather difficult. 913 */ 914 reason = "with VIPT aliasing cache"; 915 } 916 if (reason) { 917 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", 918 reason); 919 while (j > 0 && meminfo.bank[j - 1].highmem) 920 j--; 921 } 922 } 923 #endif 924 meminfo.nr_banks = j; 925 high_memory = __va(lowmem_limit - 1) + 1; 926 memblock_set_current_limit(lowmem_limit); 927 } 928 929 static inline void prepare_page_table(void) 930 { 931 unsigned long addr; 932 phys_addr_t end; 933 934 /* 935 * Clear out all the mappings below the kernel image. 936 */ 937 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) 938 pmd_clear(pmd_off_k(addr)); 939 940 #ifdef CONFIG_XIP_KERNEL 941 /* The XIP kernel is mapped in the module area -- skip over it */ 942 addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; 943 #endif 944 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) 945 pmd_clear(pmd_off_k(addr)); 946 947 /* 948 * Find the end of the first block of lowmem. 949 */ 950 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; 951 if (end >= lowmem_limit) 952 end = lowmem_limit; 953 954 /* 955 * Clear out all the kernel space mappings, except for the first 956 * memory bank, up to the vmalloc region. 957 */ 958 for (addr = __phys_to_virt(end); 959 addr < VMALLOC_START; addr += PMD_SIZE) 960 pmd_clear(pmd_off_k(addr)); 961 } 962 963 #ifdef CONFIG_ARM_LPAE 964 /* the first page is reserved for pgd */ 965 #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ 966 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) 967 #else 968 #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) 969 #endif 970 971 /* 972 * Reserve the special regions of memory 973 */ 974 void __init arm_mm_memblock_reserve(void) 975 { 976 /* 977 * Reserve the page tables. These are already in use, 978 * and can only be in node 0. 979 */ 980 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); 981 982 #ifdef CONFIG_SA1111 983 /* 984 * Because of the SA1111 DMA bug, we want to preserve our 985 * precious DMA-able memory... 986 */ 987 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); 988 #endif 989 } 990 991 /* 992 * Set up the device mappings. Since we clear out the page tables for all 993 * mappings above VMALLOC_START, we will remove any debug device mappings. 994 * This means you have to be careful how you debug this function, or any 995 * called function. This means you can't use any function or debugging 996 * method which may touch any device, otherwise the kernel _will_ crash. 997 */ 998 static void __init devicemaps_init(struct machine_desc *mdesc) 999 { 1000 struct map_desc map; 1001 unsigned long addr; 1002 void *vectors; 1003 1004 /* 1005 * Allocate the vector page early. 1006 */ 1007 vectors = early_alloc(PAGE_SIZE); 1008 1009 early_trap_init(vectors); 1010 1011 for (addr = VMALLOC_START; addr; addr += PMD_SIZE) 1012 pmd_clear(pmd_off_k(addr)); 1013 1014 /* 1015 * Map the kernel if it is XIP. 1016 * It is always first in the modulearea. 1017 */ 1018 #ifdef CONFIG_XIP_KERNEL 1019 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); 1020 map.virtual = MODULES_VADDR; 1021 map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; 1022 map.type = MT_ROM; 1023 create_mapping(&map); 1024 #endif 1025 1026 /* 1027 * Map the cache flushing regions. 1028 */ 1029 #ifdef FLUSH_BASE 1030 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); 1031 map.virtual = FLUSH_BASE; 1032 map.length = SZ_1M; 1033 map.type = MT_CACHECLEAN; 1034 create_mapping(&map); 1035 #endif 1036 #ifdef FLUSH_BASE_MINICACHE 1037 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); 1038 map.virtual = FLUSH_BASE_MINICACHE; 1039 map.length = SZ_1M; 1040 map.type = MT_MINICLEAN; 1041 create_mapping(&map); 1042 #endif 1043 1044 /* 1045 * Create a mapping for the machine vectors at the high-vectors 1046 * location (0xffff0000). If we aren't using high-vectors, also 1047 * create a mapping at the low-vectors virtual address. 1048 */ 1049 map.pfn = __phys_to_pfn(virt_to_phys(vectors)); 1050 map.virtual = 0xffff0000; 1051 map.length = PAGE_SIZE; 1052 map.type = MT_HIGH_VECTORS; 1053 create_mapping(&map); 1054 1055 if (!vectors_high()) { 1056 map.virtual = 0; 1057 map.type = MT_LOW_VECTORS; 1058 create_mapping(&map); 1059 } 1060 1061 /* 1062 * Ask the machine support to map in the statically mapped devices. 1063 */ 1064 if (mdesc->map_io) 1065 mdesc->map_io(); 1066 1067 /* 1068 * Finally flush the caches and tlb to ensure that we're in a 1069 * consistent state wrt the writebuffer. This also ensures that 1070 * any write-allocated cache lines in the vector page are written 1071 * back. After this point, we can start to touch devices again. 1072 */ 1073 local_flush_tlb_all(); 1074 flush_cache_all(); 1075 } 1076 1077 static void __init kmap_init(void) 1078 { 1079 #ifdef CONFIG_HIGHMEM 1080 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), 1081 PKMAP_BASE, _PAGE_KERNEL_TABLE); 1082 #endif 1083 } 1084 1085 static void __init map_lowmem(void) 1086 { 1087 struct memblock_region *reg; 1088 1089 /* Map all the lowmem memory banks. */ 1090 for_each_memblock(memory, reg) { 1091 phys_addr_t start = reg->base; 1092 phys_addr_t end = start + reg->size; 1093 struct map_desc map; 1094 1095 if (end > lowmem_limit) 1096 end = lowmem_limit; 1097 if (start >= end) 1098 break; 1099 1100 map.pfn = __phys_to_pfn(start); 1101 map.virtual = __phys_to_virt(start); 1102 map.length = end - start; 1103 map.type = MT_MEMORY; 1104 1105 create_mapping(&map); 1106 } 1107 } 1108 1109 /* 1110 * paging_init() sets up the page tables, initialises the zone memory 1111 * maps, and sets up the zero page, bad page and bad page tables. 1112 */ 1113 void __init paging_init(struct machine_desc *mdesc) 1114 { 1115 void *zero_page; 1116 1117 memblock_set_current_limit(lowmem_limit); 1118 1119 build_mem_type_table(); 1120 prepare_page_table(); 1121 map_lowmem(); 1122 devicemaps_init(mdesc); 1123 kmap_init(); 1124 1125 top_pmd = pmd_off_k(0xffff0000); 1126 1127 /* allocate the zero page. */ 1128 zero_page = early_alloc(PAGE_SIZE); 1129 1130 bootmem_init(); 1131 1132 empty_zero_page = virt_to_page(zero_page); 1133 __flush_dcache_page(NULL, empty_zero_page); 1134 } 1135