1*de7e7532SRussell King/* 2*de7e7532SRussell King * L2C-310 early resume code. This can be used by platforms to restore 3*de7e7532SRussell King * the settings of their L2 cache controller before restoring the 4*de7e7532SRussell King * processor state. 5*de7e7532SRussell King * 6*de7e7532SRussell King * This code can only be used to if you are running in the secure world. 7*de7e7532SRussell King */ 8*de7e7532SRussell King#include <linux/linkage.h> 9*de7e7532SRussell King#include <asm/hardware/cache-l2x0.h> 10*de7e7532SRussell King 11*de7e7532SRussell King .text 12*de7e7532SRussell King 13*de7e7532SRussell KingENTRY(l2c310_early_resume) 14*de7e7532SRussell King adr r0, 1f 15*de7e7532SRussell King ldr r2, [r0] 16*de7e7532SRussell King add r0, r2, r0 17*de7e7532SRussell King 18*de7e7532SRussell King ldmia r0, {r1, r2, r3, r4, r5, r6, r7, r8} 19*de7e7532SRussell King @ r1 = phys address of L2C-310 controller 20*de7e7532SRussell King @ r2 = aux_ctrl 21*de7e7532SRussell King @ r3 = tag_latency 22*de7e7532SRussell King @ r4 = data_latency 23*de7e7532SRussell King @ r5 = filter_start 24*de7e7532SRussell King @ r6 = filter_end 25*de7e7532SRussell King @ r7 = prefetch_ctrl 26*de7e7532SRussell King @ r8 = pwr_ctrl 27*de7e7532SRussell King 28*de7e7532SRussell King @ Check that the address has been initialised 29*de7e7532SRussell King teq r1, #0 30*de7e7532SRussell King moveq pc, lr 31*de7e7532SRussell King 32*de7e7532SRussell King @ The prefetch and power control registers are revision dependent 33*de7e7532SRussell King @ and can be written whether or not the L2 cache is enabled 34*de7e7532SRussell King ldr r0, [r1, #L2X0_CACHE_ID] 35*de7e7532SRussell King and r0, r0, #L2X0_CACHE_ID_RTL_MASK 36*de7e7532SRussell King cmp r0, #L310_CACHE_ID_RTL_R2P0 37*de7e7532SRussell King strcs r7, [r1, #L310_PREFETCH_CTRL] 38*de7e7532SRussell King cmp r0, #L310_CACHE_ID_RTL_R3P0 39*de7e7532SRussell King strcs r8, [r1, #L310_POWER_CTRL] 40*de7e7532SRussell King 41*de7e7532SRussell King @ Don't setup the L2 cache if it is already enabled 42*de7e7532SRussell King ldr r0, [r1, #L2X0_CTRL] 43*de7e7532SRussell King tst r0, #L2X0_CTRL_EN 44*de7e7532SRussell King movne pc, lr 45*de7e7532SRussell King 46*de7e7532SRussell King str r3, [r1, #L310_TAG_LATENCY_CTRL] 47*de7e7532SRussell King str r4, [r1, #L310_DATA_LATENCY_CTRL] 48*de7e7532SRussell King str r6, [r1, #L310_ADDR_FILTER_END] 49*de7e7532SRussell King str r5, [r1, #L310_ADDR_FILTER_START] 50*de7e7532SRussell King 51*de7e7532SRussell King str r2, [r1, #L2X0_AUX_CTRL] 52*de7e7532SRussell King mov r9, #L2X0_CTRL_EN 53*de7e7532SRussell King str r9, [r1, #L2X0_CTRL] 54*de7e7532SRussell King mov pc, lr 55*de7e7532SRussell KingENDPROC(l2c310_early_resume) 56*de7e7532SRussell King 57*de7e7532SRussell King .align 58*de7e7532SRussell King1: .long l2x0_saved_regs - . 59