xref: /openbmc/linux/arch/arm/mm/cache-xsc3l2.c (revision dc8601a224d546bb321b058fc5ecabdb688a3582)
1905a09d5SEric Miao /*
2905a09d5SEric Miao  * arch/arm/mm/cache-xsc3l2.c - XScale3 L2 cache controller support
3905a09d5SEric Miao  *
4905a09d5SEric Miao  * Copyright (C) 2007 ARM Limited
5905a09d5SEric Miao  *
6905a09d5SEric Miao  * This program is free software; you can redistribute it and/or modify
7905a09d5SEric Miao  * it under the terms of the GNU General Public License version 2 as
8905a09d5SEric Miao  * published by the Free Software Foundation.
9905a09d5SEric Miao  *
10905a09d5SEric Miao  * This program is distributed in the hope that it will be useful,
11905a09d5SEric Miao  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12905a09d5SEric Miao  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13905a09d5SEric Miao  * GNU General Public License for more details.
14905a09d5SEric Miao  *
15905a09d5SEric Miao  * You should have received a copy of the GNU General Public License
16905a09d5SEric Miao  * along with this program; if not, write to the Free Software
17905a09d5SEric Miao  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18905a09d5SEric Miao  */
19905a09d5SEric Miao #include <linux/init.h>
20905a09d5SEric Miao #include <asm/system.h>
210ba8b9b2SRussell King #include <asm/cputype.h>
22905a09d5SEric Miao #include <asm/cacheflush.h>
233902a15eSNicolas Pitre #include <asm/kmap_types.h>
243902a15eSNicolas Pitre #include <asm/fixmap.h>
253902a15eSNicolas Pitre #include <asm/pgtable.h>
263902a15eSNicolas Pitre #include <asm/tlbflush.h>
273902a15eSNicolas Pitre #include "mm.h"
28905a09d5SEric Miao 
29905a09d5SEric Miao #define CR_L2	(1 << 26)
30905a09d5SEric Miao 
31905a09d5SEric Miao #define CACHE_LINE_SIZE		32
32905a09d5SEric Miao #define CACHE_LINE_SHIFT	5
33905a09d5SEric Miao #define CACHE_WAY_PER_SET	8
34905a09d5SEric Miao 
35905a09d5SEric Miao #define CACHE_WAY_SIZE(l2ctype)	(8192 << (((l2ctype) >> 8) & 0xf))
36905a09d5SEric Miao #define CACHE_SET_SIZE(l2ctype)	(CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)
37905a09d5SEric Miao 
38905a09d5SEric Miao static inline int xsc3_l2_present(void)
39905a09d5SEric Miao {
40905a09d5SEric Miao 	unsigned long l2ctype;
41905a09d5SEric Miao 
42905a09d5SEric Miao 	__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
43905a09d5SEric Miao 
44905a09d5SEric Miao 	return !!(l2ctype & 0xf8);
45905a09d5SEric Miao }
46905a09d5SEric Miao 
47905a09d5SEric Miao static inline void xsc3_l2_clean_mva(unsigned long addr)
48905a09d5SEric Miao {
49905a09d5SEric Miao 	__asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr));
50905a09d5SEric Miao }
51905a09d5SEric Miao 
52905a09d5SEric Miao static inline void xsc3_l2_inv_mva(unsigned long addr)
53905a09d5SEric Miao {
54905a09d5SEric Miao 	__asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr));
55905a09d5SEric Miao }
56905a09d5SEric Miao 
57905a09d5SEric Miao static inline void xsc3_l2_inv_all(void)
58905a09d5SEric Miao {
59905a09d5SEric Miao 	unsigned long l2ctype, set_way;
60905a09d5SEric Miao 	int set, way;
61905a09d5SEric Miao 
62905a09d5SEric Miao 	__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
63905a09d5SEric Miao 
64905a09d5SEric Miao 	for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
65905a09d5SEric Miao 		for (way = 0; way < CACHE_WAY_PER_SET; way++) {
66905a09d5SEric Miao 			set_way = (way << 29) | (set << 5);
67905a09d5SEric Miao 			__asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way));
68905a09d5SEric Miao 		}
69905a09d5SEric Miao 	}
70905a09d5SEric Miao 
71905a09d5SEric Miao 	dsb();
72905a09d5SEric Miao }
73905a09d5SEric Miao 
743902a15eSNicolas Pitre #ifdef CONFIG_HIGHMEM
753902a15eSNicolas Pitre #define l2_map_save_flags(x)		raw_local_save_flags(x)
763902a15eSNicolas Pitre #define l2_map_restore_flags(x)		raw_local_irq_restore(x)
773902a15eSNicolas Pitre #else
783902a15eSNicolas Pitre #define l2_map_save_flags(x)		((x) = 0)
793902a15eSNicolas Pitre #define l2_map_restore_flags(x)		((void)(x))
803902a15eSNicolas Pitre #endif
813902a15eSNicolas Pitre 
823902a15eSNicolas Pitre static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va,
833902a15eSNicolas Pitre 				      unsigned long flags)
843902a15eSNicolas Pitre {
853902a15eSNicolas Pitre #ifdef CONFIG_HIGHMEM
863902a15eSNicolas Pitre 	unsigned long va = prev_va & PAGE_MASK;
873902a15eSNicolas Pitre 	unsigned long pa_offset = pa << (32 - PAGE_SHIFT);
883902a15eSNicolas Pitre 	if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) {
893902a15eSNicolas Pitre 		/*
903902a15eSNicolas Pitre 		 * Switching to a new page.  Because cache ops are
913902a15eSNicolas Pitre 		 * using virtual addresses only, we must put a mapping
923902a15eSNicolas Pitre 		 * in place for it.  We also enable interrupts for a
933902a15eSNicolas Pitre 		 * short while and disable them again to protect this
943902a15eSNicolas Pitre 		 * mapping.
953902a15eSNicolas Pitre 		 */
963902a15eSNicolas Pitre 		unsigned long idx;
973902a15eSNicolas Pitre 		raw_local_irq_restore(flags);
983902a15eSNicolas Pitre 		idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id();
993902a15eSNicolas Pitre 		va = __fix_to_virt(FIX_KMAP_BEGIN + idx);
1003902a15eSNicolas Pitre 		raw_local_irq_restore(flags | PSR_I_BIT);
1013902a15eSNicolas Pitre 		set_pte_ext(TOP_PTE(va), pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL), 0);
1023902a15eSNicolas Pitre 		local_flush_tlb_kernel_page(va);
1033902a15eSNicolas Pitre 	}
1043902a15eSNicolas Pitre 	return va + (pa_offset >> (32 - PAGE_SHIFT));
1053902a15eSNicolas Pitre #else
1063902a15eSNicolas Pitre 	return __phys_to_virt(pa);
1073902a15eSNicolas Pitre #endif
1083902a15eSNicolas Pitre }
1093902a15eSNicolas Pitre 
110905a09d5SEric Miao static void xsc3_l2_inv_range(unsigned long start, unsigned long end)
111905a09d5SEric Miao {
1123902a15eSNicolas Pitre 	unsigned long vaddr, flags;
1133902a15eSNicolas Pitre 
114905a09d5SEric Miao 	if (start == 0 && end == -1ul) {
115905a09d5SEric Miao 		xsc3_l2_inv_all();
116905a09d5SEric Miao 		return;
117905a09d5SEric Miao 	}
118905a09d5SEric Miao 
1193902a15eSNicolas Pitre 	vaddr = -1;  /* to force the first mapping */
1203902a15eSNicolas Pitre 	l2_map_save_flags(flags);
1213902a15eSNicolas Pitre 
122905a09d5SEric Miao 	/*
123905a09d5SEric Miao 	 * Clean and invalidate partial first cache line.
124905a09d5SEric Miao 	 */
125905a09d5SEric Miao 	if (start & (CACHE_LINE_SIZE - 1)) {
1263902a15eSNicolas Pitre 		vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr, flags);
1273902a15eSNicolas Pitre 		xsc3_l2_clean_mva(vaddr);
1283902a15eSNicolas Pitre 		xsc3_l2_inv_mva(vaddr);
129905a09d5SEric Miao 		start = (start | (CACHE_LINE_SIZE - 1)) + 1;
130905a09d5SEric Miao 	}
131905a09d5SEric Miao 
132905a09d5SEric Miao 	/*
133905a09d5SEric Miao 	 * Invalidate all full cache lines between 'start' and 'end'.
134905a09d5SEric Miao 	 */
1353902a15eSNicolas Pitre 	while (start < (end & ~(CACHE_LINE_SIZE - 1))) {
1363902a15eSNicolas Pitre 		vaddr = l2_map_va(start, vaddr, flags);
1373902a15eSNicolas Pitre 		xsc3_l2_inv_mva(vaddr);
138905a09d5SEric Miao 		start += CACHE_LINE_SIZE;
139905a09d5SEric Miao 	}
140905a09d5SEric Miao 
1413902a15eSNicolas Pitre 	/*
1423902a15eSNicolas Pitre 	 * Clean and invalidate partial last cache line.
1433902a15eSNicolas Pitre 	 */
1443902a15eSNicolas Pitre 	if (start < end) {
1453902a15eSNicolas Pitre 		vaddr = l2_map_va(start, vaddr, flags);
1463902a15eSNicolas Pitre 		xsc3_l2_clean_mva(vaddr);
1473902a15eSNicolas Pitre 		xsc3_l2_inv_mva(vaddr);
1483902a15eSNicolas Pitre 	}
1493902a15eSNicolas Pitre 
1503902a15eSNicolas Pitre 	l2_map_restore_flags(flags);
1513902a15eSNicolas Pitre 
152905a09d5SEric Miao 	dsb();
153905a09d5SEric Miao }
154905a09d5SEric Miao 
155905a09d5SEric Miao static void xsc3_l2_clean_range(unsigned long start, unsigned long end)
156905a09d5SEric Miao {
1573902a15eSNicolas Pitre 	unsigned long vaddr, flags;
1583902a15eSNicolas Pitre 
1593902a15eSNicolas Pitre 	vaddr = -1;  /* to force the first mapping */
1603902a15eSNicolas Pitre 	l2_map_save_flags(flags);
1613902a15eSNicolas Pitre 
162905a09d5SEric Miao 	start &= ~(CACHE_LINE_SIZE - 1);
163905a09d5SEric Miao 	while (start < end) {
1643902a15eSNicolas Pitre 		vaddr = l2_map_va(start, vaddr, flags);
1653902a15eSNicolas Pitre 		xsc3_l2_clean_mva(vaddr);
166905a09d5SEric Miao 		start += CACHE_LINE_SIZE;
167905a09d5SEric Miao 	}
168905a09d5SEric Miao 
1693902a15eSNicolas Pitre 	l2_map_restore_flags(flags);
1703902a15eSNicolas Pitre 
171905a09d5SEric Miao 	dsb();
172905a09d5SEric Miao }
173905a09d5SEric Miao 
174905a09d5SEric Miao /*
175905a09d5SEric Miao  * optimize L2 flush all operation by set/way format
176905a09d5SEric Miao  */
177905a09d5SEric Miao static inline void xsc3_l2_flush_all(void)
178905a09d5SEric Miao {
179905a09d5SEric Miao 	unsigned long l2ctype, set_way;
180905a09d5SEric Miao 	int set, way;
181905a09d5SEric Miao 
182905a09d5SEric Miao 	__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
183905a09d5SEric Miao 
184905a09d5SEric Miao 	for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
185905a09d5SEric Miao 		for (way = 0; way < CACHE_WAY_PER_SET; way++) {
186905a09d5SEric Miao 			set_way = (way << 29) | (set << 5);
187905a09d5SEric Miao 			__asm__("mcr p15, 1, %0, c7, c15, 2" : : "r"(set_way));
188905a09d5SEric Miao 		}
189905a09d5SEric Miao 	}
190905a09d5SEric Miao 
191905a09d5SEric Miao 	dsb();
192905a09d5SEric Miao }
193905a09d5SEric Miao 
194905a09d5SEric Miao static void xsc3_l2_flush_range(unsigned long start, unsigned long end)
195905a09d5SEric Miao {
1963902a15eSNicolas Pitre 	unsigned long vaddr, flags;
1973902a15eSNicolas Pitre 
198905a09d5SEric Miao 	if (start == 0 && end == -1ul) {
199905a09d5SEric Miao 		xsc3_l2_flush_all();
200905a09d5SEric Miao 		return;
201905a09d5SEric Miao 	}
202905a09d5SEric Miao 
2033902a15eSNicolas Pitre 	vaddr = -1;  /* to force the first mapping */
2043902a15eSNicolas Pitre 	l2_map_save_flags(flags);
2053902a15eSNicolas Pitre 
206905a09d5SEric Miao 	start &= ~(CACHE_LINE_SIZE - 1);
207905a09d5SEric Miao 	while (start < end) {
2083902a15eSNicolas Pitre 		vaddr = l2_map_va(start, vaddr, flags);
2093902a15eSNicolas Pitre 		xsc3_l2_clean_mva(vaddr);
2103902a15eSNicolas Pitre 		xsc3_l2_inv_mva(vaddr);
211905a09d5SEric Miao 		start += CACHE_LINE_SIZE;
212905a09d5SEric Miao 	}
213905a09d5SEric Miao 
2143902a15eSNicolas Pitre 	l2_map_restore_flags(flags);
2153902a15eSNicolas Pitre 
216905a09d5SEric Miao 	dsb();
217905a09d5SEric Miao }
218905a09d5SEric Miao 
219905a09d5SEric Miao static int __init xsc3_l2_init(void)
220905a09d5SEric Miao {
221905a09d5SEric Miao 	if (!cpu_is_xsc3() || !xsc3_l2_present())
222905a09d5SEric Miao 		return 0;
223905a09d5SEric Miao 
224*dc8601a2SHaojian Zhuang 	if (get_cr() & CR_L2) {
225905a09d5SEric Miao 		pr_info("XScale3 L2 cache enabled.\n");
226905a09d5SEric Miao 		xsc3_l2_inv_all();
227905a09d5SEric Miao 
228905a09d5SEric Miao 		outer_cache.inv_range = xsc3_l2_inv_range;
229905a09d5SEric Miao 		outer_cache.clean_range = xsc3_l2_clean_range;
230905a09d5SEric Miao 		outer_cache.flush_range = xsc3_l2_flush_range;
231*dc8601a2SHaojian Zhuang 	}
232905a09d5SEric Miao 
233905a09d5SEric Miao 	return 0;
234905a09d5SEric Miao }
235905a09d5SEric Miao core_initcall(xsc3_l2_init);
236