171b9114dSArnd Bergmann/* SPDX-License-Identifier: GPL-2.0 */ 271b9114dSArnd Bergmann/* linux/arch/arm/plat-s3c64xx/sleep.S 371b9114dSArnd Bergmann * 471b9114dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 571b9114dSArnd Bergmann * Copyright 2008 Simtec Electronics 671b9114dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 771b9114dSArnd Bergmann * http://armlinux.simtec.co.uk/ 871b9114dSArnd Bergmann * 971b9114dSArnd Bergmann * S3C64XX CPU sleep code 1071b9114dSArnd Bergmann */ 1171b9114dSArnd Bergmann 1271b9114dSArnd Bergmann#include <linux/linkage.h> 1371b9114dSArnd Bergmann#include <asm/assembler.h> 14*c6ff132dSArnd Bergmann#include "map.h" 1571b9114dSArnd Bergmann 1671b9114dSArnd Bergmann#undef S3C64XX_VA_GPIO 1771b9114dSArnd Bergmann#define S3C64XX_VA_GPIO (0x0) 1871b9114dSArnd Bergmann 19*c6ff132dSArnd Bergmann#include "regs-gpio.h" 2071b9114dSArnd Bergmann 2171b9114dSArnd Bergmann#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) 2271b9114dSArnd Bergmann 2371b9114dSArnd Bergmann .text 2471b9114dSArnd Bergmann 2571b9114dSArnd Bergmann /* Sleep magic, the word before the resume entry point so that the 2671b9114dSArnd Bergmann * bootloader can check for a resumeable image. */ 2771b9114dSArnd Bergmann 2871b9114dSArnd Bergmann .word 0x2bedf00d 2971b9114dSArnd Bergmann 3071b9114dSArnd Bergmann /* s3c_cpu_reusme 3171b9114dSArnd Bergmann * 3271b9114dSArnd Bergmann * This is the entry point, stored by whatever method the bootloader 3371b9114dSArnd Bergmann * requires to get the kernel runnign again. This code expects to be 3471b9114dSArnd Bergmann * entered with no caches live and the MMU disabled. It will then 3571b9114dSArnd Bergmann * restore the MMU and other basic CP registers saved and restart 3671b9114dSArnd Bergmann * the kernel C code to finish the resume code. 3771b9114dSArnd Bergmann */ 3871b9114dSArnd Bergmann 3971b9114dSArnd BergmannENTRY(s3c_cpu_resume) 4071b9114dSArnd Bergmann msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE 4171b9114dSArnd Bergmann ldr r2, =LL_UART /* for debug */ 4271b9114dSArnd Bergmann 4371b9114dSArnd Bergmann#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 4471b9114dSArnd Bergmann 4571b9114dSArnd Bergmann#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) 4671b9114dSArnd Bergmann#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) 4771b9114dSArnd Bergmann 4871b9114dSArnd Bergmann#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) 4971b9114dSArnd Bergmann#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) 5071b9114dSArnd Bergmann 5171b9114dSArnd Bergmann /* Initialise the GPIO state if we are debugging via the SMDK LEDs, 5271b9114dSArnd Bergmann * as the uboot version supplied resets these to inputs during the 5371b9114dSArnd Bergmann * resume checks. 5471b9114dSArnd Bergmann */ 5571b9114dSArnd Bergmann 5671b9114dSArnd Bergmann ldr r3, =S3C64XX_PA_GPIO 5771b9114dSArnd Bergmann ldr r0, [ r3, #S3C64XX_GPNCON ] 5871b9114dSArnd Bergmann bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ 5971b9114dSArnd Bergmann S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) 6071b9114dSArnd Bergmann orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ 6171b9114dSArnd Bergmann S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) 6271b9114dSArnd Bergmann str r0, [ r3, #S3C64XX_GPNCON ] 6371b9114dSArnd Bergmann 6471b9114dSArnd Bergmann ldr r0, [ r3, #S3C64XX_GPNDAT ] 6571b9114dSArnd Bergmann bic r0, r0, #0xf << 12 @ GPN12..15 6671b9114dSArnd Bergmann orr r0, r0, #1 << 15 @ GPN15 6771b9114dSArnd Bergmann str r0, [ r3, #S3C64XX_GPNDAT ] 6871b9114dSArnd Bergmann#endif 6971b9114dSArnd Bergmann b cpu_resume 70