1*71b9114dSArnd Bergmann/* SPDX-License-Identifier: GPL-2.0 */ 2*71b9114dSArnd Bergmann/* linux/arch/arm/plat-s3c64xx/sleep.S 3*71b9114dSArnd Bergmann * 4*71b9114dSArnd Bergmann * Copyright 2008 Openmoko, Inc. 5*71b9114dSArnd Bergmann * Copyright 2008 Simtec Electronics 6*71b9114dSArnd Bergmann * Ben Dooks <ben@simtec.co.uk> 7*71b9114dSArnd Bergmann * http://armlinux.simtec.co.uk/ 8*71b9114dSArnd Bergmann * 9*71b9114dSArnd Bergmann * S3C64XX CPU sleep code 10*71b9114dSArnd Bergmann */ 11*71b9114dSArnd Bergmann 12*71b9114dSArnd Bergmann#include <linux/linkage.h> 13*71b9114dSArnd Bergmann#include <asm/assembler.h> 14*71b9114dSArnd Bergmann#include <mach/map.h> 15*71b9114dSArnd Bergmann 16*71b9114dSArnd Bergmann#undef S3C64XX_VA_GPIO 17*71b9114dSArnd Bergmann#define S3C64XX_VA_GPIO (0x0) 18*71b9114dSArnd Bergmann 19*71b9114dSArnd Bergmann#include <mach/regs-gpio.h> 20*71b9114dSArnd Bergmann 21*71b9114dSArnd Bergmann#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) 22*71b9114dSArnd Bergmann 23*71b9114dSArnd Bergmann .text 24*71b9114dSArnd Bergmann 25*71b9114dSArnd Bergmann /* Sleep magic, the word before the resume entry point so that the 26*71b9114dSArnd Bergmann * bootloader can check for a resumeable image. */ 27*71b9114dSArnd Bergmann 28*71b9114dSArnd Bergmann .word 0x2bedf00d 29*71b9114dSArnd Bergmann 30*71b9114dSArnd Bergmann /* s3c_cpu_reusme 31*71b9114dSArnd Bergmann * 32*71b9114dSArnd Bergmann * This is the entry point, stored by whatever method the bootloader 33*71b9114dSArnd Bergmann * requires to get the kernel runnign again. This code expects to be 34*71b9114dSArnd Bergmann * entered with no caches live and the MMU disabled. It will then 35*71b9114dSArnd Bergmann * restore the MMU and other basic CP registers saved and restart 36*71b9114dSArnd Bergmann * the kernel C code to finish the resume code. 37*71b9114dSArnd Bergmann */ 38*71b9114dSArnd Bergmann 39*71b9114dSArnd BergmannENTRY(s3c_cpu_resume) 40*71b9114dSArnd Bergmann msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE 41*71b9114dSArnd Bergmann ldr r2, =LL_UART /* for debug */ 42*71b9114dSArnd Bergmann 43*71b9114dSArnd Bergmann#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 44*71b9114dSArnd Bergmann 45*71b9114dSArnd Bergmann#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) 46*71b9114dSArnd Bergmann#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) 47*71b9114dSArnd Bergmann 48*71b9114dSArnd Bergmann#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) 49*71b9114dSArnd Bergmann#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) 50*71b9114dSArnd Bergmann 51*71b9114dSArnd Bergmann /* Initialise the GPIO state if we are debugging via the SMDK LEDs, 52*71b9114dSArnd Bergmann * as the uboot version supplied resets these to inputs during the 53*71b9114dSArnd Bergmann * resume checks. 54*71b9114dSArnd Bergmann */ 55*71b9114dSArnd Bergmann 56*71b9114dSArnd Bergmann ldr r3, =S3C64XX_PA_GPIO 57*71b9114dSArnd Bergmann ldr r0, [ r3, #S3C64XX_GPNCON ] 58*71b9114dSArnd Bergmann bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ 59*71b9114dSArnd Bergmann S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) 60*71b9114dSArnd Bergmann orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ 61*71b9114dSArnd Bergmann S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) 62*71b9114dSArnd Bergmann str r0, [ r3, #S3C64XX_GPNCON ] 63*71b9114dSArnd Bergmann 64*71b9114dSArnd Bergmann ldr r0, [ r3, #S3C64XX_GPNDAT ] 65*71b9114dSArnd Bergmann bic r0, r0, #0xf << 12 @ GPN12..15 66*71b9114dSArnd Bergmann orr r0, r0, #1 << 15 @ GPN15 67*71b9114dSArnd Bergmann str r0, [ r3, #S3C64XX_GPNDAT ] 68*71b9114dSArnd Bergmann#endif 69*71b9114dSArnd Bergmann b cpu_resume 70