xref: /openbmc/linux/arch/arm/mach-s3c/sleep-s3c64xx.S (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
171b9114dSArnd Bergmann/* SPDX-License-Identifier: GPL-2.0 */
271b9114dSArnd Bergmann/* linux/arch/arm/plat-s3c64xx/sleep.S
371b9114dSArnd Bergmann *
471b9114dSArnd Bergmann * Copyright 2008 Openmoko, Inc.
571b9114dSArnd Bergmann * Copyright 2008 Simtec Electronics
671b9114dSArnd Bergmann *	Ben Dooks <ben@simtec.co.uk>
771b9114dSArnd Bergmann *	http://armlinux.simtec.co.uk/
871b9114dSArnd Bergmann *
971b9114dSArnd Bergmann * S3C64XX CPU sleep code
1071b9114dSArnd Bergmann */
1171b9114dSArnd Bergmann
1271b9114dSArnd Bergmann#include <linux/linkage.h>
1371b9114dSArnd Bergmann#include <asm/assembler.h>
14*c6ff132dSArnd Bergmann#include "map.h"
1571b9114dSArnd Bergmann
1671b9114dSArnd Bergmann#undef S3C64XX_VA_GPIO
1771b9114dSArnd Bergmann#define S3C64XX_VA_GPIO (0x0)
1871b9114dSArnd Bergmann
19*c6ff132dSArnd Bergmann#include "regs-gpio.h"
2071b9114dSArnd Bergmann
2171b9114dSArnd Bergmann#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
2271b9114dSArnd Bergmann
2371b9114dSArnd Bergmann	.text
2471b9114dSArnd Bergmann
2571b9114dSArnd Bergmann	/* Sleep magic, the word before the resume entry point so that the
2671b9114dSArnd Bergmann	 * bootloader can check for a resumeable image. */
2771b9114dSArnd Bergmann
2871b9114dSArnd Bergmann	.word	0x2bedf00d
2971b9114dSArnd Bergmann
3071b9114dSArnd Bergmann	/* s3c_cpu_reusme
3171b9114dSArnd Bergmann	 *
3271b9114dSArnd Bergmann	 * This is the entry point, stored by whatever method the bootloader
3371b9114dSArnd Bergmann	 * requires to get the kernel runnign again. This code expects to be
3471b9114dSArnd Bergmann	 * entered with no caches live and the MMU disabled. It will then
3571b9114dSArnd Bergmann	 * restore the MMU and other basic CP registers saved and restart
3671b9114dSArnd Bergmann	 * the kernel C code to finish the resume code.
3771b9114dSArnd Bergmann	*/
3871b9114dSArnd Bergmann
3971b9114dSArnd BergmannENTRY(s3c_cpu_resume)
4071b9114dSArnd Bergmann	msr	cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
4171b9114dSArnd Bergmann	ldr	r2, =LL_UART		/* for debug */
4271b9114dSArnd Bergmann	b	cpu_resume
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