12025cf9eSThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 29c1ec8e1SChris Zhong/* 39c1ec8e1SChris Zhong * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 49c1ec8e1SChris Zhong * Author: Tony Xie <tony.xie@rock-chips.com> 59c1ec8e1SChris Zhong */ 69c1ec8e1SChris Zhong 79c1ec8e1SChris Zhong#include <linux/linkage.h> 89c1ec8e1SChris Zhong#include <asm/assembler.h> 9*a9ff6961SLinus Walleij#include <asm/page.h> 109c1ec8e1SChris Zhong 119c1ec8e1SChris Zhong.data 129c1ec8e1SChris Zhong/* 139c1ec8e1SChris Zhong * this code will be copied from 149c1ec8e1SChris Zhong * ddr to sram for system resumeing. 159c1ec8e1SChris Zhong * so it is ".data section". 169c1ec8e1SChris Zhong */ 171abd3502SRussell King .align 2 189c1ec8e1SChris Zhong 199c1ec8e1SChris ZhongENTRY(rockchip_slp_cpu_resume) 209c1ec8e1SChris Zhong setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off 219c1ec8e1SChris Zhong mrc p15, 0, r1, c0, c0, 5 229c1ec8e1SChris Zhong and r1, r1, #0xf 239c1ec8e1SChris Zhong cmp r1, #0 249c1ec8e1SChris Zhong /* olny cpu0 can continue to run, the others is halt here */ 259c1ec8e1SChris Zhong beq cpu0run 269c1ec8e1SChris Zhongsecondary_loop: 279c1ec8e1SChris Zhong wfe 289c1ec8e1SChris Zhong b secondary_loop 299c1ec8e1SChris Zhongcpu0run: 309c1ec8e1SChris Zhong ldr r3, rkpm_bootdata_l2ctlr_f 319c1ec8e1SChris Zhong cmp r3, #0 329c1ec8e1SChris Zhong beq sp_set 339c1ec8e1SChris Zhong ldr r3, rkpm_bootdata_l2ctlr 349c1ec8e1SChris Zhong mcr p15, 1, r3, c9, c0, 2 359c1ec8e1SChris Zhongsp_set: 369c1ec8e1SChris Zhong ldr sp, rkpm_bootdata_cpusp 379c1ec8e1SChris Zhong ldr r1, rkpm_bootdata_cpu_code 389c1ec8e1SChris Zhong bx r1 399c1ec8e1SChris ZhongENDPROC(rockchip_slp_cpu_resume) 409c1ec8e1SChris Zhong 419c1ec8e1SChris Zhong/* Parameters filled in by the kernel */ 429c1ec8e1SChris Zhong 439c1ec8e1SChris Zhong/* Flag for whether to restore L2CTLR on resume */ 449c1ec8e1SChris Zhong .global rkpm_bootdata_l2ctlr_f 459c1ec8e1SChris Zhongrkpm_bootdata_l2ctlr_f: 469c1ec8e1SChris Zhong .long 0 479c1ec8e1SChris Zhong 489c1ec8e1SChris Zhong/* Saved L2CTLR to restore on resume */ 499c1ec8e1SChris Zhong .global rkpm_bootdata_l2ctlr 509c1ec8e1SChris Zhongrkpm_bootdata_l2ctlr: 519c1ec8e1SChris Zhong .long 0 529c1ec8e1SChris Zhong 539c1ec8e1SChris Zhong/* CPU resume SP addr */ 549c1ec8e1SChris Zhong .globl rkpm_bootdata_cpusp 559c1ec8e1SChris Zhongrkpm_bootdata_cpusp: 569c1ec8e1SChris Zhong .long 0 579c1ec8e1SChris Zhong 589c1ec8e1SChris Zhong/* CPU resume function (physical address) */ 599c1ec8e1SChris Zhong .globl rkpm_bootdata_cpu_code 609c1ec8e1SChris Zhongrkpm_bootdata_cpu_code: 619c1ec8e1SChris Zhong .long 0 629c1ec8e1SChris Zhong 639c1ec8e1SChris ZhongENTRY(rk3288_bootram_sz) 649c1ec8e1SChris Zhong .word . - rockchip_slp_cpu_resume 65