1 /* 2 * linux/arch/arm/mach-pxa/pxa25x.c 3 * 4 * Author: Nicolas Pitre 5 * Created: Jun 15, 2001 6 * Copyright: MontaVista Software Inc. 7 * 8 * Code specific to PXA21x/25x/26x variants. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * Since this file should be linked before any other machine specific file, 15 * the __initcall() here will be executed first. This serves as default 16 * initialization stuff for PXA machines which can be overridden later if 17 * need be. 18 */ 19 #include <linux/module.h> 20 #include <linux/kernel.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 #include <linux/suspend.h> 24 #include <linux/sysdev.h> 25 26 #include <asm/hardware.h> 27 #include <asm/arch/irqs.h> 28 #include <asm/arch/pxa-regs.h> 29 #include <asm/arch/pxa2xx-regs.h> 30 #include <asm/arch/mfp-pxa25x.h> 31 #include <asm/arch/reset.h> 32 #include <asm/arch/pm.h> 33 #include <asm/arch/dma.h> 34 35 #include "generic.h" 36 #include "devices.h" 37 #include "clock.h" 38 39 /* 40 * Various clock factors driven by the CCCR register. 41 */ 42 43 /* Crystal Frequency to Memory Frequency Multiplier (L) */ 44 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, }; 45 46 /* Memory Frequency to Run Mode Frequency Multiplier (M) */ 47 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 }; 48 49 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */ 50 /* Note: we store the value N * 2 here. */ 51 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 }; 52 53 /* Crystal clock */ 54 #define BASE_CLK 3686400 55 56 /* 57 * Get the clock frequency as reflected by CCCR and the turbo flag. 58 * We assume these values have been applied via a fcs. 59 * If info is not 0 we also display the current settings. 60 */ 61 unsigned int pxa25x_get_clk_frequency_khz(int info) 62 { 63 unsigned long cccr, turbo; 64 unsigned int l, L, m, M, n2, N; 65 66 cccr = CCCR; 67 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) ); 68 69 l = L_clk_mult[(cccr >> 0) & 0x1f]; 70 m = M_clk_mult[(cccr >> 5) & 0x03]; 71 n2 = N2_clk_mult[(cccr >> 7) & 0x07]; 72 73 L = l * BASE_CLK; 74 M = m * L; 75 N = n2 * M / 2; 76 77 if(info) 78 { 79 L += 5000; 80 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n", 81 L / 1000000, (L % 1000000) / 10000, l ); 82 M += 5000; 83 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", 84 M / 1000000, (M % 1000000) / 10000, m ); 85 N += 5000; 86 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", 87 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5, 88 (turbo & 1) ? "" : "in" ); 89 } 90 91 return (turbo & 1) ? (N/1000) : (M/1000); 92 } 93 94 /* 95 * Return the current memory clock frequency in units of 10kHz 96 */ 97 unsigned int pxa25x_get_memclk_frequency_10khz(void) 98 { 99 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 100 } 101 102 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk) 103 { 104 return pxa25x_get_memclk_frequency_10khz() * 10000; 105 } 106 107 static const struct clkops clk_pxa25x_lcd_ops = { 108 .enable = clk_cken_enable, 109 .disable = clk_cken_disable, 110 .getrate = clk_pxa25x_lcd_getrate, 111 }; 112 113 static unsigned long gpio12_config_32k[] = { 114 GPIO12_32KHz, 115 }; 116 117 static unsigned long gpio12_config_gpio[] = { 118 GPIO12_GPIO, 119 }; 120 121 static void clk_gpio12_enable(struct clk *clk) 122 { 123 pxa2xx_mfp_config(gpio12_config_32k, 1); 124 } 125 126 static void clk_gpio12_disable(struct clk *clk) 127 { 128 pxa2xx_mfp_config(gpio12_config_gpio, 1); 129 } 130 131 static const struct clkops clk_pxa25x_gpio12_ops = { 132 .enable = clk_gpio12_enable, 133 .disable = clk_gpio12_disable, 134 }; 135 136 static unsigned long gpio11_config_3m6[] = { 137 GPIO11_3_6MHz, 138 }; 139 140 static unsigned long gpio11_config_gpio[] = { 141 GPIO11_GPIO, 142 }; 143 144 static void clk_gpio11_enable(struct clk *clk) 145 { 146 pxa2xx_mfp_config(gpio11_config_3m6, 1); 147 } 148 149 static void clk_gpio11_disable(struct clk *clk) 150 { 151 pxa2xx_mfp_config(gpio11_config_gpio, 1); 152 } 153 154 static const struct clkops clk_pxa25x_gpio11_ops = { 155 .enable = clk_gpio11_enable, 156 .disable = clk_gpio11_disable, 157 }; 158 159 /* 160 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz) 161 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz 162 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly) 163 */ 164 static struct clk pxa25x_hwuart_clk = 165 INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev) 166 ; 167 168 /* 169 * PXA 2xx clock declarations. Order is important (see aliases below) 170 * Please be careful not to disrupt the ordering. 171 */ 172 static struct clk pxa25x_clks[] = { 173 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev), 174 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev), 175 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev), 176 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL), 177 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev), 178 INIT_CLK("GPIO11_CLK", &clk_pxa25x_gpio11_ops, 3686400, 0, NULL), 179 INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL), 180 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev), 181 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev), 182 183 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev), 184 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev), 185 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev), 186 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev), 187 INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev), 188 189 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL), 190 191 /* 192 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL), 193 */ 194 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL), 195 }; 196 197 static struct clk pxa2xx_clk_aliases[] = { 198 INIT_CKOTHER("GPIO7_CLK", &pxa25x_clks[4], NULL), 199 INIT_CKOTHER("SA1111_CLK", &pxa25x_clks[5], NULL), 200 }; 201 202 #ifdef CONFIG_PM 203 204 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 205 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 206 207 /* 208 * List of global PXA peripheral registers to preserve. 209 * More ones like CP and general purpose register values are preserved 210 * with the stack pointer in sleep.S. 211 */ 212 enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, 213 214 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 215 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 216 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U, 217 218 SLEEP_SAVE_PSTR, 219 220 SLEEP_SAVE_CKEN, 221 222 SLEEP_SAVE_COUNT 223 }; 224 225 226 static void pxa25x_cpu_pm_save(unsigned long *sleep_save) 227 { 228 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); 229 230 SAVE(GAFR0_L); SAVE(GAFR0_U); 231 SAVE(GAFR1_L); SAVE(GAFR1_U); 232 SAVE(GAFR2_L); SAVE(GAFR2_U); 233 234 SAVE(CKEN); 235 SAVE(PSTR); 236 237 /* Clear GPIO transition detect bits */ 238 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; 239 } 240 241 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save) 242 { 243 /* ensure not to come back here if it wasn't intended */ 244 PSPR = 0; 245 246 /* restore registers */ 247 RESTORE(GAFR0_L); RESTORE(GAFR0_U); 248 RESTORE(GAFR1_L); RESTORE(GAFR1_U); 249 RESTORE(GAFR2_L); RESTORE(GAFR2_U); 250 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 251 252 PSSR = PSSR_RDH | PSSR_PH; 253 254 RESTORE(CKEN); 255 RESTORE(PSTR); 256 } 257 258 static void pxa25x_cpu_pm_enter(suspend_state_t state) 259 { 260 /* Clear reset status */ 261 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 262 263 switch (state) { 264 case PM_SUSPEND_MEM: 265 /* set resume return address */ 266 PSPR = virt_to_phys(pxa_cpu_resume); 267 pxa25x_cpu_suspend(PWRMODE_SLEEP); 268 break; 269 } 270 } 271 272 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { 273 .save_count = SLEEP_SAVE_COUNT, 274 .valid = suspend_valid_only_mem, 275 .save = pxa25x_cpu_pm_save, 276 .restore = pxa25x_cpu_pm_restore, 277 .enter = pxa25x_cpu_pm_enter, 278 }; 279 280 static void __init pxa25x_init_pm(void) 281 { 282 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns; 283 } 284 #else 285 static inline void pxa25x_init_pm(void) {} 286 #endif 287 288 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm 289 */ 290 291 static int pxa25x_set_wake(unsigned int irq, unsigned int on) 292 { 293 int gpio = IRQ_TO_GPIO(irq); 294 uint32_t mask = 0; 295 296 if (gpio >= 0 && gpio < 85) 297 return gpio_set_wake(gpio, on); 298 299 if (irq == IRQ_RTCAlrm) { 300 mask = PWER_RTC; 301 goto set_pwer; 302 } 303 304 return -EINVAL; 305 306 set_pwer: 307 if (on) 308 PWER |= mask; 309 else 310 PWER &=~mask; 311 312 return 0; 313 } 314 315 void __init pxa25x_init_irq(void) 316 { 317 pxa_init_irq(32, pxa25x_set_wake); 318 pxa_init_gpio(85, pxa25x_set_wake); 319 } 320 321 static struct platform_device *pxa25x_devices[] __initdata = { 322 &pxa25x_device_udc, 323 &pxa_device_ffuart, 324 &pxa_device_btuart, 325 &pxa_device_stuart, 326 &pxa_device_i2s, 327 &pxa_device_rtc, 328 &pxa25x_device_ssp, 329 &pxa25x_device_nssp, 330 &pxa25x_device_assp, 331 &pxa25x_device_pwm0, 332 &pxa25x_device_pwm1, 333 }; 334 335 static struct sys_device pxa25x_sysdev[] = { 336 { 337 .cls = &pxa_irq_sysclass, 338 }, { 339 .cls = &pxa_gpio_sysclass, 340 }, 341 }; 342 343 static int __init pxa25x_init(void) 344 { 345 int i, ret = 0; 346 347 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 348 if (cpu_is_pxa255()) 349 clks_register(&pxa25x_hwuart_clk, 1); 350 351 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 352 353 reset_status = RCSR; 354 355 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks)); 356 357 if ((ret = pxa_init_dma(16))) 358 return ret; 359 360 pxa25x_init_pm(); 361 362 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) { 363 ret = sysdev_register(&pxa25x_sysdev[i]); 364 if (ret) 365 pr_err("failed to register sysdev[%d]\n", i); 366 } 367 368 ret = platform_add_devices(pxa25x_devices, 369 ARRAY_SIZE(pxa25x_devices)); 370 if (ret) 371 return ret; 372 } 373 374 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */ 375 if (cpu_is_pxa255()) 376 ret = platform_device_register(&pxa_device_hwuart); 377 378 clks_register(pxa2xx_clk_aliases, ARRAY_SIZE(pxa2xx_clk_aliases)); 379 380 return ret; 381 } 382 383 postcore_initcall(pxa25x_init); 384