1 /* 2 * OMAP4 Power Management Routines 3 * 4 * Copyright (C) 2010-2011 Texas Instruments, Inc. 5 * Rajendra Nayak <rnayak@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/pm.h> 14 #include <linux/suspend.h> 15 #include <linux/module.h> 16 #include <linux/list.h> 17 #include <linux/err.h> 18 #include <linux/slab.h> 19 #include <asm/system_misc.h> 20 21 #include "soc.h" 22 #include "common.h" 23 #include "clockdomain.h" 24 #include "powerdomain.h" 25 #include "pm.h" 26 27 struct power_state { 28 struct powerdomain *pwrdm; 29 u32 next_state; 30 #ifdef CONFIG_SUSPEND 31 u32 saved_state; 32 u32 saved_logic_state; 33 #endif 34 struct list_head node; 35 }; 36 37 static LIST_HEAD(pwrst_list); 38 39 #ifdef CONFIG_SUSPEND 40 static int omap4_pm_suspend(void) 41 { 42 struct power_state *pwrst; 43 int state, ret = 0; 44 u32 cpu_id = smp_processor_id(); 45 46 /* Save current powerdomain state */ 47 list_for_each_entry(pwrst, &pwrst_list, node) { 48 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); 49 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm); 50 } 51 52 /* Set targeted power domain states by suspend */ 53 list_for_each_entry(pwrst, &pwrst_list, node) { 54 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 55 pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); 56 } 57 58 /* 59 * For MPUSS to hit power domain retention(CSWR or OSWR), 60 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state, 61 * since CPU power domain CSWR is not supported by hardware 62 * Only master CPU follows suspend path. All other CPUs follow 63 * CPU hotplug path in system wide suspend. On OMAP4, CPU power 64 * domain CSWR is not supported by hardware. 65 * More details can be found in OMAP4430 TRM section 4.3.4.2. 66 */ 67 omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); 68 69 /* Restore next powerdomain state */ 70 list_for_each_entry(pwrst, &pwrst_list, node) { 71 state = pwrdm_read_prev_pwrst(pwrst->pwrdm); 72 if (state > pwrst->next_state) { 73 pr_info("Powerdomain (%s) didn't enter target state %d\n", 74 pwrst->pwrdm->name, pwrst->next_state); 75 ret = -1; 76 } 77 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 78 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state); 79 } 80 if (ret) 81 pr_crit("Could not enter target state in pm_suspend\n"); 82 else 83 pr_info("Successfully put all powerdomains to target state\n"); 84 85 return 0; 86 } 87 #endif /* CONFIG_SUSPEND */ 88 89 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) 90 { 91 struct power_state *pwrst; 92 93 if (!pwrdm->pwrsts) 94 return 0; 95 96 /* 97 * Skip CPU0 and CPU1 power domains. CPU1 is programmed 98 * through hotplug path and CPU0 explicitly programmed 99 * further down in the code path 100 */ 101 if (!strncmp(pwrdm->name, "cpu", 3)) 102 return 0; 103 104 /* 105 * FIXME: Remove this check when core retention is supported 106 * Only MPUSS power domain is added in the list. 107 */ 108 if (strcmp(pwrdm->name, "mpu_pwrdm")) 109 return 0; 110 111 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); 112 if (!pwrst) 113 return -ENOMEM; 114 115 pwrst->pwrdm = pwrdm; 116 pwrst->next_state = PWRDM_POWER_RET; 117 list_add(&pwrst->node, &pwrst_list); 118 119 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); 120 } 121 122 /** 123 * omap_default_idle - OMAP4 default ilde routine.' 124 * 125 * Implements OMAP4 memory, IO ordering requirements which can't be addressed 126 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and 127 * by secondary CPU with CONFIG_CPUIDLE. 128 */ 129 static void omap_default_idle(void) 130 { 131 local_fiq_disable(); 132 133 omap_do_wfi(); 134 135 local_fiq_enable(); 136 } 137 138 /** 139 * omap4_pm_init - Init routine for OMAP4 PM 140 * 141 * Initializes all powerdomain and clockdomain target states 142 * and all PRCM settings. 143 */ 144 int __init omap4_pm_init(void) 145 { 146 int ret; 147 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup; 148 struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm; 149 150 if (omap_rev() == OMAP4430_REV_ES1_0) { 151 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); 152 return -ENODEV; 153 } 154 155 pr_err("Power Management for TI OMAP4.\n"); 156 157 ret = pwrdm_for_each(pwrdms_setup, NULL); 158 if (ret) { 159 pr_err("Failed to setup powerdomains\n"); 160 goto err2; 161 } 162 163 /* 164 * The dynamic dependency between MPUSS -> MEMIF and 165 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as 166 * expected. The hardware recommendation is to enable static 167 * dependencies for these to avoid system lock ups or random crashes. 168 * The L4 wakeup depedency is added to workaround the OCP sync hardware 169 * BUG with 32K synctimer which lead to incorrect timer value read 170 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which 171 * are part of L4 wakeup clockdomain. 172 */ 173 mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); 174 emif_clkdm = clkdm_lookup("l3_emif_clkdm"); 175 l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); 176 l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); 177 l4_per_clkdm = clkdm_lookup("l4_per_clkdm"); 178 l4wkup = clkdm_lookup("l4_wkup_clkdm"); 179 ducati_clkdm = clkdm_lookup("ducati_clkdm"); 180 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) || 181 (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm)) 182 goto err2; 183 184 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); 185 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); 186 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); 187 ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm); 188 ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup); 189 ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); 190 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); 191 if (ret) { 192 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); 193 goto err2; 194 } 195 196 ret = omap4_mpuss_init(); 197 if (ret) { 198 pr_err("Failed to initialise OMAP4 MPUSS\n"); 199 goto err2; 200 } 201 202 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); 203 204 #ifdef CONFIG_SUSPEND 205 omap_pm_suspend = omap4_pm_suspend; 206 #endif 207 208 /* Overwrite the default cpu_do_idle() */ 209 arm_pm_idle = omap_default_idle; 210 211 omap4_idle_init(); 212 213 err2: 214 return ret; 215 } 216