1b2b9762fSSantosh Shilimkar /* 2b2b9762fSSantosh Shilimkar * OMAP MPUSS low power code 3b2b9762fSSantosh Shilimkar * 4b2b9762fSSantosh Shilimkar * Copyright (C) 2011 Texas Instruments, Inc. 5b2b9762fSSantosh Shilimkar * Santosh Shilimkar <santosh.shilimkar@ti.com> 6b2b9762fSSantosh Shilimkar * 7b2b9762fSSantosh Shilimkar * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU 8b2b9762fSSantosh Shilimkar * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller, 9b2b9762fSSantosh Shilimkar * CPU0 and CPU1 LPRM modules. 10b2b9762fSSantosh Shilimkar * CPU0, CPU1 and MPUSS each have there own power domain and 11b2b9762fSSantosh Shilimkar * hence multiple low power combinations of MPUSS are possible. 12b2b9762fSSantosh Shilimkar * 13b2b9762fSSantosh Shilimkar * The CPU0 and CPU1 can't support Closed switch Retention (CSWR) 14b2b9762fSSantosh Shilimkar * because the mode is not supported by hw constraints of dormant 15b2b9762fSSantosh Shilimkar * mode. While waking up from the dormant mode, a reset signal 16b2b9762fSSantosh Shilimkar * to the Cortex-A9 processor must be asserted by the external 17b2b9762fSSantosh Shilimkar * power controller. 18b2b9762fSSantosh Shilimkar * 19b2b9762fSSantosh Shilimkar * With architectural inputs and hardware recommendations, only 20b2b9762fSSantosh Shilimkar * below modes are supported from power gain vs latency point of view. 21b2b9762fSSantosh Shilimkar * 22b2b9762fSSantosh Shilimkar * CPU0 CPU1 MPUSS 23b2b9762fSSantosh Shilimkar * ---------------------------------------------- 24b2b9762fSSantosh Shilimkar * ON ON ON 25b2b9762fSSantosh Shilimkar * ON(Inactive) OFF ON(Inactive) 26b2b9762fSSantosh Shilimkar * OFF OFF CSWR 27*3ba2a739SSantosh Shilimkar * OFF OFF OSWR 28*3ba2a739SSantosh Shilimkar * OFF OFF OFF(Device OFF *TBD) 29b2b9762fSSantosh Shilimkar * ---------------------------------------------- 30b2b9762fSSantosh Shilimkar * 31b2b9762fSSantosh Shilimkar * Note: CPU0 is the master core and it is the last CPU to go down 32b2b9762fSSantosh Shilimkar * and first to wake-up when MPUSS low power states are excercised 33b2b9762fSSantosh Shilimkar * 34b2b9762fSSantosh Shilimkar * 35b2b9762fSSantosh Shilimkar * This program is free software; you can redistribute it and/or modify 36b2b9762fSSantosh Shilimkar * it under the terms of the GNU General Public License version 2 as 37b2b9762fSSantosh Shilimkar * published by the Free Software Foundation. 38b2b9762fSSantosh Shilimkar */ 39b2b9762fSSantosh Shilimkar 40b2b9762fSSantosh Shilimkar #include <linux/kernel.h> 41b2b9762fSSantosh Shilimkar #include <linux/io.h> 42b2b9762fSSantosh Shilimkar #include <linux/errno.h> 43b2b9762fSSantosh Shilimkar #include <linux/linkage.h> 44b2b9762fSSantosh Shilimkar #include <linux/smp.h> 45b2b9762fSSantosh Shilimkar 46b2b9762fSSantosh Shilimkar #include <asm/cacheflush.h> 47b2b9762fSSantosh Shilimkar #include <asm/tlbflush.h> 48b2b9762fSSantosh Shilimkar #include <asm/smp_scu.h> 49b2b9762fSSantosh Shilimkar #include <asm/system.h> 50b2b9762fSSantosh Shilimkar #include <asm/pgalloc.h> 51b2b9762fSSantosh Shilimkar #include <asm/suspend.h> 525e94c6e3SSantosh Shilimkar #include <asm/hardware/cache-l2x0.h> 53b2b9762fSSantosh Shilimkar 54b2b9762fSSantosh Shilimkar #include <plat/omap44xx.h> 55b2b9762fSSantosh Shilimkar 56b2b9762fSSantosh Shilimkar #include "common.h" 57b2b9762fSSantosh Shilimkar #include "omap4-sar-layout.h" 58b2b9762fSSantosh Shilimkar #include "pm.h" 59*3ba2a739SSantosh Shilimkar #include "prcm_mpu44xx.h" 60*3ba2a739SSantosh Shilimkar #include "prminst44xx.h" 61*3ba2a739SSantosh Shilimkar #include "prcm44xx.h" 62*3ba2a739SSantosh Shilimkar #include "prm44xx.h" 63*3ba2a739SSantosh Shilimkar #include "prm-regbits-44xx.h" 64b2b9762fSSantosh Shilimkar 65b2b9762fSSantosh Shilimkar #ifdef CONFIG_SMP 66b2b9762fSSantosh Shilimkar 67b2b9762fSSantosh Shilimkar struct omap4_cpu_pm_info { 68b2b9762fSSantosh Shilimkar struct powerdomain *pwrdm; 69b2b9762fSSantosh Shilimkar void __iomem *scu_sar_addr; 70b2b9762fSSantosh Shilimkar void __iomem *wkup_sar_addr; 715e94c6e3SSantosh Shilimkar void __iomem *l2x0_sar_addr; 72b2b9762fSSantosh Shilimkar }; 73b2b9762fSSantosh Shilimkar 74b2b9762fSSantosh Shilimkar static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); 75e44f9a77SSantosh Shilimkar static struct powerdomain *mpuss_pd; 765e94c6e3SSantosh Shilimkar static void __iomem *sar_base; 77b2b9762fSSantosh Shilimkar 78b2b9762fSSantosh Shilimkar /* 79b2b9762fSSantosh Shilimkar * Program the wakeup routine address for the CPU0 and CPU1 80b2b9762fSSantosh Shilimkar * used for OFF or DORMANT wakeup. 81b2b9762fSSantosh Shilimkar */ 82b2b9762fSSantosh Shilimkar static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr) 83b2b9762fSSantosh Shilimkar { 84b2b9762fSSantosh Shilimkar struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 85b2b9762fSSantosh Shilimkar 86b2b9762fSSantosh Shilimkar __raw_writel(addr, pm_info->wkup_sar_addr); 87b2b9762fSSantosh Shilimkar } 88b2b9762fSSantosh Shilimkar 89b2b9762fSSantosh Shilimkar /* 90b2b9762fSSantosh Shilimkar * Set the CPUx powerdomain's previous power state 91b2b9762fSSantosh Shilimkar */ 92b2b9762fSSantosh Shilimkar static inline void set_cpu_next_pwrst(unsigned int cpu_id, 93b2b9762fSSantosh Shilimkar unsigned int power_state) 94b2b9762fSSantosh Shilimkar { 95b2b9762fSSantosh Shilimkar struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 96b2b9762fSSantosh Shilimkar 97b2b9762fSSantosh Shilimkar pwrdm_set_next_pwrst(pm_info->pwrdm, power_state); 98b2b9762fSSantosh Shilimkar } 99b2b9762fSSantosh Shilimkar 100b2b9762fSSantosh Shilimkar /* 101b2b9762fSSantosh Shilimkar * Read CPU's previous power state 102b2b9762fSSantosh Shilimkar */ 103b2b9762fSSantosh Shilimkar static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id) 104b2b9762fSSantosh Shilimkar { 105b2b9762fSSantosh Shilimkar struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 106b2b9762fSSantosh Shilimkar 107b2b9762fSSantosh Shilimkar return pwrdm_read_prev_pwrst(pm_info->pwrdm); 108b2b9762fSSantosh Shilimkar } 109b2b9762fSSantosh Shilimkar 110b2b9762fSSantosh Shilimkar /* 111b2b9762fSSantosh Shilimkar * Clear the CPUx powerdomain's previous power state 112b2b9762fSSantosh Shilimkar */ 113b2b9762fSSantosh Shilimkar static inline void clear_cpu_prev_pwrst(unsigned int cpu_id) 114b2b9762fSSantosh Shilimkar { 115b2b9762fSSantosh Shilimkar struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 116b2b9762fSSantosh Shilimkar 117b2b9762fSSantosh Shilimkar pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 118b2b9762fSSantosh Shilimkar } 119b2b9762fSSantosh Shilimkar 120b2b9762fSSantosh Shilimkar /* 121b2b9762fSSantosh Shilimkar * Store the SCU power status value to scratchpad memory 122b2b9762fSSantosh Shilimkar */ 123b2b9762fSSantosh Shilimkar static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) 124b2b9762fSSantosh Shilimkar { 125b2b9762fSSantosh Shilimkar struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 126b2b9762fSSantosh Shilimkar u32 scu_pwr_st; 127b2b9762fSSantosh Shilimkar 128b2b9762fSSantosh Shilimkar switch (cpu_state) { 129b2b9762fSSantosh Shilimkar case PWRDM_POWER_RET: 130b2b9762fSSantosh Shilimkar scu_pwr_st = SCU_PM_DORMANT; 131b2b9762fSSantosh Shilimkar break; 132b2b9762fSSantosh Shilimkar case PWRDM_POWER_OFF: 133b2b9762fSSantosh Shilimkar scu_pwr_st = SCU_PM_POWEROFF; 134b2b9762fSSantosh Shilimkar break; 135b2b9762fSSantosh Shilimkar case PWRDM_POWER_ON: 136b2b9762fSSantosh Shilimkar case PWRDM_POWER_INACTIVE: 137b2b9762fSSantosh Shilimkar default: 138b2b9762fSSantosh Shilimkar scu_pwr_st = SCU_PM_NORMAL; 139b2b9762fSSantosh Shilimkar break; 140b2b9762fSSantosh Shilimkar } 141b2b9762fSSantosh Shilimkar 142b2b9762fSSantosh Shilimkar __raw_writel(scu_pwr_st, pm_info->scu_sar_addr); 143b2b9762fSSantosh Shilimkar } 144b2b9762fSSantosh Shilimkar 145*3ba2a739SSantosh Shilimkar /* Helper functions for MPUSS OSWR */ 146*3ba2a739SSantosh Shilimkar static inline void mpuss_clear_prev_logic_pwrst(void) 147*3ba2a739SSantosh Shilimkar { 148*3ba2a739SSantosh Shilimkar u32 reg; 149*3ba2a739SSantosh Shilimkar 150*3ba2a739SSantosh Shilimkar reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 151*3ba2a739SSantosh Shilimkar OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 152*3ba2a739SSantosh Shilimkar omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION, 153*3ba2a739SSantosh Shilimkar OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 154*3ba2a739SSantosh Shilimkar } 155*3ba2a739SSantosh Shilimkar 156*3ba2a739SSantosh Shilimkar static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id) 157*3ba2a739SSantosh Shilimkar { 158*3ba2a739SSantosh Shilimkar u32 reg; 159*3ba2a739SSantosh Shilimkar 160*3ba2a739SSantosh Shilimkar if (cpu_id) { 161*3ba2a739SSantosh Shilimkar reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, 162*3ba2a739SSantosh Shilimkar OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); 163*3ba2a739SSantosh Shilimkar omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, 164*3ba2a739SSantosh Shilimkar OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); 165*3ba2a739SSantosh Shilimkar } else { 166*3ba2a739SSantosh Shilimkar reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, 167*3ba2a739SSantosh Shilimkar OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); 168*3ba2a739SSantosh Shilimkar omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, 169*3ba2a739SSantosh Shilimkar OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); 170*3ba2a739SSantosh Shilimkar } 171*3ba2a739SSantosh Shilimkar } 172*3ba2a739SSantosh Shilimkar 173*3ba2a739SSantosh Shilimkar /** 174*3ba2a739SSantosh Shilimkar * omap4_mpuss_read_prev_context_state: 175*3ba2a739SSantosh Shilimkar * Function returns the MPUSS previous context state 176*3ba2a739SSantosh Shilimkar */ 177*3ba2a739SSantosh Shilimkar u32 omap4_mpuss_read_prev_context_state(void) 178*3ba2a739SSantosh Shilimkar { 179*3ba2a739SSantosh Shilimkar u32 reg; 180*3ba2a739SSantosh Shilimkar 181*3ba2a739SSantosh Shilimkar reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 182*3ba2a739SSantosh Shilimkar OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET); 183*3ba2a739SSantosh Shilimkar reg &= OMAP4430_LOSTCONTEXT_DFF_MASK; 184*3ba2a739SSantosh Shilimkar return reg; 185*3ba2a739SSantosh Shilimkar } 186*3ba2a739SSantosh Shilimkar 1875e94c6e3SSantosh Shilimkar /* 1885e94c6e3SSantosh Shilimkar * Store the CPU cluster state for L2X0 low power operations. 1895e94c6e3SSantosh Shilimkar */ 1905e94c6e3SSantosh Shilimkar static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state) 1915e94c6e3SSantosh Shilimkar { 1925e94c6e3SSantosh Shilimkar struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id); 1935e94c6e3SSantosh Shilimkar 1945e94c6e3SSantosh Shilimkar __raw_writel(save_state, pm_info->l2x0_sar_addr); 1955e94c6e3SSantosh Shilimkar } 1965e94c6e3SSantosh Shilimkar 1975e94c6e3SSantosh Shilimkar /* 1985e94c6e3SSantosh Shilimkar * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to 1995e94c6e3SSantosh Shilimkar * in every restore MPUSS OFF path. 2005e94c6e3SSantosh Shilimkar */ 2015e94c6e3SSantosh Shilimkar #ifdef CONFIG_CACHE_L2X0 2025e94c6e3SSantosh Shilimkar static void save_l2x0_context(void) 2035e94c6e3SSantosh Shilimkar { 2045e94c6e3SSantosh Shilimkar u32 val; 2055e94c6e3SSantosh Shilimkar void __iomem *l2x0_base = omap4_get_l2cache_base(); 2065e94c6e3SSantosh Shilimkar 2075e94c6e3SSantosh Shilimkar val = __raw_readl(l2x0_base + L2X0_AUX_CTRL); 2085e94c6e3SSantosh Shilimkar __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET); 2095e94c6e3SSantosh Shilimkar val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL); 2105e94c6e3SSantosh Shilimkar __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET); 2115e94c6e3SSantosh Shilimkar } 2125e94c6e3SSantosh Shilimkar #else 2135e94c6e3SSantosh Shilimkar static void save_l2x0_context(void) 2145e94c6e3SSantosh Shilimkar {} 2155e94c6e3SSantosh Shilimkar #endif 2165e94c6e3SSantosh Shilimkar 217b2b9762fSSantosh Shilimkar /** 218b2b9762fSSantosh Shilimkar * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function 219b2b9762fSSantosh Shilimkar * The purpose of this function is to manage low power programming 220b2b9762fSSantosh Shilimkar * of OMAP4 MPUSS subsystem 221b2b9762fSSantosh Shilimkar * @cpu : CPU ID 222b2b9762fSSantosh Shilimkar * @power_state: Low power state. 223e44f9a77SSantosh Shilimkar * 224e44f9a77SSantosh Shilimkar * MPUSS states for the context save: 225e44f9a77SSantosh Shilimkar * save_state = 226e44f9a77SSantosh Shilimkar * 0 - Nothing lost and no need to save: MPUSS INACTIVE 227e44f9a77SSantosh Shilimkar * 1 - CPUx L1 and logic lost: MPUSS CSWR 228e44f9a77SSantosh Shilimkar * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR 229e44f9a77SSantosh Shilimkar * 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF 230b2b9762fSSantosh Shilimkar */ 231b2b9762fSSantosh Shilimkar int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) 232b2b9762fSSantosh Shilimkar { 233b2b9762fSSantosh Shilimkar unsigned int save_state = 0; 234b2b9762fSSantosh Shilimkar unsigned int wakeup_cpu; 235b2b9762fSSantosh Shilimkar 236b2b9762fSSantosh Shilimkar if (omap_rev() == OMAP4430_REV_ES1_0) 237b2b9762fSSantosh Shilimkar return -ENXIO; 238b2b9762fSSantosh Shilimkar 239b2b9762fSSantosh Shilimkar switch (power_state) { 240b2b9762fSSantosh Shilimkar case PWRDM_POWER_ON: 241b2b9762fSSantosh Shilimkar case PWRDM_POWER_INACTIVE: 242b2b9762fSSantosh Shilimkar save_state = 0; 243b2b9762fSSantosh Shilimkar break; 244b2b9762fSSantosh Shilimkar case PWRDM_POWER_OFF: 245b2b9762fSSantosh Shilimkar save_state = 1; 246b2b9762fSSantosh Shilimkar break; 247b2b9762fSSantosh Shilimkar case PWRDM_POWER_RET: 248b2b9762fSSantosh Shilimkar default: 249b2b9762fSSantosh Shilimkar /* 250b2b9762fSSantosh Shilimkar * CPUx CSWR is invalid hardware state. Also CPUx OSWR 251b2b9762fSSantosh Shilimkar * doesn't make much scense, since logic is lost and $L1 252b2b9762fSSantosh Shilimkar * needs to be cleaned because of coherency. This makes 253b2b9762fSSantosh Shilimkar * CPUx OSWR equivalent to CPUX OFF and hence not supported 254b2b9762fSSantosh Shilimkar */ 255b2b9762fSSantosh Shilimkar WARN_ON(1); 256b2b9762fSSantosh Shilimkar return -ENXIO; 257b2b9762fSSantosh Shilimkar } 258b2b9762fSSantosh Shilimkar 259*3ba2a739SSantosh Shilimkar /* 260*3ba2a739SSantosh Shilimkar * Check MPUSS next state and save interrupt controller if needed. 261*3ba2a739SSantosh Shilimkar * In MPUSS OSWR or device OFF, interrupt controller contest is lost. 262*3ba2a739SSantosh Shilimkar */ 263*3ba2a739SSantosh Shilimkar mpuss_clear_prev_logic_pwrst(); 264e44f9a77SSantosh Shilimkar pwrdm_clear_all_prev_pwrst(mpuss_pd); 265*3ba2a739SSantosh Shilimkar if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) && 266*3ba2a739SSantosh Shilimkar (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF)) 267*3ba2a739SSantosh Shilimkar save_state = 2; 268*3ba2a739SSantosh Shilimkar 269b2b9762fSSantosh Shilimkar clear_cpu_prev_pwrst(cpu); 270*3ba2a739SSantosh Shilimkar cpu_clear_prev_logic_pwrst(cpu); 271b2b9762fSSantosh Shilimkar set_cpu_next_pwrst(cpu, power_state); 272b2b9762fSSantosh Shilimkar set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); 273b2b9762fSSantosh Shilimkar scu_pwrst_prepare(cpu, power_state); 2745e94c6e3SSantosh Shilimkar l2x0_pwrst_prepare(cpu, save_state); 275b2b9762fSSantosh Shilimkar 276b2b9762fSSantosh Shilimkar /* 277b2b9762fSSantosh Shilimkar * Call low level function with targeted low power state. 278b2b9762fSSantosh Shilimkar */ 279b2b9762fSSantosh Shilimkar cpu_suspend(save_state, omap4_finish_suspend); 280b2b9762fSSantosh Shilimkar 281b2b9762fSSantosh Shilimkar /* 282b2b9762fSSantosh Shilimkar * Restore the CPUx power state to ON otherwise CPUx 283b2b9762fSSantosh Shilimkar * power domain can transitions to programmed low power 284b2b9762fSSantosh Shilimkar * state while doing WFI outside the low powe code. On 285b2b9762fSSantosh Shilimkar * secure devices, CPUx does WFI which can result in 286b2b9762fSSantosh Shilimkar * domain transition 287b2b9762fSSantosh Shilimkar */ 288b2b9762fSSantosh Shilimkar wakeup_cpu = smp_processor_id(); 289b2b9762fSSantosh Shilimkar set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON); 290b2b9762fSSantosh Shilimkar 291b2b9762fSSantosh Shilimkar return 0; 292b2b9762fSSantosh Shilimkar } 293b2b9762fSSantosh Shilimkar 294b5b4f288SSantosh Shilimkar /** 295b5b4f288SSantosh Shilimkar * omap4_hotplug_cpu: OMAP4 CPU hotplug entry 296b5b4f288SSantosh Shilimkar * @cpu : CPU ID 297b5b4f288SSantosh Shilimkar * @power_state: CPU low power state. 298b5b4f288SSantosh Shilimkar */ 299b5b4f288SSantosh Shilimkar int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) 300b5b4f288SSantosh Shilimkar { 301b5b4f288SSantosh Shilimkar unsigned int cpu_state = 0; 302b5b4f288SSantosh Shilimkar 303b5b4f288SSantosh Shilimkar if (omap_rev() == OMAP4430_REV_ES1_0) 304b5b4f288SSantosh Shilimkar return -ENXIO; 305b5b4f288SSantosh Shilimkar 306b5b4f288SSantosh Shilimkar if (power_state == PWRDM_POWER_OFF) 307b5b4f288SSantosh Shilimkar cpu_state = 1; 308b5b4f288SSantosh Shilimkar 309b5b4f288SSantosh Shilimkar clear_cpu_prev_pwrst(cpu); 310b5b4f288SSantosh Shilimkar set_cpu_next_pwrst(cpu, power_state); 311b5b4f288SSantosh Shilimkar set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup)); 312b5b4f288SSantosh Shilimkar scu_pwrst_prepare(cpu, power_state); 313b5b4f288SSantosh Shilimkar 314b5b4f288SSantosh Shilimkar /* 315b5b4f288SSantosh Shilimkar * CPU never retuns back if targetted power state is OFF mode. 316b5b4f288SSantosh Shilimkar * CPU ONLINE follows normal CPU ONLINE ptah via 317b5b4f288SSantosh Shilimkar * omap_secondary_startup(). 318b5b4f288SSantosh Shilimkar */ 319b5b4f288SSantosh Shilimkar omap4_finish_suspend(cpu_state); 320b5b4f288SSantosh Shilimkar 321b5b4f288SSantosh Shilimkar set_cpu_next_pwrst(cpu, PWRDM_POWER_ON); 322b5b4f288SSantosh Shilimkar return 0; 323b5b4f288SSantosh Shilimkar } 324b5b4f288SSantosh Shilimkar 325b5b4f288SSantosh Shilimkar 326b2b9762fSSantosh Shilimkar /* 327b2b9762fSSantosh Shilimkar * Initialise OMAP4 MPUSS 328b2b9762fSSantosh Shilimkar */ 329b2b9762fSSantosh Shilimkar int __init omap4_mpuss_init(void) 330b2b9762fSSantosh Shilimkar { 331b2b9762fSSantosh Shilimkar struct omap4_cpu_pm_info *pm_info; 332b2b9762fSSantosh Shilimkar 333b2b9762fSSantosh Shilimkar if (omap_rev() == OMAP4430_REV_ES1_0) { 334b2b9762fSSantosh Shilimkar WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); 335b2b9762fSSantosh Shilimkar return -ENODEV; 336b2b9762fSSantosh Shilimkar } 337b2b9762fSSantosh Shilimkar 3385e94c6e3SSantosh Shilimkar sar_base = omap4_get_sar_ram_base(); 3395e94c6e3SSantosh Shilimkar 340b2b9762fSSantosh Shilimkar /* Initilaise per CPU PM information */ 341b2b9762fSSantosh Shilimkar pm_info = &per_cpu(omap4_pm_info, 0x0); 342b2b9762fSSantosh Shilimkar pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; 343b2b9762fSSantosh Shilimkar pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET; 3445e94c6e3SSantosh Shilimkar pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; 345b2b9762fSSantosh Shilimkar pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm"); 346b2b9762fSSantosh Shilimkar if (!pm_info->pwrdm) { 347b2b9762fSSantosh Shilimkar pr_err("Lookup failed for CPU0 pwrdm\n"); 348b2b9762fSSantosh Shilimkar return -ENODEV; 349b2b9762fSSantosh Shilimkar } 350b2b9762fSSantosh Shilimkar 351b2b9762fSSantosh Shilimkar /* Clear CPU previous power domain state */ 352b2b9762fSSantosh Shilimkar pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 353*3ba2a739SSantosh Shilimkar cpu_clear_prev_logic_pwrst(0); 354b2b9762fSSantosh Shilimkar 355b2b9762fSSantosh Shilimkar /* Initialise CPU0 power domain state to ON */ 356b2b9762fSSantosh Shilimkar pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 357b2b9762fSSantosh Shilimkar 358b2b9762fSSantosh Shilimkar pm_info = &per_cpu(omap4_pm_info, 0x1); 359b2b9762fSSantosh Shilimkar pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; 360b2b9762fSSantosh Shilimkar pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; 3615e94c6e3SSantosh Shilimkar pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; 362b2b9762fSSantosh Shilimkar pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm"); 363b2b9762fSSantosh Shilimkar if (!pm_info->pwrdm) { 364b2b9762fSSantosh Shilimkar pr_err("Lookup failed for CPU1 pwrdm\n"); 365b2b9762fSSantosh Shilimkar return -ENODEV; 366b2b9762fSSantosh Shilimkar } 367b2b9762fSSantosh Shilimkar 368b2b9762fSSantosh Shilimkar /* Clear CPU previous power domain state */ 369b2b9762fSSantosh Shilimkar pwrdm_clear_all_prev_pwrst(pm_info->pwrdm); 370*3ba2a739SSantosh Shilimkar cpu_clear_prev_logic_pwrst(1); 371b2b9762fSSantosh Shilimkar 372b2b9762fSSantosh Shilimkar /* Initialise CPU1 power domain state to ON */ 373b2b9762fSSantosh Shilimkar pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); 374b2b9762fSSantosh Shilimkar 375e44f9a77SSantosh Shilimkar mpuss_pd = pwrdm_lookup("mpu_pwrdm"); 376e44f9a77SSantosh Shilimkar if (!mpuss_pd) { 377e44f9a77SSantosh Shilimkar pr_err("Failed to lookup MPUSS power domain\n"); 378e44f9a77SSantosh Shilimkar return -ENODEV; 379e44f9a77SSantosh Shilimkar } 380e44f9a77SSantosh Shilimkar pwrdm_clear_all_prev_pwrst(mpuss_pd); 381*3ba2a739SSantosh Shilimkar mpuss_clear_prev_logic_pwrst(); 382e44f9a77SSantosh Shilimkar 383b2b9762fSSantosh Shilimkar /* Save device type on scratchpad for low level code to use */ 384b2b9762fSSantosh Shilimkar if (omap_type() != OMAP2_DEVICE_TYPE_GP) 385b2b9762fSSantosh Shilimkar __raw_writel(1, sar_base + OMAP_TYPE_OFFSET); 386b2b9762fSSantosh Shilimkar else 387b2b9762fSSantosh Shilimkar __raw_writel(0, sar_base + OMAP_TYPE_OFFSET); 388b2b9762fSSantosh Shilimkar 3895e94c6e3SSantosh Shilimkar save_l2x0_context(); 3905e94c6e3SSantosh Shilimkar 391b2b9762fSSantosh Shilimkar return 0; 392b2b9762fSSantosh Shilimkar } 393b2b9762fSSantosh Shilimkar 394b2b9762fSSantosh Shilimkar #endif 395