1 /* 2 * OMAP2+ DMA driver 3 * 4 * Copyright (C) 2003 - 2008 Nokia Corporation 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 7 * Graphics DMA and LCD DMA graphics tranformations 8 * by Imre Deak <imre.deak@nokia.com> 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. 10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. 11 * 12 * Copyright (C) 2009 Texas Instruments 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 14 * 15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 16 * Converted DMA library into platform driver 17 * - G, Manjunath Kondaiah <manjugk@ti.com> 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 */ 23 24 #include <linux/err.h> 25 #include <linux/io.h> 26 #include <linux/slab.h> 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/device.h> 30 31 #include <plat-omap/dma-omap.h> 32 33 #include "omap_hwmod.h" 34 #include "omap_device.h" 35 36 #define OMAP2_DMA_STRIDE 0x60 37 38 static u32 errata; 39 static u8 dma_stride; 40 41 static struct omap_dma_dev_attr *d; 42 43 static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end; 44 45 static u16 reg_map[] = { 46 [REVISION] = 0x00, 47 [GCR] = 0x78, 48 [IRQSTATUS_L0] = 0x08, 49 [IRQSTATUS_L1] = 0x0c, 50 [IRQSTATUS_L2] = 0x10, 51 [IRQSTATUS_L3] = 0x14, 52 [IRQENABLE_L0] = 0x18, 53 [IRQENABLE_L1] = 0x1c, 54 [IRQENABLE_L2] = 0x20, 55 [IRQENABLE_L3] = 0x24, 56 [SYSSTATUS] = 0x28, 57 [OCP_SYSCONFIG] = 0x2c, 58 [CAPS_0] = 0x64, 59 [CAPS_2] = 0x6c, 60 [CAPS_3] = 0x70, 61 [CAPS_4] = 0x74, 62 63 /* Common register offsets */ 64 [CCR] = 0x80, 65 [CLNK_CTRL] = 0x84, 66 [CICR] = 0x88, 67 [CSR] = 0x8c, 68 [CSDP] = 0x90, 69 [CEN] = 0x94, 70 [CFN] = 0x98, 71 [CSEI] = 0xa4, 72 [CSFI] = 0xa8, 73 [CDEI] = 0xac, 74 [CDFI] = 0xb0, 75 [CSAC] = 0xb4, 76 [CDAC] = 0xb8, 77 78 /* Channel specific register offsets */ 79 [CSSA] = 0x9c, 80 [CDSA] = 0xa0, 81 [CCEN] = 0xbc, 82 [CCFN] = 0xc0, 83 [COLOR] = 0xc4, 84 85 /* OMAP4 specific registers */ 86 [CDP] = 0xd0, 87 [CNDP] = 0xd4, 88 [CCDN] = 0xd8, 89 }; 90 91 static void __iomem *dma_base; 92 static inline void dma_write(u32 val, int reg, int lch) 93 { 94 u8 stride; 95 u32 offset; 96 97 stride = (reg >= dma_common_ch_start) ? dma_stride : 0; 98 offset = reg_map[reg] + (stride * lch); 99 __raw_writel(val, dma_base + offset); 100 } 101 102 static inline u32 dma_read(int reg, int lch) 103 { 104 u8 stride; 105 u32 offset, val; 106 107 stride = (reg >= dma_common_ch_start) ? dma_stride : 0; 108 offset = reg_map[reg] + (stride * lch); 109 val = __raw_readl(dma_base + offset); 110 return val; 111 } 112 113 static inline void omap2_disable_irq_lch(int lch) 114 { 115 u32 val; 116 117 val = dma_read(IRQENABLE_L0, lch); 118 val &= ~(1 << lch); 119 dma_write(val, IRQENABLE_L0, lch); 120 } 121 122 static void omap2_clear_dma(int lch) 123 { 124 int i = dma_common_ch_start; 125 126 for (; i <= dma_common_ch_end; i += 1) 127 dma_write(0, i, lch); 128 } 129 130 static void omap2_show_dma_caps(void) 131 { 132 u8 revision = dma_read(REVISION, 0) & 0xff; 133 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 134 revision >> 4, revision & 0xf); 135 return; 136 } 137 138 static u32 configure_dma_errata(void) 139 { 140 141 /* 142 * Errata applicable for OMAP2430ES1.0 and all omap2420 143 * 144 * I. 145 * Erratum ID: Not Available 146 * Inter Frame DMA buffering issue DMA will wrongly 147 * buffer elements if packing and bursting is enabled. This might 148 * result in data gets stalled in FIFO at the end of the block. 149 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to 150 * guarantee no data will stay in the DMA FIFO in case inter frame 151 * buffering occurs 152 * 153 * II. 154 * Erratum ID: Not Available 155 * DMA may hang when several channels are used in parallel 156 * In the following configuration, DMA channel hanging can occur: 157 * a. Channel i, hardware synchronized, is enabled 158 * b. Another channel (Channel x), software synchronized, is enabled. 159 * c. Channel i is disabled before end of transfer 160 * d. Channel i is reenabled. 161 * e. Steps 1 to 4 are repeated a certain number of times. 162 * f. A third channel (Channel y), software synchronized, is enabled. 163 * Channel x and Channel y may hang immediately after step 'f'. 164 * Workaround: 165 * For any channel used - make sure NextLCH_ID is set to the value j. 166 */ 167 if (cpu_is_omap2420() || (cpu_is_omap2430() && 168 (omap_type() == OMAP2430_REV_ES1_0))) { 169 170 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING); 171 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS); 172 } 173 174 /* 175 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled 176 * after a transaction error. 177 * Workaround: SW should explicitely disable the channel. 178 */ 179 if (cpu_class_is_omap2()) 180 SET_DMA_ERRATA(DMA_ERRATA_i378); 181 182 /* 183 * Erratum ID: i541: sDMA FIFO draining does not finish 184 * If sDMA channel is disabled on the fly, sDMA enters standby even 185 * through FIFO Drain is still in progress 186 * Workaround: Put sDMA in NoStandby more before a logical channel is 187 * disabled, then put it back to SmartStandby right after the channel 188 * finishes FIFO draining. 189 */ 190 if (cpu_is_omap34xx()) 191 SET_DMA_ERRATA(DMA_ERRATA_i541); 192 193 /* 194 * Erratum ID: i88 : Special programming model needed to disable DMA 195 * before end of block. 196 * Workaround: software must ensure that the DMA is configured in No 197 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01") 198 */ 199 if (omap_type() == OMAP3430_REV_ES1_0) 200 SET_DMA_ERRATA(DMA_ERRATA_i88); 201 202 /* 203 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is 204 * read before the DMA controller finished disabling the channel. 205 */ 206 SET_DMA_ERRATA(DMA_ERRATA_3_3); 207 208 /* 209 * Erratum ID: Not Available 210 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared 211 * after secure sram context save and restore. 212 * Work around: Hence we need to manually clear those IRQs to avoid 213 * spurious interrupts. This affects only secure devices. 214 */ 215 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 216 SET_DMA_ERRATA(DMA_ROMCODE_BUG); 217 218 return errata; 219 } 220 221 /* One time initializations */ 222 static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused) 223 { 224 struct platform_device *pdev; 225 struct omap_system_dma_plat_info *p; 226 struct resource *mem; 227 char *name = "omap_dma_system"; 228 229 dma_stride = OMAP2_DMA_STRIDE; 230 dma_common_ch_start = CSDP; 231 232 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL); 233 if (!p) { 234 pr_err("%s: Unable to allocate pdata for %s:%s\n", 235 __func__, name, oh->name); 236 return -ENOMEM; 237 } 238 239 p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr; 240 p->disable_irq_lch = omap2_disable_irq_lch; 241 p->show_dma_caps = omap2_show_dma_caps; 242 p->clear_dma = omap2_clear_dma; 243 p->dma_write = dma_write; 244 p->dma_read = dma_read; 245 246 p->clear_lch_regs = NULL; 247 248 p->errata = configure_dma_errata(); 249 250 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0); 251 kfree(p); 252 if (IS_ERR(pdev)) { 253 pr_err("%s: Can't build omap_device for %s:%s.\n", 254 __func__, name, oh->name); 255 return PTR_ERR(pdev); 256 } 257 258 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 259 if (!mem) { 260 dev_err(&pdev->dev, "%s: no mem resource\n", __func__); 261 return -EINVAL; 262 } 263 dma_base = ioremap(mem->start, resource_size(mem)); 264 if (!dma_base) { 265 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); 266 return -ENOMEM; 267 } 268 269 d = oh->dev_attr; 270 d->chan = kzalloc(sizeof(struct omap_dma_lch) * 271 (d->lch_count), GFP_KERNEL); 272 273 if (!d->chan) { 274 dev_err(&pdev->dev, "%s: kzalloc fail\n", __func__); 275 return -ENOMEM; 276 } 277 278 /* Check the capabilities register for descriptor loading feature */ 279 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) 280 dma_common_ch_end = CCDN; 281 else 282 dma_common_ch_end = CCFN; 283 284 return 0; 285 } 286 287 static int __init omap2_system_dma_init(void) 288 { 289 return omap_hwmod_for_each_by_class("dma", 290 omap2_system_dma_init_dev, NULL); 291 } 292 arch_initcall(omap2_system_dma_init); 293