1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-omap2/cpuidle34xx.c 4 * 5 * OMAP3 CPU IDLE Routines 6 * 7 * Copyright (C) 2008 Texas Instruments, Inc. 8 * Rajendra Nayak <rnayak@ti.com> 9 * 10 * Copyright (C) 2007 Texas Instruments, Inc. 11 * Karthik Dasu <karthik-dp@ti.com> 12 * 13 * Copyright (C) 2006 Nokia Corporation 14 * Tony Lindgren <tony@atomide.com> 15 * 16 * Copyright (C) 2005 Texas Instruments, Inc. 17 * Richard Woodruff <r-woodruff2@ti.com> 18 * 19 * Based on pm.c for omap2 20 */ 21 22 #include <linux/sched.h> 23 #include <linux/cpuidle.h> 24 #include <linux/export.h> 25 #include <linux/cpu_pm.h> 26 #include <asm/cpuidle.h> 27 28 #include "powerdomain.h" 29 #include "clockdomain.h" 30 31 #include "pm.h" 32 #include "control.h" 33 #include "common.h" 34 #include "soc.h" 35 36 /* Mach specific information to be recorded in the C-state driver_data */ 37 struct omap3_idle_statedata { 38 u8 mpu_state; 39 u8 core_state; 40 u8 per_min_state; 41 u8 flags; 42 }; 43 44 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; 45 46 /* 47 * Possible flag bits for struct omap3_idle_statedata.flags: 48 * 49 * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go 50 * inactive. This in turn prevents the MPU DPLL from entering autoidle 51 * mode, so wakeup latency is greatly reduced, at the cost of additional 52 * energy consumption. This also prevents the CORE clockdomain from 53 * entering idle. 54 */ 55 #define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0) 56 57 /* 58 * Prevent PER OFF if CORE is not in RETention or OFF as this would 59 * disable PER wakeups completely. 60 */ 61 static struct omap3_idle_statedata omap3_idle_data[] = { 62 { 63 .mpu_state = PWRDM_POWER_ON, 64 .core_state = PWRDM_POWER_ON, 65 /* In C1 do not allow PER state lower than CORE state */ 66 .per_min_state = PWRDM_POWER_ON, 67 .flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE, 68 }, 69 { 70 .mpu_state = PWRDM_POWER_ON, 71 .core_state = PWRDM_POWER_ON, 72 .per_min_state = PWRDM_POWER_RET, 73 }, 74 { 75 .mpu_state = PWRDM_POWER_RET, 76 .core_state = PWRDM_POWER_ON, 77 .per_min_state = PWRDM_POWER_RET, 78 }, 79 { 80 .mpu_state = PWRDM_POWER_OFF, 81 .core_state = PWRDM_POWER_ON, 82 .per_min_state = PWRDM_POWER_RET, 83 }, 84 { 85 .mpu_state = PWRDM_POWER_RET, 86 .core_state = PWRDM_POWER_RET, 87 .per_min_state = PWRDM_POWER_OFF, 88 }, 89 { 90 .mpu_state = PWRDM_POWER_OFF, 91 .core_state = PWRDM_POWER_RET, 92 .per_min_state = PWRDM_POWER_OFF, 93 }, 94 { 95 .mpu_state = PWRDM_POWER_OFF, 96 .core_state = PWRDM_POWER_OFF, 97 .per_min_state = PWRDM_POWER_OFF, 98 }, 99 }; 100 101 /** 102 * omap3_enter_idle - Programs OMAP3 to enter the specified state 103 * @dev: cpuidle device 104 * @drv: cpuidle driver 105 * @index: the index of state to be entered 106 */ 107 static int omap3_enter_idle(struct cpuidle_device *dev, 108 struct cpuidle_driver *drv, 109 int index) 110 { 111 struct omap3_idle_statedata *cx = &omap3_idle_data[index]; 112 int error; 113 114 if (omap_irq_pending() || need_resched()) 115 goto return_sleep_time; 116 117 /* Deny idle for C1 */ 118 if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) { 119 clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]); 120 } else { 121 pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); 122 pwrdm_set_next_pwrst(core_pd, cx->core_state); 123 } 124 125 /* 126 * Call idle CPU PM enter notifier chain so that 127 * VFP context is saved. 128 */ 129 if (cx->mpu_state == PWRDM_POWER_OFF) { 130 error = cpu_pm_enter(); 131 if (error) 132 goto out_clkdm_set; 133 } 134 135 /* Execute ARM wfi */ 136 ct_idle_enter(); 137 omap_sram_idle(); 138 ct_idle_exit(); 139 140 /* 141 * Call idle CPU PM enter notifier chain to restore 142 * VFP context. 143 */ 144 if (cx->mpu_state == PWRDM_POWER_OFF && 145 pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF) 146 cpu_pm_exit(); 147 148 out_clkdm_set: 149 /* Re-allow idle for C1 */ 150 if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) 151 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); 152 153 return_sleep_time: 154 155 return index; 156 } 157 158 /** 159 * next_valid_state - Find next valid C-state 160 * @dev: cpuidle device 161 * @drv: cpuidle driver 162 * @index: Index of currently selected c-state 163 * 164 * If the state corresponding to index is valid, index is returned back 165 * to the caller. Else, this function searches for a lower c-state which is 166 * still valid (as defined in omap3_power_states[]) and returns its index. 167 * 168 * A state is valid if the 'valid' field is enabled and 169 * if it satisfies the enable_off_mode condition. 170 */ 171 static int next_valid_state(struct cpuidle_device *dev, 172 struct cpuidle_driver *drv, int index) 173 { 174 struct omap3_idle_statedata *cx = &omap3_idle_data[index]; 175 u32 mpu_deepest_state = PWRDM_POWER_RET; 176 u32 core_deepest_state = PWRDM_POWER_RET; 177 int idx; 178 int next_index = 0; /* C1 is the default value */ 179 180 if (enable_off_mode) { 181 mpu_deepest_state = PWRDM_POWER_OFF; 182 /* 183 * Erratum i583: valable for ES rev < Es1.2 on 3630. 184 * CORE OFF mode is not supported in a stable form, restrict 185 * instead the CORE state to RET. 186 */ 187 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) 188 core_deepest_state = PWRDM_POWER_OFF; 189 } 190 191 /* Check if current state is valid */ 192 if ((cx->mpu_state >= mpu_deepest_state) && 193 (cx->core_state >= core_deepest_state)) 194 return index; 195 196 /* 197 * Drop to next valid state. 198 * Start search from the next (lower) state. 199 */ 200 for (idx = index - 1; idx >= 0; idx--) { 201 cx = &omap3_idle_data[idx]; 202 if ((cx->mpu_state >= mpu_deepest_state) && 203 (cx->core_state >= core_deepest_state)) { 204 next_index = idx; 205 break; 206 } 207 } 208 209 return next_index; 210 } 211 212 /** 213 * omap3_enter_idle_bm - Checks for any bus activity 214 * @dev: cpuidle device 215 * @drv: cpuidle driver 216 * @index: array index of target state to be programmed 217 * 218 * This function checks for any pending activity and then programs 219 * the device to the specified or a safer state. 220 */ 221 static int omap3_enter_idle_bm(struct cpuidle_device *dev, 222 struct cpuidle_driver *drv, 223 int index) 224 { 225 int new_state_idx, ret; 226 u8 per_next_state, per_saved_state; 227 struct omap3_idle_statedata *cx; 228 229 /* 230 * Use only C1 if CAM is active. 231 * CAM does not have wakeup capability in OMAP3. 232 */ 233 if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON) 234 new_state_idx = drv->safe_state_index; 235 else 236 new_state_idx = next_valid_state(dev, drv, index); 237 238 /* 239 * FIXME: we currently manage device-specific idle states 240 * for PER and CORE in combination with CPU-specific 241 * idle states. This is wrong, and device-specific 242 * idle management needs to be separated out into 243 * its own code. 244 */ 245 246 /* Program PER state */ 247 cx = &omap3_idle_data[new_state_idx]; 248 249 per_next_state = pwrdm_read_next_pwrst(per_pd); 250 per_saved_state = per_next_state; 251 if (per_next_state < cx->per_min_state) { 252 per_next_state = cx->per_min_state; 253 pwrdm_set_next_pwrst(per_pd, per_next_state); 254 } 255 256 ret = omap3_enter_idle(dev, drv, new_state_idx); 257 258 /* Restore original PER state if it was modified */ 259 if (per_next_state != per_saved_state) 260 pwrdm_set_next_pwrst(per_pd, per_saved_state); 261 262 return ret; 263 } 264 265 static struct cpuidle_driver omap3_idle_driver = { 266 .name = "omap3_idle", 267 .owner = THIS_MODULE, 268 .states = { 269 { 270 .flags = CPUIDLE_FLAG_RCU_IDLE, 271 .enter = omap3_enter_idle_bm, 272 .exit_latency = 2 + 2, 273 .target_residency = 5, 274 .name = "C1", 275 .desc = "MPU ON + CORE ON", 276 }, 277 { 278 .flags = CPUIDLE_FLAG_RCU_IDLE, 279 .enter = omap3_enter_idle_bm, 280 .exit_latency = 10 + 10, 281 .target_residency = 30, 282 .name = "C2", 283 .desc = "MPU ON + CORE ON", 284 }, 285 { 286 .flags = CPUIDLE_FLAG_RCU_IDLE, 287 .enter = omap3_enter_idle_bm, 288 .exit_latency = 50 + 50, 289 .target_residency = 300, 290 .name = "C3", 291 .desc = "MPU RET + CORE ON", 292 }, 293 { 294 .flags = CPUIDLE_FLAG_RCU_IDLE, 295 .enter = omap3_enter_idle_bm, 296 .exit_latency = 1500 + 1800, 297 .target_residency = 4000, 298 .name = "C4", 299 .desc = "MPU OFF + CORE ON", 300 }, 301 { 302 .flags = CPUIDLE_FLAG_RCU_IDLE, 303 .enter = omap3_enter_idle_bm, 304 .exit_latency = 2500 + 7500, 305 .target_residency = 12000, 306 .name = "C5", 307 .desc = "MPU RET + CORE RET", 308 }, 309 { 310 .flags = CPUIDLE_FLAG_RCU_IDLE, 311 .enter = omap3_enter_idle_bm, 312 .exit_latency = 3000 + 8500, 313 .target_residency = 15000, 314 .name = "C6", 315 .desc = "MPU OFF + CORE RET", 316 }, 317 { 318 .flags = CPUIDLE_FLAG_RCU_IDLE, 319 .enter = omap3_enter_idle_bm, 320 .exit_latency = 10000 + 30000, 321 .target_residency = 30000, 322 .name = "C7", 323 .desc = "MPU OFF + CORE OFF", 324 }, 325 }, 326 .state_count = ARRAY_SIZE(omap3_idle_data), 327 .safe_state_index = 0, 328 }; 329 330 /* 331 * Numbers based on measurements made in October 2009 for PM optimized kernel 332 * with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP, 333 * and worst case latencies). 334 */ 335 static struct cpuidle_driver omap3430_idle_driver = { 336 .name = "omap3430_idle", 337 .owner = THIS_MODULE, 338 .states = { 339 { 340 .flags = CPUIDLE_FLAG_RCU_IDLE, 341 .enter = omap3_enter_idle_bm, 342 .exit_latency = 110 + 162, 343 .target_residency = 5, 344 .name = "C1", 345 .desc = "MPU ON + CORE ON", 346 }, 347 { 348 .flags = CPUIDLE_FLAG_RCU_IDLE, 349 .enter = omap3_enter_idle_bm, 350 .exit_latency = 106 + 180, 351 .target_residency = 309, 352 .name = "C2", 353 .desc = "MPU ON + CORE ON", 354 }, 355 { 356 .flags = CPUIDLE_FLAG_RCU_IDLE, 357 .enter = omap3_enter_idle_bm, 358 .exit_latency = 107 + 410, 359 .target_residency = 46057, 360 .name = "C3", 361 .desc = "MPU RET + CORE ON", 362 }, 363 { 364 .flags = CPUIDLE_FLAG_RCU_IDLE, 365 .enter = omap3_enter_idle_bm, 366 .exit_latency = 121 + 3374, 367 .target_residency = 46057, 368 .name = "C4", 369 .desc = "MPU OFF + CORE ON", 370 }, 371 { 372 .flags = CPUIDLE_FLAG_RCU_IDLE, 373 .enter = omap3_enter_idle_bm, 374 .exit_latency = 855 + 1146, 375 .target_residency = 46057, 376 .name = "C5", 377 .desc = "MPU RET + CORE RET", 378 }, 379 { 380 .flags = CPUIDLE_FLAG_RCU_IDLE, 381 .enter = omap3_enter_idle_bm, 382 .exit_latency = 7580 + 4134, 383 .target_residency = 484329, 384 .name = "C6", 385 .desc = "MPU OFF + CORE RET", 386 }, 387 { 388 .flags = CPUIDLE_FLAG_RCU_IDLE, 389 .enter = omap3_enter_idle_bm, 390 .exit_latency = 7505 + 15274, 391 .target_residency = 484329, 392 .name = "C7", 393 .desc = "MPU OFF + CORE OFF", 394 }, 395 }, 396 .state_count = ARRAY_SIZE(omap3_idle_data), 397 .safe_state_index = 0, 398 }; 399 400 /* Public functions */ 401 402 /** 403 * omap3_idle_init - Init routine for OMAP3 idle 404 * 405 * Registers the OMAP3 specific cpuidle driver to the cpuidle 406 * framework with the valid set of states. 407 */ 408 int __init omap3_idle_init(void) 409 { 410 mpu_pd = pwrdm_lookup("mpu_pwrdm"); 411 core_pd = pwrdm_lookup("core_pwrdm"); 412 per_pd = pwrdm_lookup("per_pwrdm"); 413 cam_pd = pwrdm_lookup("cam_pwrdm"); 414 415 if (!mpu_pd || !core_pd || !per_pd || !cam_pd) 416 return -ENODEV; 417 418 if (cpu_is_omap3430()) 419 return cpuidle_register(&omap3430_idle_driver, NULL); 420 else 421 return cpuidle_register(&omap3_idle_driver, NULL); 422 } 423