1 /* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007, 2012 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #undef DEBUG 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 #include <linux/of_address.h> 18 #include <linux/regmap.h> 19 #include <linux/mfd/syscon.h> 20 21 #include "soc.h" 22 #include "iomap.h" 23 #include "common.h" 24 #include "cm-regbits-34xx.h" 25 #include "prm-regbits-34xx.h" 26 #include "prm3xxx.h" 27 #include "cm3xxx.h" 28 #include "sdrc.h" 29 #include "pm.h" 30 #include "control.h" 31 #include "clock.h" 32 33 /* Used by omap3_ctrl_save_padconf() */ 34 #define START_PADCONF_SAVE 0x2 35 #define PADCONF_SAVE_DONE 0x1 36 37 static void __iomem *omap2_ctrl_base; 38 static s16 omap2_ctrl_offset; 39 static void __iomem *omap4_ctrl_pad_base; 40 static struct regmap *omap2_ctrl_syscon; 41 42 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 43 struct omap3_scratchpad { 44 u32 boot_config_ptr; 45 u32 public_restore_ptr; 46 u32 secure_ram_restore_ptr; 47 u32 sdrc_module_semaphore; 48 u32 prcm_block_offset; 49 u32 sdrc_block_offset; 50 }; 51 52 struct omap3_scratchpad_prcm_block { 53 u32 prm_contents[2]; 54 u32 cm_contents[11]; 55 u32 prcm_block_size; 56 }; 57 58 struct omap3_scratchpad_sdrc_block { 59 u16 sysconfig; 60 u16 cs_cfg; 61 u16 sharing; 62 u16 err_type; 63 u32 dll_a_ctrl; 64 u32 dll_b_ctrl; 65 u32 power; 66 u32 cs_0; 67 u32 mcfg_0; 68 u16 mr_0; 69 u16 emr_1_0; 70 u16 emr_2_0; 71 u16 emr_3_0; 72 u32 actim_ctrla_0; 73 u32 actim_ctrlb_0; 74 u32 rfr_ctrl_0; 75 u32 cs_1; 76 u32 mcfg_1; 77 u16 mr_1; 78 u16 emr_1_1; 79 u16 emr_2_1; 80 u16 emr_3_1; 81 u32 actim_ctrla_1; 82 u32 actim_ctrlb_1; 83 u32 rfr_ctrl_1; 84 u16 dcdl_1_ctrl; 85 u16 dcdl_2_ctrl; 86 u32 flags; 87 u32 block_size; 88 }; 89 90 void *omap3_secure_ram_storage; 91 92 /* 93 * This is used to store ARM registers in SDRAM before attempting 94 * an MPU OFF. The save and restore happens from the SRAM sleep code. 95 * The address is stored in scratchpad, so that it can be used 96 * during the restore path. 97 */ 98 u32 omap3_arm_context[128]; 99 100 struct omap3_control_regs { 101 u32 sysconfig; 102 u32 devconf0; 103 u32 mem_dftrw0; 104 u32 mem_dftrw1; 105 u32 msuspendmux_0; 106 u32 msuspendmux_1; 107 u32 msuspendmux_2; 108 u32 msuspendmux_3; 109 u32 msuspendmux_4; 110 u32 msuspendmux_5; 111 u32 sec_ctrl; 112 u32 devconf1; 113 u32 csirxfe; 114 u32 iva2_bootaddr; 115 u32 iva2_bootmod; 116 u32 debobs_0; 117 u32 debobs_1; 118 u32 debobs_2; 119 u32 debobs_3; 120 u32 debobs_4; 121 u32 debobs_5; 122 u32 debobs_6; 123 u32 debobs_7; 124 u32 debobs_8; 125 u32 prog_io0; 126 u32 prog_io1; 127 u32 dss_dpll_spreading; 128 u32 core_dpll_spreading; 129 u32 per_dpll_spreading; 130 u32 usbhost_dpll_spreading; 131 u32 pbias_lite; 132 u32 temp_sensor; 133 u32 sramldo4; 134 u32 sramldo5; 135 u32 csi; 136 u32 padconf_sys_nirq; 137 }; 138 139 static struct omap3_control_regs control_context; 140 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 141 142 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) 143 144 void __init omap2_set_globals_control(void __iomem *ctrl, 145 void __iomem *ctrl_pad) 146 { 147 omap2_ctrl_base = ctrl; 148 omap4_ctrl_pad_base = ctrl_pad; 149 } 150 151 u8 omap_ctrl_readb(u16 offset) 152 { 153 u32 val; 154 u8 byte_offset = offset & 0x3; 155 156 val = omap_ctrl_readl(offset); 157 158 return (val >> (byte_offset * 8)) & 0xff; 159 } 160 161 u16 omap_ctrl_readw(u16 offset) 162 { 163 u32 val; 164 u16 byte_offset = offset & 0x2; 165 166 val = omap_ctrl_readl(offset); 167 168 return (val >> (byte_offset * 8)) & 0xffff; 169 } 170 171 u32 omap_ctrl_readl(u16 offset) 172 { 173 u32 val; 174 175 offset &= 0xfffc; 176 if (!omap2_ctrl_syscon) 177 val = readl_relaxed(omap2_ctrl_base + offset); 178 else 179 regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset, 180 &val); 181 182 return val; 183 } 184 185 void omap_ctrl_writeb(u8 val, u16 offset) 186 { 187 u32 tmp; 188 u8 byte_offset = offset & 0x3; 189 190 tmp = omap_ctrl_readl(offset); 191 192 tmp &= 0xffffffff ^ (0xff << (byte_offset * 8)); 193 tmp |= val << (byte_offset * 8); 194 195 omap_ctrl_writel(tmp, offset); 196 } 197 198 void omap_ctrl_writew(u16 val, u16 offset) 199 { 200 u32 tmp; 201 u8 byte_offset = offset & 0x2; 202 203 tmp = omap_ctrl_readl(offset); 204 205 tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8)); 206 tmp |= val << (byte_offset * 8); 207 208 omap_ctrl_writel(tmp, offset); 209 } 210 211 void omap_ctrl_writel(u32 val, u16 offset) 212 { 213 offset &= 0xfffc; 214 if (!omap2_ctrl_syscon) 215 writel_relaxed(val, omap2_ctrl_base + offset); 216 else 217 regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset, 218 val); 219 } 220 221 /* 222 * On OMAP4 control pad are not addressable from control 223 * core base. So the common omap_ctrl_read/write APIs breaks 224 * Hence export separate APIs to manage the omap4 pad control 225 * registers. This APIs will work only for OMAP4 226 */ 227 228 u32 omap4_ctrl_pad_readl(u16 offset) 229 { 230 return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); 231 } 232 233 void omap4_ctrl_pad_writel(u32 val, u16 offset) 234 { 235 writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); 236 } 237 238 #ifdef CONFIG_ARCH_OMAP3 239 240 /** 241 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 242 * @bootmode: 8-bit value to pass to some boot code 243 * 244 * Set the bootmode in the scratchpad RAM. This is used after the 245 * system restarts. Not sure what actually uses this - it may be the 246 * bootloader, rather than the boot ROM - contrary to the preserved 247 * comment below. No return value. 248 */ 249 void omap3_ctrl_write_boot_mode(u8 bootmode) 250 { 251 u32 l; 252 253 l = ('B' << 24) | ('M' << 16) | bootmode; 254 255 /* 256 * Reserve the first word in scratchpad for communicating 257 * with the boot ROM. A pointer to a data structure 258 * describing the boot process can be stored there, 259 * cf. OMAP34xx TRM, Initialization / Software Booting 260 * Configuration. 261 * 262 * XXX This should use some omap_ctrl_writel()-type function 263 */ 264 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 265 } 266 267 #endif 268 269 /** 270 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor 271 * @bootaddr: physical address of the boot loader 272 * 273 * Set boot address for the boot loader of a supported processor 274 * when a power ON sequence occurs. 275 */ 276 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) 277 { 278 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : 279 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : 280 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 281 soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 282 0; 283 284 if (!offset) { 285 pr_err("%s: unsupported omap type\n", __func__); 286 return; 287 } 288 289 omap_ctrl_writel(bootaddr, offset); 290 } 291 292 /** 293 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor 294 * @bootmode: 8-bit value to pass to some boot code 295 * 296 * Sets boot mode for the boot loader of a supported processor 297 * when a power ON sequence occurs. 298 */ 299 void omap_ctrl_write_dsp_boot_mode(u8 bootmode) 300 { 301 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : 302 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : 303 0; 304 305 if (!offset) { 306 pr_err("%s: unsupported omap type\n", __func__); 307 return; 308 } 309 310 omap_ctrl_writel(bootmode, offset); 311 } 312 313 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 314 /* 315 * Clears the scratchpad contents in case of cold boot- 316 * called during bootup 317 */ 318 void omap3_clear_scratchpad_contents(void) 319 { 320 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 321 void __iomem *v_addr; 322 u32 offset = 0; 323 324 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 325 if (omap3xxx_prm_clear_global_cold_reset()) { 326 for ( ; offset <= max_offset; offset += 0x4) 327 writel_relaxed(0x0, (v_addr + offset)); 328 } 329 } 330 331 /* Populate the scratchpad structure with restore structure */ 332 void omap3_save_scratchpad_contents(void) 333 { 334 void __iomem *scratchpad_address; 335 u32 arm_context_addr; 336 struct omap3_scratchpad scratchpad_contents; 337 struct omap3_scratchpad_prcm_block prcm_block_contents; 338 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 339 340 /* 341 * Populate the Scratchpad contents 342 * 343 * The "get_*restore_pointer" functions are used to provide a 344 * physical restore address where the ROM code jumps while waking 345 * up from MPU OFF/OSWR state. 346 * The restore pointer is stored into the scratchpad. 347 */ 348 scratchpad_contents.boot_config_ptr = 0x0; 349 if (cpu_is_omap3630()) 350 scratchpad_contents.public_restore_ptr = 351 virt_to_phys(omap3_restore_3630); 352 else if (omap_rev() != OMAP3430_REV_ES3_0 && 353 omap_rev() != OMAP3430_REV_ES3_1 && 354 omap_rev() != OMAP3430_REV_ES3_1_2) 355 scratchpad_contents.public_restore_ptr = 356 virt_to_phys(omap3_restore); 357 else 358 scratchpad_contents.public_restore_ptr = 359 virt_to_phys(omap3_restore_es3); 360 361 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 362 scratchpad_contents.secure_ram_restore_ptr = 0x0; 363 else 364 scratchpad_contents.secure_ram_restore_ptr = 365 (u32) __pa(omap3_secure_ram_storage); 366 scratchpad_contents.sdrc_module_semaphore = 0x0; 367 scratchpad_contents.prcm_block_offset = 0x2C; 368 scratchpad_contents.sdrc_block_offset = 0x64; 369 370 /* Populate the PRCM block contents */ 371 omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); 372 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); 373 374 prcm_block_contents.prcm_block_size = 0x0; 375 376 /* Populate the SDRC block contents */ 377 sdrc_block_contents.sysconfig = 378 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 379 sdrc_block_contents.cs_cfg = 380 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 381 sdrc_block_contents.sharing = 382 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 383 sdrc_block_contents.err_type = 384 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 385 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 386 sdrc_block_contents.dll_b_ctrl = 0x0; 387 /* 388 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 389 * be programed to issue automatic self refresh on timeout 390 * of AUTO_CNT = 1 prior to any transition to OFF mode. 391 */ 392 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 393 && (omap_rev() >= OMAP3430_REV_ES3_0)) 394 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 395 ~(SDRC_POWER_AUTOCOUNT_MASK| 396 SDRC_POWER_CLKCTRL_MASK)) | 397 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 398 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 399 else 400 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 401 402 sdrc_block_contents.cs_0 = 0x0; 403 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 404 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 405 sdrc_block_contents.emr_1_0 = 0x0; 406 sdrc_block_contents.emr_2_0 = 0x0; 407 sdrc_block_contents.emr_3_0 = 0x0; 408 sdrc_block_contents.actim_ctrla_0 = 409 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 410 sdrc_block_contents.actim_ctrlb_0 = 411 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 412 sdrc_block_contents.rfr_ctrl_0 = 413 sdrc_read_reg(SDRC_RFR_CTRL_0); 414 sdrc_block_contents.cs_1 = 0x0; 415 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 416 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 417 sdrc_block_contents.emr_1_1 = 0x0; 418 sdrc_block_contents.emr_2_1 = 0x0; 419 sdrc_block_contents.emr_3_1 = 0x0; 420 sdrc_block_contents.actim_ctrla_1 = 421 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 422 sdrc_block_contents.actim_ctrlb_1 = 423 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 424 sdrc_block_contents.rfr_ctrl_1 = 425 sdrc_read_reg(SDRC_RFR_CTRL_1); 426 sdrc_block_contents.dcdl_1_ctrl = 0x0; 427 sdrc_block_contents.dcdl_2_ctrl = 0x0; 428 sdrc_block_contents.flags = 0x0; 429 sdrc_block_contents.block_size = 0x0; 430 431 arm_context_addr = virt_to_phys(omap3_arm_context); 432 433 /* Copy all the contents to the scratchpad location */ 434 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 435 memcpy_toio(scratchpad_address, &scratchpad_contents, 436 sizeof(scratchpad_contents)); 437 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 438 memcpy_toio(scratchpad_address + 439 scratchpad_contents.prcm_block_offset, 440 &prcm_block_contents, sizeof(prcm_block_contents)); 441 memcpy_toio(scratchpad_address + 442 scratchpad_contents.sdrc_block_offset, 443 &sdrc_block_contents, sizeof(sdrc_block_contents)); 444 /* 445 * Copies the address of the location in SDRAM where ARM 446 * registers get saved during a MPU OFF transition. 447 */ 448 memcpy_toio(scratchpad_address + 449 scratchpad_contents.sdrc_block_offset + 450 sizeof(sdrc_block_contents), &arm_context_addr, 4); 451 } 452 453 void omap3_control_save_context(void) 454 { 455 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 456 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 457 control_context.mem_dftrw0 = 458 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 459 control_context.mem_dftrw1 = 460 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 461 control_context.msuspendmux_0 = 462 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 463 control_context.msuspendmux_1 = 464 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 465 control_context.msuspendmux_2 = 466 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 467 control_context.msuspendmux_3 = 468 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 469 control_context.msuspendmux_4 = 470 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 471 control_context.msuspendmux_5 = 472 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 473 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 474 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 475 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 476 control_context.iva2_bootaddr = 477 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 478 control_context.iva2_bootmod = 479 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 480 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 481 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 482 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 483 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 484 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 485 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 486 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 487 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 488 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 489 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 490 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 491 control_context.dss_dpll_spreading = 492 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 493 control_context.core_dpll_spreading = 494 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 495 control_context.per_dpll_spreading = 496 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 497 control_context.usbhost_dpll_spreading = 498 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 499 control_context.pbias_lite = 500 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 501 control_context.temp_sensor = 502 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 503 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 504 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 505 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 506 control_context.padconf_sys_nirq = 507 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 508 } 509 510 void omap3_control_restore_context(void) 511 { 512 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 513 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 514 omap_ctrl_writel(control_context.mem_dftrw0, 515 OMAP343X_CONTROL_MEM_DFTRW0); 516 omap_ctrl_writel(control_context.mem_dftrw1, 517 OMAP343X_CONTROL_MEM_DFTRW1); 518 omap_ctrl_writel(control_context.msuspendmux_0, 519 OMAP2_CONTROL_MSUSPENDMUX_0); 520 omap_ctrl_writel(control_context.msuspendmux_1, 521 OMAP2_CONTROL_MSUSPENDMUX_1); 522 omap_ctrl_writel(control_context.msuspendmux_2, 523 OMAP2_CONTROL_MSUSPENDMUX_2); 524 omap_ctrl_writel(control_context.msuspendmux_3, 525 OMAP2_CONTROL_MSUSPENDMUX_3); 526 omap_ctrl_writel(control_context.msuspendmux_4, 527 OMAP2_CONTROL_MSUSPENDMUX_4); 528 omap_ctrl_writel(control_context.msuspendmux_5, 529 OMAP2_CONTROL_MSUSPENDMUX_5); 530 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 531 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 532 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 533 omap_ctrl_writel(control_context.iva2_bootaddr, 534 OMAP343X_CONTROL_IVA2_BOOTADDR); 535 omap_ctrl_writel(control_context.iva2_bootmod, 536 OMAP343X_CONTROL_IVA2_BOOTMOD); 537 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 538 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 539 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 540 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 541 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 542 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 543 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 544 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 545 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 546 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 547 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 548 omap_ctrl_writel(control_context.dss_dpll_spreading, 549 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 550 omap_ctrl_writel(control_context.core_dpll_spreading, 551 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 552 omap_ctrl_writel(control_context.per_dpll_spreading, 553 OMAP343X_CONTROL_PER_DPLL_SPREADING); 554 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 555 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 556 omap_ctrl_writel(control_context.pbias_lite, 557 OMAP343X_CONTROL_PBIAS_LITE); 558 omap_ctrl_writel(control_context.temp_sensor, 559 OMAP343X_CONTROL_TEMP_SENSOR); 560 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 561 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 562 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 563 omap_ctrl_writel(control_context.padconf_sys_nirq, 564 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 565 } 566 567 void omap3630_ctrl_disable_rta(void) 568 { 569 if (!cpu_is_omap3630()) 570 return; 571 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 572 } 573 574 /** 575 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 576 * 577 * Tell the SCM to start saving the padconf registers, then wait for 578 * the process to complete. Returns 0 unconditionally, although it 579 * should also eventually be able to return -ETIMEDOUT, if the save 580 * does not complete. 581 * 582 * XXX This function is missing a timeout. What should it be? 583 */ 584 int omap3_ctrl_save_padconf(void) 585 { 586 u32 cpo; 587 588 /* Save the padconf registers */ 589 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 590 cpo |= START_PADCONF_SAVE; 591 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 592 593 /* wait for the save to complete */ 594 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 595 & PADCONF_SAVE_DONE)) 596 udelay(1); 597 598 return 0; 599 } 600 601 /** 602 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle 603 * 604 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to 605 * force disable IVA2 so that it does not prevent any low-power states. 606 */ 607 static void __init omap3_ctrl_set_iva_bootmode_idle(void) 608 { 609 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 610 OMAP343X_CONTROL_IVA2_BOOTMOD); 611 } 612 613 /** 614 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle 615 * 616 * Sets up the pads controlling the stacked modem in such way that the 617 * device can enter idle. 618 */ 619 static void __init omap3_ctrl_setup_d2d_padconf(void) 620 { 621 u16 mask, padconf; 622 623 /* 624 * In a stand alone OMAP3430 where there is not a stacked 625 * modem for the D2D Idle Ack and D2D MStandby must be pulled 626 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 627 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. 628 */ 629 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 630 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 631 padconf |= mask; 632 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 633 634 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 635 padconf |= mask; 636 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 637 } 638 639 /** 640 * omap3_ctrl_init - does static initializations for control module 641 * 642 * Initializes system control module. This sets up the sysconfig autoidle, 643 * and sets up modem and iva2 so that they can be idled properly. 644 */ 645 void __init omap3_ctrl_init(void) 646 { 647 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 648 649 omap3_ctrl_set_iva_bootmode_idle(); 650 651 omap3_ctrl_setup_d2d_padconf(); 652 } 653 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 654 655 struct control_init_data { 656 int index; 657 s16 offset; 658 }; 659 660 static struct control_init_data ctrl_data = { 661 .index = TI_CLKM_CTRL, 662 }; 663 664 static const struct control_init_data omap2_ctrl_data = { 665 .index = TI_CLKM_CTRL, 666 .offset = -OMAP2_CONTROL_GENERAL, 667 }; 668 669 static const struct of_device_id omap_scrm_dt_match_table[] = { 670 { .compatible = "ti,am3-scrm", .data = &ctrl_data }, 671 { .compatible = "ti,am4-scrm", .data = &ctrl_data }, 672 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, 673 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, 674 { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, 675 { } 676 }; 677 678 /** 679 * omap2_control_base_init - initialize iomappings for the control driver 680 * 681 * Detects and initializes the iomappings for the control driver, based 682 * on the DT data. Returns 0 in success, negative error value 683 * otherwise. 684 */ 685 int __init omap2_control_base_init(void) 686 { 687 struct device_node *np; 688 const struct of_device_id *match; 689 struct control_init_data *data; 690 691 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 692 data = (struct control_init_data *)match->data; 693 694 omap2_ctrl_base = of_iomap(np, 0); 695 if (!omap2_ctrl_base) 696 return -ENOMEM; 697 698 omap2_ctrl_offset = data->offset; 699 } 700 701 return 0; 702 } 703 704 /** 705 * omap_control_init - low level init for the control driver 706 * 707 * Initializes the low level clock infrastructure for control driver. 708 * Returns 0 in success, negative error value in failure. 709 */ 710 int __init omap_control_init(void) 711 { 712 struct device_node *np, *scm_conf; 713 const struct of_device_id *match; 714 const struct omap_prcm_init_data *data; 715 int ret; 716 struct regmap *syscon; 717 718 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 719 data = match->data; 720 721 /* 722 * Check if we have scm_conf node, if yes, use this to 723 * access clock registers. 724 */ 725 scm_conf = of_get_child_by_name(np, "scm_conf"); 726 727 if (scm_conf) { 728 syscon = syscon_node_to_regmap(scm_conf); 729 730 if (IS_ERR(syscon)) 731 return PTR_ERR(syscon); 732 733 omap2_ctrl_syscon = syscon; 734 735 if (of_get_child_by_name(scm_conf, "clocks")) { 736 ret = omap2_clk_provider_init(scm_conf, 737 data->index, 738 syscon, NULL); 739 if (ret) 740 return ret; 741 } 742 743 iounmap(omap2_ctrl_base); 744 omap2_ctrl_base = NULL; 745 } else { 746 /* No scm_conf found, direct access */ 747 ret = omap2_clk_provider_init(np, data->index, NULL, 748 omap2_ctrl_base); 749 if (ret) 750 return ret; 751 } 752 } 753 754 return 0; 755 } 756 757 /** 758 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers 759 * 760 * Legacy iomap init for clock provider. Needed only by legacy boot mode, 761 * where the base addresses are not parsed from DT, but still required 762 * by the clock driver to be setup properly. 763 */ 764 void __init omap3_control_legacy_iomap_init(void) 765 { 766 omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base); 767 } 768